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517 lines
13 KiB
C
517 lines
13 KiB
C
16 years ago
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/*
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* File: mcf5xxx.c
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* Purpose: Generic high-level routines for generic ColdFire processors
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*
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* Notes:
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*
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* License: All software covered by license agreement in -
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* docs/Freescale_Software_License.pdf
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*/
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#include "common.h"
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/********************************************************************/
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#define EXCEPTFMT "%s -- PC = %#08X\n"
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/********************************************************************/
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/*
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* This is the exception handler for all defined exceptions. Most
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* exceptions do nothing, but some of the more important ones are
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* handled to some extent.
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*
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* Called by asm_exception_handler
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*/
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void
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mcf5xxx_exception_handler (void *framep)
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{
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switch (MCF5XXX_RD_SF_FORMAT(framep))
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{
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case 4:
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case 5:
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case 6:
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case 7:
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break;
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default:
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printf(EXCEPTFMT,"Illegal stack type", MCF5XXX_SF_PC(framep));
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break;
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}
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switch (MCF5XXX_RD_SF_VECTOR(framep))
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{
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case 2:
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printf(EXCEPTFMT, "Access Error", MCF5XXX_SF_PC(framep));
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switch (MCF5XXX_RD_SF_FS(framep))
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{
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case 4:
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printf("Error on instruction fetch\n");
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break;
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case 8:
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printf("Error on operand write\n");
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break;
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case 9:
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printf("Attempted write to write-protected space\n");
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break;
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case 12:
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printf("Error on operand read\n");
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break;
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default:
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printf("Reserved Fault Status Encoding\n");
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break;
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}
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break;
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case 3:
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printf(EXCEPTFMT, "Address Error", MCF5XXX_SF_PC(framep));
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switch (MCF5XXX_RD_SF_FS(framep))
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{
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case 4:
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printf("Error on instruction fetch\n");
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break;
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case 8:
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printf("Error on operand write\n");
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break;
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case 9:
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printf("Attempted write to write-protected space\n");
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break;
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case 12:
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printf("Error on operand read\n");
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break;
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default:
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printf("Reserved Fault Status Encoding\n");
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break;
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}
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break;
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case 4:
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printf(EXCEPTFMT, "Illegal instruction", MCF5XXX_SF_PC(framep));
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break;
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case 8:
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printf(EXCEPTFMT, "Privilege violation", MCF5XXX_SF_PC(framep));
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break;
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case 9:
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printf(EXCEPTFMT, "Trace Exception", MCF5XXX_SF_PC(framep));
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break;
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case 10:
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printf(EXCEPTFMT, "Unimplemented A-Line Instruction", \
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MCF5XXX_SF_PC(framep));
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break;
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case 11:
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printf(EXCEPTFMT, "Unimplemented F-Line Instruction", \
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MCF5XXX_SF_PC(framep));
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break;
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case 12:
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printf(EXCEPTFMT, "Debug Interrupt", MCF5XXX_SF_PC(framep));
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break;
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case 14:
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printf(EXCEPTFMT, "Format Error", MCF5XXX_SF_PC(framep));
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break;
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case 15:
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printf(EXCEPTFMT, "Unitialized Interrupt", MCF5XXX_SF_PC(framep));
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break;
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case 24:
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printf(EXCEPTFMT, "Spurious Interrupt", MCF5XXX_SF_PC(framep));
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break;
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case 25:
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case 26:
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case 27:
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case 28:
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case 29:
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case 30:
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case 31:
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printf("Autovector interrupt level %d\n",
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MCF5XXX_RD_SF_VECTOR(framep) - 24);
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break;
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case 32:
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case 33:
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case 34:
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case 35:
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case 36:
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case 37:
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case 38:
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case 39:
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case 40:
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case 41:
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case 42:
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case 43:
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case 44:
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case 45:
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case 46:
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case 47:
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printf("TRAP #%d\n", MCF5XXX_RD_SF_VECTOR(framep) - 32);
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break;
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case 5:
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case 6:
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case 7:
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case 13:
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case 16:
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case 17:
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case 18:
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case 19:
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case 20:
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case 21:
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case 22:
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case 23:
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case 48:
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case 49:
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case 50:
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case 51:
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case 52:
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case 53:
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case 54:
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case 55:
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case 56:
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case 57:
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case 58:
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case 59:
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case 60:
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case 61:
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case 62:
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case 63:
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printf("Reserved: #%d\n", MCF5XXX_RD_SF_VECTOR(framep));
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break;
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default:
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cpu_handle_interrupt(MCF5XXX_RD_SF_VECTOR(framep));
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break;
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}
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}
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/********************************************************************/
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/*
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* Interpret the reset values of D0 and D1
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*
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* Parameters:
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* d0 - the reset value of data register zero
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* d1 - the reset value of data register one
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*/
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void
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mcf5xxx_interpret_d0d1(int d0, int d1)
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{
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#ifdef DEBUG_PRINT
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printf("\nColdFire Core Configuration:\n");
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printf("----------------------------\n");
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printf("Processor Family %#02x\n",MCF5XXX_D0_PF(d0));
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printf("ColdFire Core Version: %d\n",MCF5XXX_D0_VER(d0));
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printf("Processor Revision: %d\n",MCF5XXX_D0_REV(d1));
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printf("Bus Width: ");
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switch (MCF5XXX_D1_BUSW(d1))
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{
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case 0:
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printf("32-bit\n");
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break;
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default:
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printf("Reserved\n");
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}
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printf("ISA Version: ");
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switch (MCF5XXX_D0_ISA(d0))
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{
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case 0:
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printf("A\n");
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break;
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case 1:
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printf("B\n");
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break;
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case 2:
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printf("C\n");
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break;
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case 8:
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printf("A+\n");
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break;
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default:
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printf("Reserved\n");
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}
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printf("Debug Version: ");
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switch (MCF5XXX_D0_DEBUG(d0))
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{
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case 0:
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printf("A\n");
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break;
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case 1:
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printf("B\n");
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break;
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case 2:
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printf("C\n");
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break;
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case 3:
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printf("D\n");
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break;
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case 4:
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printf("E\n");
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break;
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case 9:
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printf("B+\n");
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break;
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default :
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printf("Reserved\n");
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}
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printf("MAC: %s\n", MCF5XXX_D0_MAC(d0) ? "Yes" : "No");
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printf("DIV: %s\n", MCF5XXX_D0_DIV(d0) ? "Yes" : "No");
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printf("EMAC: %s\n", MCF5XXX_D0_EMAC(d0) ? "Yes" : "No");
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printf("FPU: %s\n", MCF5XXX_D0_FPU(d0) ? "Yes" : "No");
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printf("MMU: %s\n", MCF5XXX_D0_MMU(d0) ? "Yes" : "No");
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printf("RAM Bank 0 Size: ");
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switch (MCF5XXX_D1_RAM0SIZ(d1))
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{
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case 0:
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case 1:
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case 2:
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case 3:
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printf("None\n");
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break;
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case 4:
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printf("4KB\n");
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break;
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case 5:
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printf("8KB\n");
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break;
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case 6:
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printf("16KB\n");
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break;
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case 7:
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printf("32KB\n");
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break;
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case 8:
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printf("64KB\n");
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break;
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case 9:
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printf("128KB\n");
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break;
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case 10:
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printf("256KB\n");
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break;
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case 11:
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printf("512KB\n");
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break;
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default:
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printf("Reserved\n");
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}
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printf("RAM Bank 1 Size: ");
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switch (MCF5XXX_D1_RAM1SIZ(d1))
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{
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case 0:
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case 1:
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case 2:
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case 3:
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printf("None\n");
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break;
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case 4:
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printf("4KB\n");
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break;
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case 5:
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printf("8KB\n");
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break;
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case 6:
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printf("16KB\n");
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break;
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case 7:
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printf("32KB\n");
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break;
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case 8:
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printf("64KB\n");
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break;
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case 9:
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printf("128KB\n");
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break;
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case 10:
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printf("256KB\n");
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break;
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case 11:
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printf("512KB\n");
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break;
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default:
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printf("Reserved\n");
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}
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printf("ROM Bank 0 Size: ");
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switch (MCF5XXX_D1_ROM0SIZ(d1))
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{
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case 0:
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case 1:
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case 2:
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case 3:
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printf("None\n");
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break;
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case 4:
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printf("4KB\n");
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break;
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case 5:
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printf("8KB\n");
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break;
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case 6:
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printf("16KB\n");
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break;
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case 7:
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printf("32KB\n");
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break;
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case 8:
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printf("64KB\n");
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break;
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case 9:
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printf("128KB\n");
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default:
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printf("Reserved\n");
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}
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printf("ROM Bank 1 Size: ");
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switch (MCF5XXX_D1_ROM1SIZ(d1))
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{
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case 0:
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case 1:
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case 2:
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case 3:
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printf("None\n");
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break;
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case 4:
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printf("4KB\n");
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break;
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case 5:
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printf("8KB\n");
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break;
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case 6:
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printf("16KB\n");
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break;
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case 7:
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printf("32KB\n");
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break;
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case 8:
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printf("64KB\n");
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break;
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case 9:
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printf("128KB\n");
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default:
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printf("Reserved\n");
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}
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printf("Cache Line Size: ");
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switch (MCF5XXX_D1_CL(d1))
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{
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case 0:
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printf("16-byte\n");
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break;
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default:
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printf("Reserved\n");
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}
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printf("I-Cache Associativity: ");
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switch (MCF5XXX_D1_ICA(d1))
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{
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case 0:
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printf("Four-way\n");
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break;
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case 1:
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printf("Direct mapped\n");
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break;
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default:
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printf("Reserved\n");
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}
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printf("D-Cache Associativity: ");
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switch (MCF5XXX_D1_DCA(d1))
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{
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case 0:
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printf("Four-way\n");
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break;
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case 1:
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printf("Direct mapped\n");
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break;
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default:
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printf("Reserved\n");
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}
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printf("I-Cache Size: ");
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switch (MCF5XXX_D1_ICSIZ(d1))
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{
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case 0:
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printf("None\n");
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break;
|
||
|
|
case 1:
|
||
|
|
printf("512B\n");
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
printf("1KB\n");
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
printf("2KB\n");
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
printf("4KB\n");
|
||
|
|
break;
|
||
|
|
case 5:
|
||
|
|
printf("8KB\n");
|
||
|
|
break;
|
||
|
|
case 6:
|
||
|
|
printf("16KB\n");
|
||
|
|
break;
|
||
|
|
case 7:
|
||
|
|
printf("32KB\n");
|
||
|
|
break;
|
||
|
|
case 8:
|
||
|
|
printf("64KB\n");
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
printf("Reserved\n");
|
||
|
|
}
|
||
|
|
printf("D-Cache Size: ");
|
||
|
|
switch (MCF5XXX_D1_DCSIZ(d1))
|
||
|
|
{
|
||
|
|
case 0:
|
||
|
|
printf("None\n");
|
||
|
|
break;
|
||
|
|
case 1:
|
||
|
|
printf("512B\n");
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
printf("1KB\n");
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
printf("2KB\n");
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
printf("4KB\n");
|
||
|
|
break;
|
||
|
|
case 5:
|
||
|
|
printf("8KB\n");
|
||
|
|
break;
|
||
|
|
case 6:
|
||
|
|
printf("16KB\n");
|
||
|
|
break;
|
||
|
|
case 7:
|
||
|
|
printf("32KB\n");
|
||
|
|
break;
|
||
|
|
case 8:
|
||
|
|
printf("64KB\n");
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
printf("Reserved\n");
|
||
|
|
}
|
||
|
|
printf("\n");
|
||
|
|
#else
|
||
|
|
/* Remove compiler warnings. */
|
||
|
|
( void ) d0;
|
||
|
|
( void ) d1;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/********************************************************************/
|
||
|
|
void
|
||
|
|
mcf5xxx_irq_enable (void)
|
||
|
|
{
|
||
|
|
asm_set_ipl(0);
|
||
|
|
}
|
||
|
|
/********************************************************************/
|
||
|
|
void
|
||
|
|
mcf5xxx_irq_disable (void)
|
||
|
|
{
|
||
|
|
asm_set_ipl(7);
|
||
|
|
}
|
||
|
|
/********************************************************************/
|
||
|
|
/*
|
||
|
|
* Write new interrupt vector handler into the vector table
|
||
|
|
* Return previous handler address
|
||
|
|
*/
|
||
|
|
|
||
|
|
ADDRESS
|
||
|
|
mcf5xxx_set_handler (int vector, ADDRESS new_handler)
|
||
|
|
{
|
||
|
|
ADDRESS old_handler;
|
||
|
|
extern uint32 __VECTOR_RAM[];
|
||
|
|
|
||
|
|
old_handler = (ADDRESS) __VECTOR_RAM[vector];
|
||
|
|
__VECTOR_RAM[vector] = (uint32)new_handler;
|
||
|
|
return old_handler;
|
||
|
|
}
|
||
|
|
|
||
|
|
/********************************************************************/
|