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/*
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* These files are taken from the MCF523X source code example package
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* which is available on the Freescale website. Freescale explicitly
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* grants the redistribution and modification of these source files.
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* The complete licensing information is available in the file
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* LICENSE_FREESCALE.TXT.
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*
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* File: mcf523x_fec.h
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* Purpose: Register and bit definitions for the MCF523X
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*
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* Notes:
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*
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*/
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#ifndef __MCF523X_FEC_H__
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#define __MCF523X_FEC_H__
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/*********************************************************************
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*
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* Fast Ethernet Controller (FEC)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004]))
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#define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008]))
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#define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010]))
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#define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014]))
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#define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024]))
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#define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040]))
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#define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044]))
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#define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064]))
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#define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084]))
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#define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4]))
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#define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4]))
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#define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8]))
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#define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC]))
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#define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118]))
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#define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C]))
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#define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120]))
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#define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124]))
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#define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144]))
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#define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C]))
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#define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150]))
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#define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180]))
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#define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184]))
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#define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188]))
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#define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200]))
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#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204]))
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#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208]))
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#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C]))
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#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210]))
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#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214]))
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#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218]))
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#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C]))
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#define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220]))
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#define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224]))
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#define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228]))
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#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C]))
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#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230]))
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#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234]))
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#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238]))
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#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C]))
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#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240]))
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#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244]))
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#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248]))
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#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C]))
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#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250]))
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#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254]))
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#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258]))
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#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C]))
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#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260]))
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#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264]))
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#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268]))
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#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C]))
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#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270]))
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#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274]))
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#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284]))
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#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288]))
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#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C]))
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#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290]))
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#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294]))
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#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298]))
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#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C]))
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#define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0]))
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#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4]))
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#define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8]))
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#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC]))
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#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0]))
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#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4]))
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#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8]))
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#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0]))
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#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC]))
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#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4]))
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#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8]))
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#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC]))
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#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0]))
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#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4]))
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#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8]))
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#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC]))
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#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0]))
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/* Bit definitions and macros for MCF_FEC_EIR */
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#define MCF_FEC_EIR_UN (0x00080000)
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#define MCF_FEC_EIR_RL (0x00100000)
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#define MCF_FEC_EIR_LC (0x00200000)
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#define MCF_FEC_EIR_EBERR (0x00400000)
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#define MCF_FEC_EIR_MII (0x00800000)
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#define MCF_FEC_EIR_RXB (0x01000000)
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#define MCF_FEC_EIR_RXF (0x02000000)
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#define MCF_FEC_EIR_TXB (0x04000000)
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#define MCF_FEC_EIR_TXF (0x08000000)
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#define MCF_FEC_EIR_GRA (0x10000000)
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#define MCF_FEC_EIR_BABT (0x20000000)
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#define MCF_FEC_EIR_BABR (0x40000000)
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#define MCF_FEC_EIR_HBERR (0x80000000)
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/* Bit definitions and macros for MCF_FEC_EIMR */
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#define MCF_FEC_EIMR_UN (0x00080000)
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#define MCF_FEC_EIMR_RL (0x00100000)
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#define MCF_FEC_EIMR_LC (0x00200000)
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#define MCF_FEC_EIMR_EBERR (0x00400000)
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#define MCF_FEC_EIMR_MII (0x00800000)
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#define MCF_FEC_EIMR_RXB (0x01000000)
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#define MCF_FEC_EIMR_RXF (0x02000000)
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#define MCF_FEC_EIMR_TXB (0x04000000)
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#define MCF_FEC_EIMR_TXF (0x08000000)
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#define MCF_FEC_EIMR_GRA (0x10000000)
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#define MCF_FEC_EIMR_BABT (0x20000000)
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#define MCF_FEC_EIMR_BABR (0x40000000)
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#define MCF_FEC_EIMR_HBERR (0x80000000)
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/* Bit definitions and macros for MCF_FEC_RDAR */
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#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000)
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/* Bit definitions and macros for MCF_FEC_TDAR */
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#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000)
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/* Bit definitions and macros for MCF_FEC_ECR */
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#define MCF_FEC_ECR_RESET (0x00000001)
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#define MCF_FEC_ECR_ETHER_EN (0x00000002)
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/* Bit definitions and macros for MCF_FEC_MMFR */
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#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
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#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
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#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
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#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
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#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
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#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
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#define MCF_FEC_MMFR_ST_01 (0x40000000)
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#define MCF_FEC_MMFR_OP_READ (0x20000000)
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#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
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#define MCF_FEC_MMFR_TA_10 (0x00020000)
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/* Bit definitions and macros for MCF_FEC_MSCR */
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#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
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#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080)
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/* Bit definitions and macros for MCF_FEC_MIBC */
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#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
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#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
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/* Bit definitions and macros for MCF_FEC_RCR */
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#define MCF_FEC_RCR_LOOP (0x00000001)
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#define MCF_FEC_RCR_DRT (0x00000002)
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#define MCF_FEC_RCR_MII_MODE (0x00000004)
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#define MCF_FEC_RCR_PROM (0x00000008)
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#define MCF_FEC_RCR_BC_REJ (0x00000010)
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#define MCF_FEC_RCR_FCE (0x00000020)
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#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16)
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/* Bit definitions and macros for MCF_FEC_TCR */
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#define MCF_FEC_TCR_GTS (0x00000001)
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#define MCF_FEC_TCR_HBC (0x00000002)
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#define MCF_FEC_TCR_FDEN (0x00000004)
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#define MCF_FEC_TCR_TFC_PAUSE (0x00000008)
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#define MCF_FEC_TCR_RFC_PAUSE (0x00000010)
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/* Bit definitions and macros for MCF_FEC_PAUR */
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#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
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#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_FEC_OPD */
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#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
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#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_FEC_TFWR */
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#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0)
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/* Bit definitions and macros for MCF_FEC_FRBR */
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#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2)
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/* Bit definitions and macros for MCF_FEC_FRSR */
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#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2)
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/* Bit definitions and macros for MCF_FEC_ERDSR */
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#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
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/* Bit definitions and macros for MCF_FEC_ETDSR */
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#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
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/* Bit definitions and macros for MCF_FEC_EMRBR */
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#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4)
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/********************************************************************/
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#endif /* __MCF523X_FEC_H__ */
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