/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : IO_Map.H
**     Project   : RTOSDemo
**     Processor : MC9S12DP256BCPV
**     Beantype  : IO_Map
**     Version   : Driver 01.01
**     Compiler  : Metrowerks HC12 C Compiler
**     Date/Time : 13/06/2005, 20:14
**     Abstract  :
**         This bean "IO_Map" implements an IO devices mapping.
**     Settings  :
**
**     Contents  :
**         No public methods
**
**     (c) Copyright UNIS, spol. s r.o. 1997-2002
**     UNIS, spol. s r.o.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : info@processorexpert.com
** ###################################################################*/

/* Linker pragmas */
#pragma LINK_INFO DERIVATIVE   "MC9S12DP256B"
#pragma LINK_INFO OSCFREQUENCY "16000000"


#define REG_BASE 0x0000                /* Base address for the I/O register block */

/* Based on CPU DB MC9S12DP256_112, version 2.87.278 (RegistersPrg V1.027) */
#ifndef _MC9S12DP256_112_H
#define _MC9S12DP256_112_H

#include "PE_Types.h"

#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */

/*********************************************/
/*                                           */
/* PE I/O map format                         */
/*                                           */
/*********************************************/

/*** PORTAB - Port AB Register; 0x00000000 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PORTA - Port A Register; 0x00000000 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Port A Bit0, ADDR8, DATA8, DATA0 */
        byte BIT1        :1;                                       /* Port A Bit1, ADDR9, DATA9 DATA1 */
        byte BIT2        :1;                                       /* Port A Bit2, ADDR10, DATA10, DATA2 */
        byte BIT3        :1;                                       /* Port A Bit3, ADDR11, DATA11, DATA3 */
        byte BIT4        :1;                                       /* Port A Bit4, ADDR12, DATA12, DATA4 */
        byte BIT5        :1;                                       /* Port A Bit5, ADDR13, DATA13, DATA5 */
        byte BIT6        :1;                                       /* Port A Bit6, ADDR14, DATA14, DATA6 */
        byte BIT7        :1;                                       /* Port A Bit7, ADDR15, DATA15, DATA7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PORTASTR;
    #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte
    #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0
    #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1
    #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2
    #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3
    #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4
    #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5
    #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6
    #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7
    #define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT
    
    /*** PORTB - Port B Register; 0x00000001 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Port B Bit 0, ADDR0, DATA0 */
        byte BIT1        :1;                                       /* Port B Bit1, ADDR1, DATA1 */
        byte BIT2        :1;                                       /* Port B Bit2, ADDR2, DATA2 */
        byte BIT3        :1;                                       /* Port B Bit3, ADDR3, DATA3 */
        byte BIT4        :1;                                       /* Port B Bit4, ADDR4, DATA4 */
        byte BIT5        :1;                                       /* Port B Bit5, ADDR5, DATA5 */
        byte BIT6        :1;                                       /* Port B Bit6, ADDR6, DATA6 */
        byte BIT7        :1;                                       /* Port B Bit7, ADDR7, DATA7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PORTBSTR;
    #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte
    #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0
    #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1
    #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2
    #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3
    #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4
    #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5
    #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6
    #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7
    #define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word BIT0        :1;                                       /* Port B Bit 0, ADDR0, DATA0 */
    word BIT1        :1;                                       /* Port B Bit1, ADDR1, DATA1 */
    word BIT2        :1;                                       /* Port B Bit2, ADDR2, DATA2 */
    word BIT3        :1;                                       /* Port B Bit3, ADDR3, DATA3 */
    word BIT4        :1;                                       /* Port B Bit4, ADDR4, DATA4 */
    word BIT5        :1;                                       /* Port B Bit5, ADDR5, DATA5 */
    word BIT6        :1;                                       /* Port B Bit6, ADDR6, DATA6 */
    word BIT7        :1;                                       /* Port B Bit7, ADDR7, DATA7 */
    word BIT8        :1;                                       /* Port A Bit0, ADDR8, DATA8, DATA0 */
    word BIT9        :1;                                       /* Port A Bit1, ADDR9, DATA9 DATA1 */
    word BIT10       :1;                                       /* Port A Bit2, ADDR10, DATA10, DATA2 */
    word BIT11       :1;                                       /* Port A Bit3, ADDR11, DATA11, DATA3 */
    word BIT12       :1;                                       /* Port A Bit4, ADDR12, DATA12, DATA4 */
    word BIT13       :1;                                       /* Port A Bit5, ADDR13, DATA13, DATA5 */
    word BIT14       :1;                                       /* Port A Bit6, ADDR14, DATA14, DATA6 */
    word BIT15       :1;                                       /* Port A Bit7, ADDR15, DATA15, DATA7 */
  } Bits;
  struct {
    word grpBIT  :16;
  } MergedBits;
} PORTABSTR;
extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000);
#define PORTAB _PORTAB.Word
#define PORTAB_BIT0 _PORTAB.Bits.BIT0
#define PORTAB_BIT1 _PORTAB.Bits.BIT1
#define PORTAB_BIT2 _PORTAB.Bits.BIT2
#define PORTAB_BIT3 _PORTAB.Bits.BIT3
#define PORTAB_BIT4 _PORTAB.Bits.BIT4
#define PORTAB_BIT5 _PORTAB.Bits.BIT5
#define PORTAB_BIT6 _PORTAB.Bits.BIT6
#define PORTAB_BIT7 _PORTAB.Bits.BIT7
#define PORTAB_BIT8 _PORTAB.Bits.BIT8
#define PORTAB_BIT9 _PORTAB.Bits.BIT9
#define PORTAB_BIT10 _PORTAB.Bits.BIT10
#define PORTAB_BIT11 _PORTAB.Bits.BIT11
#define PORTAB_BIT12 _PORTAB.Bits.BIT12
#define PORTAB_BIT13 _PORTAB.Bits.BIT13
#define PORTAB_BIT14 _PORTAB.Bits.BIT14
#define PORTAB_BIT15 _PORTAB.Bits.BIT15
#define PORTAB_BIT _PORTAB.MergedBits.grpBIT


/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** DDRA - Port A Data Direction Register; 0x00000002 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Data Direction Port A Bit 0 */
        byte BIT1        :1;                                       /* Data Direction Port A Bit 1 */
        byte BIT2        :1;                                       /* Data Direction Port A Bit 2 */
        byte BIT3        :1;                                       /* Data Direction Port A Bit 3 */
        byte BIT4        :1;                                       /* Data Direction Port A Bit 4 */
        byte BIT5        :1;                                       /* Data Direction Port A Bit 5 */
        byte BIT6        :1;                                       /* Data Direction Port A Bit 6 */
        byte BIT7        :1;                                       /* Data Direction Port A Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } DDRASTR;
    #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte
    #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0
    #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1
    #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2
    #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3
    #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4
    #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5
    #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6
    #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7
    #define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT
    
    /*** DDRB - Port B Data Direction Register; 0x00000003 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Data Direction Port B Bit 0 */
        byte BIT1        :1;                                       /* Data Direction Port B Bit 1 */
        byte BIT2        :1;                                       /* Data Direction Port B Bit 2 */
        byte BIT3        :1;                                       /* Data Direction Port B Bit 3 */
        byte BIT4        :1;                                       /* Data Direction Port B Bit 4 */
        byte BIT5        :1;                                       /* Data Direction Port B Bit 5 */
        byte BIT6        :1;                                       /* Data Direction Port B Bit 6 */
        byte BIT7        :1;                                       /* Data Direction Port B Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } DDRBSTR;
    #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte
    #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0
    #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1
    #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2
    #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3
    #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4
    #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5
    #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6
    #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7
    #define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word BIT0        :1;                                       /* Data Direction Port B Bit 0 */
    word BIT1        :1;                                       /* Data Direction Port B Bit 1 */
    word BIT2        :1;                                       /* Data Direction Port B Bit 2 */
    word BIT3        :1;                                       /* Data Direction Port B Bit 3 */
    word BIT4        :1;                                       /* Data Direction Port B Bit 4 */
    word BIT5        :1;                                       /* Data Direction Port B Bit 5 */
    word BIT6        :1;                                       /* Data Direction Port B Bit 6 */
    word BIT7        :1;                                       /* Data Direction Port B Bit 7 */
    word BIT8        :1;                                       /* Data Direction Port A Bit 8 */
    word BIT9        :1;                                       /* Data Direction Port A Bit 9 */
    word BIT10       :1;                                       /* Data Direction Port A Bit 10 */
    word BIT11       :1;                                       /* Data Direction Port A Bit 11 */
    word BIT12       :1;                                       /* Data Direction Port A Bit 12 */
    word BIT13       :1;                                       /* Data Direction Port A Bit 13 */
    word BIT14       :1;                                       /* Data Direction Port A Bit 14 */
    word BIT15       :1;                                       /* Data Direction Port A Bit 15 */
  } Bits;
  struct {
    word grpBIT  :16;
  } MergedBits;
} DDRABSTR;
extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002);
#define DDRAB _DDRAB.Word
#define DDRAB_BIT0 _DDRAB.Bits.BIT0
#define DDRAB_BIT1 _DDRAB.Bits.BIT1
#define DDRAB_BIT2 _DDRAB.Bits.BIT2
#define DDRAB_BIT3 _DDRAB.Bits.BIT3
#define DDRAB_BIT4 _DDRAB.Bits.BIT4
#define DDRAB_BIT5 _DDRAB.Bits.BIT5
#define DDRAB_BIT6 _DDRAB.Bits.BIT6
#define DDRAB_BIT7 _DDRAB.Bits.BIT7
#define DDRAB_BIT8 _DDRAB.Bits.BIT8
#define DDRAB_BIT9 _DDRAB.Bits.BIT9
#define DDRAB_BIT10 _DDRAB.Bits.BIT10
#define DDRAB_BIT11 _DDRAB.Bits.BIT11
#define DDRAB_BIT12 _DDRAB.Bits.BIT12
#define DDRAB_BIT13 _DDRAB.Bits.BIT13
#define DDRAB_BIT14 _DDRAB.Bits.BIT14
#define DDRAB_BIT15 _DDRAB.Bits.BIT15
#define DDRAB_BIT _DDRAB.MergedBits.grpBIT


/*** TCNT - Timer Count Register; 0x00000044 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TCNTHi - Timer Count Register High; 0x00000044 ***/
    union {
      byte Byte;
      struct {
        byte BIT15       :1;                                       /* Timer Count Register Bit 15 */
        byte BIT14       :1;                                       /* Timer Count Register Bit 14 */
        byte BIT13       :1;                                       /* Timer Count Register Bit 13 */
        byte BIT12       :1;                                       /* Timer Count Register Bit 12 */
        byte BIT11       :1;                                       /* Timer Count Register Bit 11 */
        byte BIT10       :1;                                       /* Timer Count Register Bit 10 */
        byte BIT9        :1;                                       /* Timer Count Register Bit 9 */
        byte BIT8        :1;                                       /* Timer Count Register Bit 8 */
      } Bits;
    } TCNTHiSTR;
    #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte
    #define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15
    #define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14
    #define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13
    #define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12
    #define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11
    #define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10
    #define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9
    #define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8
    
    /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Count Register Bit 0 */
        byte BIT1        :1;                                       /* Timer Count Register Bit 1 */
        byte BIT2        :1;                                       /* Timer Count Register Bit 2 */
        byte BIT3        :1;                                       /* Timer Count Register Bit 3 */
        byte BIT4        :1;                                       /* Timer Count Bit Register 4 */
        byte BIT5        :1;                                       /* Timer Count Bit Register 5 */
        byte BIT6        :1;                                       /* Timer Count Bit Register 6 */
        byte BIT7        :1;                                       /* Timer Count Bit Register 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TCNTLoSTR;
    #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte
    #define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0
    #define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1
    #define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2
    #define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3
    #define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4
    #define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5
    #define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6
    #define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7
    #define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} TCNTSTR;
extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044);
#define TCNT _TCNT.Word
#define TCNT_BIT _TCNT.MergedBits.grpBIT


/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC0HiSTR;
    #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte
    #define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8
    #define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9
    #define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10
    #define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11
    #define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12
    #define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13
    #define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14
    #define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15
    #define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8
    #define TC0Hi_BIT TC0Hi_BIT_8
    
    /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture/Output Compare Register 0 Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC0LoSTR;
    #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte
    #define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0
    #define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1
    #define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2
    #define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3
    #define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4
    #define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5
    #define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6
    #define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7
    #define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} TC0STR;
extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050);
#define TC0 _TC0.Word
#define TC0_BIT _TC0.MergedBits.grpBIT


/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC1HiSTR;
    #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte
    #define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8
    #define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9
    #define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10
    #define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11
    #define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12
    #define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13
    #define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14
    #define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15
    #define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8
    #define TC1Hi_BIT TC1Hi_BIT_8
    
    /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture/Output Compare Register 1 Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC1LoSTR;
    #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte
    #define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0
    #define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1
    #define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2
    #define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3
    #define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4
    #define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5
    #define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6
    #define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7
    #define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} TC1STR;
extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052);
#define TC1 _TC1.Word
#define TC1_BIT _TC1.MergedBits.grpBIT


/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC2HiSTR;
    #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte
    #define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8
    #define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9
    #define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10
    #define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11
    #define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12
    #define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13
    #define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14
    #define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15
    #define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8
    #define TC2Hi_BIT TC2Hi_BIT_8
    
    /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture/Output Compare Register 2 Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC2LoSTR;
    #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte
    #define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0
    #define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1
    #define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2
    #define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3
    #define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4
    #define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5
    #define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6
    #define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7
    #define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} TC2STR;
extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054);
#define TC2 _TC2.Word
#define TC2_BIT _TC2.MergedBits.grpBIT


/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC3HiSTR;
    #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte
    #define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8
    #define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9
    #define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10
    #define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11
    #define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12
    #define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13
    #define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14
    #define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15
    #define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8
    #define TC3Hi_BIT TC3Hi_BIT_8
    
    /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture/Output Compare Register 3 Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC3LoSTR;
    #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte
    #define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0
    #define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1
    #define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2
    #define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3
    #define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4
    #define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5
    #define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6
    #define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7
    #define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} TC3STR;
extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056);
#define TC3 _TC3.Word
#define TC3_BIT _TC3.MergedBits.grpBIT


/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC4HiSTR;
    #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte
    #define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8
    #define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9
    #define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10
    #define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11
    #define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12
    #define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13
    #define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14
    #define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15
    #define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8
    #define TC4Hi_BIT TC4Hi_BIT_8
    
    /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture/Output Compare Register 4 Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC4LoSTR;
    #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte
    #define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0
    #define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1
    #define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2
    #define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3
    #define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4
    #define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5
    #define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6
    #define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7
    #define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} TC4STR;
extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058);
#define TC4 _TC4.Word
#define TC4_BIT _TC4.MergedBits.grpBIT


/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC5HiSTR;
    #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte
    #define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8
    #define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9
    #define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10
    #define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11
    #define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12
    #define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13
    #define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14
    #define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15
    #define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8
    #define TC5Hi_BIT TC5Hi_BIT_8
    
    /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture/Output Compare Register 5 Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC5LoSTR;
    #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte
    #define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0
    #define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1
    #define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2
    #define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3
    #define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4
    #define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5
    #define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6
    #define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7
    #define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} TC5STR;
extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A);
#define TC5 _TC5.Word
#define TC5_BIT _TC5.MergedBits.grpBIT


/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC6HiSTR;
    #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte
    #define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8
    #define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9
    #define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10
    #define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11
    #define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12
    #define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13
    #define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14
    #define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15
    #define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8
    #define TC6Hi_BIT TC6Hi_BIT_8
    
    /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture/Output Compare Register 6 Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC6LoSTR;
    #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte
    #define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0
    #define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1
    #define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2
    #define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3
    #define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4
    #define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5
    #define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6
    #define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7
    #define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} TC6STR;
extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C);
#define TC6 _TC6.Word
#define TC6_BIT _TC6.MergedBits.grpBIT


/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC7HiSTR;
    #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte
    #define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8
    #define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9
    #define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10
    #define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11
    #define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12
    #define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13
    #define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14
    #define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15
    #define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8
    #define TC7Hi_BIT TC7Hi_BIT_8
    
    /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture/Output Compare Register 7 Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC7LoSTR;
    #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte
    #define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0
    #define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1
    #define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2
    #define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3
    #define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4
    #define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5
    #define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6
    #define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7
    #define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} TC7STR;
extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E);
#define TC7 _TC7.Word
#define TC7_BIT _TC7.MergedBits.grpBIT


/*** PACN32 - Pulse Accumulators Count 32 Register; 0x00000062 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PACN3 - Pulse Accumulators Count 3 Register; 0x00000062 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PACN3STR;
    #define PACN3 _PACN32.Overlap_STR.PACN3STR.Byte
    #define PACN3_BIT _PACN32.Overlap_STR.PACN3STR.MergedBits.grpBIT
    
    /*** PACN2 - Pulse Accumulators Count 2 Register; 0x00000063 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PACN2STR;
    #define PACN2 _PACN32.Overlap_STR.PACN2STR.Byte
    #define PACN2_BIT _PACN32.Overlap_STR.PACN2STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PACN32STR;
extern volatile PACN32STR _PACN32 @(REG_BASE + 0x00000062);
#define PACN32 _PACN32.Word
#define PACN32_BIT _PACN32.MergedBits.grpBIT


/*** PACN10 - Pulse Accumulators Count 10 Register; 0x00000064 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PACN1 - Pulse Accumulators Count 1 Register; 0x00000064 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PACN1STR;
    #define PACN1 _PACN10.Overlap_STR.PACN1STR.Byte
    #define PACN1_BIT _PACN10.Overlap_STR.PACN1STR.MergedBits.grpBIT
    
    /*** PACN0 - Pulse Accumulators Count 0 Register; 0x00000065 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PACN0STR;
    #define PACN0 _PACN10.Overlap_STR.PACN0STR.Byte
    #define PACN0_BIT _PACN10.Overlap_STR.PACN0STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PACN10STR;
extern volatile PACN10STR _PACN10 @(REG_BASE + 0x00000064);
#define PACN10 _PACN10.Word
#define PACN10_BIT _PACN10.MergedBits.grpBIT


/*** PA32H - 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PA3H - 8-Bit Pulse Accumulators Holding 3 Register; 0x00000072 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Pulse Accumulator Bit 0 */
        byte BIT1        :1;                                       /* Pulse Accumulator Bit 1 */
        byte BIT2        :1;                                       /* Pulse Accumulator Bit 2 */
        byte BIT3        :1;                                       /* Pulse Accumulator Bit 3 */
        byte BIT4        :1;                                       /* Pulse Accumulator Bit 4 */
        byte BIT5        :1;                                       /* Pulse Accumulator Bit 5 */
        byte BIT6        :1;                                       /* Pulse Accumulator Bit 6 */
        byte BIT7        :1;                                       /* Pulse Accumulator Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PA3HSTR;
    #define PA3H _PA32H.Overlap_STR.PA3HSTR.Byte
    #define PA3H_BIT0 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT0
    #define PA3H_BIT1 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT1
    #define PA3H_BIT2 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT2
    #define PA3H_BIT3 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT3
    #define PA3H_BIT4 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT4
    #define PA3H_BIT5 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT5
    #define PA3H_BIT6 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT6
    #define PA3H_BIT7 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT7
    #define PA3H_BIT _PA32H.Overlap_STR.PA3HSTR.MergedBits.grpBIT
    
    /*** PA2H - 8-Bit Pulse Accumulators Holding 2 Register; 0x00000073 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Pulse Accumulator Bit 0 */
        byte BIT1        :1;                                       /* Pulse Accumulator Bit 1 */
        byte BIT2        :1;                                       /* Pulse Accumulator Bit 2 */
        byte BIT3        :1;                                       /* Pulse Accumulator Bit 3 */
        byte BIT4        :1;                                       /* Pulse Accumulator Bit 4 */
        byte BIT5        :1;                                       /* Pulse Accumulator Bit 5 */
        byte BIT6        :1;                                       /* Pulse Accumulator Bit 6 */
        byte BIT7        :1;                                       /* Pulse Accumulator Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PA2HSTR;
    #define PA2H _PA32H.Overlap_STR.PA2HSTR.Byte
    #define PA2H_BIT0 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT0
    #define PA2H_BIT1 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT1
    #define PA2H_BIT2 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT2
    #define PA2H_BIT3 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT3
    #define PA2H_BIT4 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT4
    #define PA2H_BIT5 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT5
    #define PA2H_BIT6 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT6
    #define PA2H_BIT7 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT7
    #define PA2H_BIT _PA32H.Overlap_STR.PA2HSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word BIT0        :1;                                       /* Pulse Accumulator Bit 0 */
    word BIT1        :1;                                       /* Pulse Accumulator Bit 1 */
    word BIT2        :1;                                       /* Pulse Accumulator Bit 2 */
    word BIT3        :1;                                       /* Pulse Accumulator Bit 3 */
    word BIT4        :1;                                       /* Pulse Accumulator Bit 4 */
    word BIT5        :1;                                       /* Pulse Accumulator Bit 5 */
    word BIT6        :1;                                       /* Pulse Accumulator Bit 6 */
    word BIT7        :1;                                       /* Pulse Accumulator Bit 7 */
    word BIT8        :1;                                       /* Pulse Accumulator Bit 8 */
    word BIT9        :1;                                       /* Pulse Accumulator Bit 9 */
    word BIT10       :1;                                       /* Pulse Accumulator Bit 10 */
    word BIT11       :1;                                       /* Pulse Accumulator Bit 11 */
    word BIT12       :1;                                       /* Pulse Accumulator Bit 12 */
    word BIT13       :1;                                       /* Pulse Accumulator Bit 13 */
    word BIT14       :1;                                       /* Pulse Accumulator Bit 14 */
    word BIT15       :1;                                       /* Pulse Accumulator Bit 15 */
  } Bits;
  struct {
    word grpBIT  :16;
  } MergedBits;
} PA32HSTR;
extern volatile PA32HSTR _PA32H @(REG_BASE + 0x00000072);
#define PA32H _PA32H.Word
#define PA32H_BIT0 _PA32H.Bits.BIT0
#define PA32H_BIT1 _PA32H.Bits.BIT1
#define PA32H_BIT2 _PA32H.Bits.BIT2
#define PA32H_BIT3 _PA32H.Bits.BIT3
#define PA32H_BIT4 _PA32H.Bits.BIT4
#define PA32H_BIT5 _PA32H.Bits.BIT5
#define PA32H_BIT6 _PA32H.Bits.BIT6
#define PA32H_BIT7 _PA32H.Bits.BIT7
#define PA32H_BIT8 _PA32H.Bits.BIT8
#define PA32H_BIT9 _PA32H.Bits.BIT9
#define PA32H_BIT10 _PA32H.Bits.BIT10
#define PA32H_BIT11 _PA32H.Bits.BIT11
#define PA32H_BIT12 _PA32H.Bits.BIT12
#define PA32H_BIT13 _PA32H.Bits.BIT13
#define PA32H_BIT14 _PA32H.Bits.BIT14
#define PA32H_BIT15 _PA32H.Bits.BIT15
#define PA32H_BIT _PA32H.MergedBits.grpBIT


/*** PA10H - 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PA1H - 8-Bit Pulse Accumulators Holding 1 Register; 0x00000074 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Pulse Accumulator Bit 0 */
        byte BIT1        :1;                                       /* Pulse Accumulator Bit 1 */
        byte BIT2        :1;                                       /* Pulse Accumulator Bit 2 */
        byte BIT3        :1;                                       /* Pulse Accumulator Bit 3 */
        byte BIT4        :1;                                       /* Pulse Accumulator Bit 4 */
        byte BIT5        :1;                                       /* Pulse Accumulator Bit 5 */
        byte BIT6        :1;                                       /* Pulse Accumulator Bit 6 */
        byte BIT7        :1;                                       /* Pulse Accumulator Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PA1HSTR;
    #define PA1H _PA10H.Overlap_STR.PA1HSTR.Byte
    #define PA1H_BIT0 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT0
    #define PA1H_BIT1 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT1
    #define PA1H_BIT2 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT2
    #define PA1H_BIT3 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT3
    #define PA1H_BIT4 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT4
    #define PA1H_BIT5 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT5
    #define PA1H_BIT6 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT6
    #define PA1H_BIT7 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT7
    #define PA1H_BIT _PA10H.Overlap_STR.PA1HSTR.MergedBits.grpBIT
    
    /*** PA0H - 8-Bit Pulse Accumulators Holding 0 Register; 0x00000075 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Pulse Accumulator Bit 0 */
        byte BIT1        :1;                                       /* Pulse Accumulator Bit 1 */
        byte BIT2        :1;                                       /* Pulse Accumulator Bit 2 */
        byte BIT3        :1;                                       /* Pulse Accumulator Bit 3 */
        byte BIT4        :1;                                       /* Pulse Accumulator Bit 4 */
        byte BIT5        :1;                                       /* Pulse Accumulator Bit 5 */
        byte BIT6        :1;                                       /* Pulse Accumulator Bit 6 */
        byte BIT7        :1;                                       /* Pulse Accumulator Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PA0HSTR;
    #define PA0H _PA10H.Overlap_STR.PA0HSTR.Byte
    #define PA0H_BIT0 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT0
    #define PA0H_BIT1 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT1
    #define PA0H_BIT2 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT2
    #define PA0H_BIT3 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT3
    #define PA0H_BIT4 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT4
    #define PA0H_BIT5 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT5
    #define PA0H_BIT6 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT6
    #define PA0H_BIT7 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT7
    #define PA0H_BIT _PA10H.Overlap_STR.PA0HSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word BIT0        :1;                                       /* Pulse Accumulator Bit 0 */
    word BIT1        :1;                                       /* Pulse Accumulator Bit 1 */
    word BIT2        :1;                                       /* Pulse Accumulator Bit 2 */
    word BIT3        :1;                                       /* Pulse Accumulator Bit 3 */
    word BIT4        :1;                                       /* Pulse Accumulator Bit 4 */
    word BIT5        :1;                                       /* Pulse Accumulator Bit 5 */
    word BIT6        :1;                                       /* Pulse Accumulator Bit 6 */
    word BIT7        :1;                                       /* Pulse Accumulator Bit 7 */
    word BIT8        :1;                                       /* Pulse Accumulator Bit 8 */
    word BIT9        :1;                                       /* Pulse Accumulator Bit 9 */
    word BIT10       :1;                                       /* Pulse Accumulator Bit 10 */
    word BIT11       :1;                                       /* Pulse Accumulator Bit 11 */
    word BIT12       :1;                                       /* Pulse Accumulator Bit 12 */
    word BIT13       :1;                                       /* Pulse Accumulator Bit 13 */
    word BIT14       :1;                                       /* Pulse Accumulator Bit 14 */
    word BIT15       :1;                                       /* Pulse Accumulator Bit 15 */
  } Bits;
  struct {
    word grpBIT  :16;
  } MergedBits;
} PA10HSTR;
extern volatile PA10HSTR _PA10H @(REG_BASE + 0x00000074);
#define PA10H _PA10H.Word
#define PA10H_BIT0 _PA10H.Bits.BIT0
#define PA10H_BIT1 _PA10H.Bits.BIT1
#define PA10H_BIT2 _PA10H.Bits.BIT2
#define PA10H_BIT3 _PA10H.Bits.BIT3
#define PA10H_BIT4 _PA10H.Bits.BIT4
#define PA10H_BIT5 _PA10H.Bits.BIT5
#define PA10H_BIT6 _PA10H.Bits.BIT6
#define PA10H_BIT7 _PA10H.Bits.BIT7
#define PA10H_BIT8 _PA10H.Bits.BIT8
#define PA10H_BIT9 _PA10H.Bits.BIT9
#define PA10H_BIT10 _PA10H.Bits.BIT10
#define PA10H_BIT11 _PA10H.Bits.BIT11
#define PA10H_BIT12 _PA10H.Bits.BIT12
#define PA10H_BIT13 _PA10H.Bits.BIT13
#define PA10H_BIT14 _PA10H.Bits.BIT14
#define PA10H_BIT15 _PA10H.Bits.BIT15
#define PA10H_BIT _PA10H.MergedBits.grpBIT


/*** MCCNT - Modulus Down-Counter Count Register; 0x00000076 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** MCCNThi - Modulus Down-Counter Count Register High; 0x00000076 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Modulus Down-Counter Bit 8 */
        byte BIT9        :1;                                       /* Modulus Down-Counter Bit 9 */
        byte BIT10       :1;                                       /* Modulus Down-Counter Bit 10 */
        byte BIT11       :1;                                       /* Modulus Down-Counter Bit 11 */
        byte BIT12       :1;                                       /* Modulus Down-Counter Bit 12 */
        byte BIT13       :1;                                       /* Modulus Down-Counter Bit 13 */
        byte BIT14       :1;                                       /* Modulus Down-Counter Bit 14 */
        byte BIT15       :1;                                       /* Modulus Down-Counter Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } MCCNThiSTR;
    #define MCCNThi _MCCNT.Overlap_STR.MCCNThiSTR.Byte
    #define MCCNThi_BIT8 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT8
    #define MCCNThi_BIT9 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT9
    #define MCCNThi_BIT10 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT10
    #define MCCNThi_BIT11 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT11
    #define MCCNThi_BIT12 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT12
    #define MCCNThi_BIT13 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT13
    #define MCCNThi_BIT14 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT14
    #define MCCNThi_BIT15 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT15
    #define MCCNThi_BIT_8 _MCCNT.Overlap_STR.MCCNThiSTR.MergedBits.grpBIT_8
    #define MCCNThi_BIT MCCNThi_BIT_8
    
    /*** MCCNTlo - Modulus Down-Counter Count Register Low; 0x00000077 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Modulus Down-Counter Bit 0 */
        byte BIT1        :1;                                       /* Modulus Down-Counter Bit 1 */
        byte BIT2        :1;                                       /* Modulus Down-Counter Bit 2 */
        byte BIT3        :1;                                       /* Modulus Down-Counter Bit 3 */
        byte BIT4        :1;                                       /* Modulus Down-Counter Bit 4 */
        byte BIT5        :1;                                       /* Modulus Down-Counter Bit 5 */
        byte BIT6        :1;                                       /* Modulus Down-Counter Bit 6 */
        byte BIT7        :1;                                       /* Modulus Down-Counter Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } MCCNTloSTR;
    #define MCCNTlo _MCCNT.Overlap_STR.MCCNTloSTR.Byte
    #define MCCNTlo_BIT0 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT0
    #define MCCNTlo_BIT1 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT1
    #define MCCNTlo_BIT2 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT2
    #define MCCNTlo_BIT3 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT3
    #define MCCNTlo_BIT4 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT4
    #define MCCNTlo_BIT5 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT5
    #define MCCNTlo_BIT6 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT6
    #define MCCNTlo_BIT7 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT7
    #define MCCNTlo_BIT _MCCNT.Overlap_STR.MCCNTloSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} MCCNTSTR;
extern volatile MCCNTSTR _MCCNT @(REG_BASE + 0x00000076);
#define MCCNT _MCCNT.Word
#define MCCNT_BIT _MCCNT.MergedBits.grpBIT


/*** TC0H - Timer Input Capture Holding Registers 0; 0x00000078 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC0Hhi - Timer Input Capture Holding Registers 0 High; 0x00000078 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture Holding Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture Holding Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture Holding Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture Holding Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture Holding Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture Holding Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture Holding Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture Holding Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC0HhiSTR;
    #define TC0Hhi _TC0H.Overlap_STR.TC0HhiSTR.Byte
    #define TC0Hhi_BIT8 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT8
    #define TC0Hhi_BIT9 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT9
    #define TC0Hhi_BIT10 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT10
    #define TC0Hhi_BIT11 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT11
    #define TC0Hhi_BIT12 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT12
    #define TC0Hhi_BIT13 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT13
    #define TC0Hhi_BIT14 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT14
    #define TC0Hhi_BIT15 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT15
    #define TC0Hhi_BIT_8 _TC0H.Overlap_STR.TC0HhiSTR.MergedBits.grpBIT_8
    #define TC0Hhi_BIT TC0Hhi_BIT_8
    
    /*** TC0Hlo - Timer Input Capture Holding Registers 0 Low; 0x00000079 ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture Holding Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture Holding Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture Holding Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture Holding Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture Holding Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture Holding Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture Holding Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture Holding Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC0HloSTR;
    #define TC0Hlo _TC0H.Overlap_STR.TC0HloSTR.Byte
    #define TC0Hlo_BIT0 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT0
    #define TC0Hlo_BIT1 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT1
    #define TC0Hlo_BIT2 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT2
    #define TC0Hlo_BIT3 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT3
    #define TC0Hlo_BIT4 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT4
    #define TC0Hlo_BIT5 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT5
    #define TC0Hlo_BIT6 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT6
    #define TC0Hlo_BIT7 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT7
    #define TC0Hlo_BIT _TC0H.Overlap_STR.TC0HloSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word BIT0        :1;                                       /* Timer Input Capture Holding Bit 0 */
    word BIT1        :1;                                       /* Timer Input Capture Holding Bit 1 */
    word BIT2        :1;                                       /* Timer Input Capture Holding Bit 2 */
    word BIT3        :1;                                       /* Timer Input Capture Holding Bit 3 */
    word BIT4        :1;                                       /* Timer Input Capture Holding Bit 4 */
    word BIT5        :1;                                       /* Timer Input Capture Holding Bit 5 */
    word BIT6        :1;                                       /* Timer Input Capture Holding Bit 6 */
    word BIT7        :1;                                       /* Timer Input Capture Holding Bit 7 */
    word BIT8        :1;                                       /* Timer Input Capture Holding Bit 8 */
    word BIT9        :1;                                       /* Timer Input Capture Holding Bit 9 */
    word BIT10       :1;                                       /* Timer Input Capture Holding Bit 10 */
    word BIT11       :1;                                       /* Timer Input Capture Holding Bit 11 */
    word BIT12       :1;                                       /* Timer Input Capture Holding Bit 12 */
    word BIT13       :1;                                       /* Timer Input Capture Holding Bit 13 */
    word BIT14       :1;                                       /* Timer Input Capture Holding Bit 14 */
    word BIT15       :1;                                       /* Timer Input Capture Holding Bit 15 */
  } Bits;
  struct {
    word grpBIT  :16;
  } MergedBits;
} TC0HSTR;
extern volatile TC0HSTR _TC0H @(REG_BASE + 0x00000078);
#define TC0H _TC0H.Word
#define TC0H_BIT0 _TC0H.Bits.BIT0
#define TC0H_BIT1 _TC0H.Bits.BIT1
#define TC0H_BIT2 _TC0H.Bits.BIT2
#define TC0H_BIT3 _TC0H.Bits.BIT3
#define TC0H_BIT4 _TC0H.Bits.BIT4
#define TC0H_BIT5 _TC0H.Bits.BIT5
#define TC0H_BIT6 _TC0H.Bits.BIT6
#define TC0H_BIT7 _TC0H.Bits.BIT7
#define TC0H_BIT8 _TC0H.Bits.BIT8
#define TC0H_BIT9 _TC0H.Bits.BIT9
#define TC0H_BIT10 _TC0H.Bits.BIT10
#define TC0H_BIT11 _TC0H.Bits.BIT11
#define TC0H_BIT12 _TC0H.Bits.BIT12
#define TC0H_BIT13 _TC0H.Bits.BIT13
#define TC0H_BIT14 _TC0H.Bits.BIT14
#define TC0H_BIT15 _TC0H.Bits.BIT15
#define TC0H_BIT _TC0H.MergedBits.grpBIT


/*** TC1H - Timer Input Capture Holding Registers 1; 0x0000007A ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC1Hhi - Timer Input Capture Holding Registers 1 High; 0x0000007A ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture Holding Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture Holding Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture Holding Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture Holding Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture Holding Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture Holding Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture Holding Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture Holding Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC1HhiSTR;
    #define TC1Hhi _TC1H.Overlap_STR.TC1HhiSTR.Byte
    #define TC1Hhi_BIT8 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT8
    #define TC1Hhi_BIT9 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT9
    #define TC1Hhi_BIT10 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT10
    #define TC1Hhi_BIT11 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT11
    #define TC1Hhi_BIT12 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT12
    #define TC1Hhi_BIT13 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT13
    #define TC1Hhi_BIT14 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT14
    #define TC1Hhi_BIT15 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT15
    #define TC1Hhi_BIT_8 _TC1H.Overlap_STR.TC1HhiSTR.MergedBits.grpBIT_8
    #define TC1Hhi_BIT TC1Hhi_BIT_8
    
    /*** TC1Hlo - Timer Input Capture Holding Registers 1 Low; 0x0000007B ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture Holding Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture Holding Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture Holding Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture Holding Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture Holding Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture Holding Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture Holding Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture Holding Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC1HloSTR;
    #define TC1Hlo _TC1H.Overlap_STR.TC1HloSTR.Byte
    #define TC1Hlo_BIT0 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT0
    #define TC1Hlo_BIT1 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT1
    #define TC1Hlo_BIT2 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT2
    #define TC1Hlo_BIT3 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT3
    #define TC1Hlo_BIT4 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT4
    #define TC1Hlo_BIT5 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT5
    #define TC1Hlo_BIT6 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT6
    #define TC1Hlo_BIT7 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT7
    #define TC1Hlo_BIT _TC1H.Overlap_STR.TC1HloSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word BIT0        :1;                                       /* Timer Input Capture Holding Bit 0 */
    word BIT1        :1;                                       /* Timer Input Capture Holding Bit 1 */
    word BIT2        :1;                                       /* Timer Input Capture Holding Bit 2 */
    word BIT3        :1;                                       /* Timer Input Capture Holding Bit 3 */
    word BIT4        :1;                                       /* Timer Input Capture Holding Bit 4 */
    word BIT5        :1;                                       /* Timer Input Capture Holding Bit 5 */
    word BIT6        :1;                                       /* Timer Input Capture Holding Bit 6 */
    word BIT7        :1;                                       /* Timer Input Capture Holding Bit 7 */
    word BIT8        :1;                                       /* Timer Input Capture Holding Bit 8 */
    word BIT9        :1;                                       /* Timer Input Capture Holding Bit 9 */
    word BIT10       :1;                                       /* Timer Input Capture Holding Bit 10 */
    word BIT11       :1;                                       /* Timer Input Capture Holding Bit 11 */
    word BIT12       :1;                                       /* Timer Input Capture Holding Bit 12 */
    word BIT13       :1;                                       /* Timer Input Capture Holding Bit 13 */
    word BIT14       :1;                                       /* Timer Input Capture Holding Bit 14 */
    word BIT15       :1;                                       /* Timer Input Capture Holding Bit 15 */
  } Bits;
  struct {
    word grpBIT  :16;
  } MergedBits;
} TC1HSTR;
extern volatile TC1HSTR _TC1H @(REG_BASE + 0x0000007A);
#define TC1H _TC1H.Word
#define TC1H_BIT0 _TC1H.Bits.BIT0
#define TC1H_BIT1 _TC1H.Bits.BIT1
#define TC1H_BIT2 _TC1H.Bits.BIT2
#define TC1H_BIT3 _TC1H.Bits.BIT3
#define TC1H_BIT4 _TC1H.Bits.BIT4
#define TC1H_BIT5 _TC1H.Bits.BIT5
#define TC1H_BIT6 _TC1H.Bits.BIT6
#define TC1H_BIT7 _TC1H.Bits.BIT7
#define TC1H_BIT8 _TC1H.Bits.BIT8
#define TC1H_BIT9 _TC1H.Bits.BIT9
#define TC1H_BIT10 _TC1H.Bits.BIT10
#define TC1H_BIT11 _TC1H.Bits.BIT11
#define TC1H_BIT12 _TC1H.Bits.BIT12
#define TC1H_BIT13 _TC1H.Bits.BIT13
#define TC1H_BIT14 _TC1H.Bits.BIT14
#define TC1H_BIT15 _TC1H.Bits.BIT15
#define TC1H_BIT _TC1H.MergedBits.grpBIT


/*** TC2H - Timer Input Capture Holding Registers 2; 0x0000007C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC2Hhi - Timer Input Capture Holding Registers 2 High; 0x0000007C ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture Holding Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture Holding Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture Holding Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture Holding Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture Holding Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture Holding Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture Holding Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture Holding Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC2HhiSTR;
    #define TC2Hhi _TC2H.Overlap_STR.TC2HhiSTR.Byte
    #define TC2Hhi_BIT8 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT8
    #define TC2Hhi_BIT9 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT9
    #define TC2Hhi_BIT10 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT10
    #define TC2Hhi_BIT11 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT11
    #define TC2Hhi_BIT12 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT12
    #define TC2Hhi_BIT13 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT13
    #define TC2Hhi_BIT14 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT14
    #define TC2Hhi_BIT15 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT15
    #define TC2Hhi_BIT_8 _TC2H.Overlap_STR.TC2HhiSTR.MergedBits.grpBIT_8
    #define TC2Hhi_BIT TC2Hhi_BIT_8
    
    /*** TC2Hlo - Timer Input Capture Holding Registers 2 Low; 0x0000007D ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture Holding Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture Holding Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture Holding Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture Holding Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture Holding Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture Holding Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture Holding Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture Holding Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC2HloSTR;
    #define TC2Hlo _TC2H.Overlap_STR.TC2HloSTR.Byte
    #define TC2Hlo_BIT0 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT0
    #define TC2Hlo_BIT1 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT1
    #define TC2Hlo_BIT2 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT2
    #define TC2Hlo_BIT3 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT3
    #define TC2Hlo_BIT4 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT4
    #define TC2Hlo_BIT5 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT5
    #define TC2Hlo_BIT6 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT6
    #define TC2Hlo_BIT7 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT7
    #define TC2Hlo_BIT _TC2H.Overlap_STR.TC2HloSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word BIT0        :1;                                       /* Timer Input Capture Holding Bit 0 */
    word BIT1        :1;                                       /* Timer Input Capture Holding Bit 1 */
    word BIT2        :1;                                       /* Timer Input Capture Holding Bit 2 */
    word BIT3        :1;                                       /* Timer Input Capture Holding Bit 3 */
    word BIT4        :1;                                       /* Timer Input Capture Holding Bit 4 */
    word BIT5        :1;                                       /* Timer Input Capture Holding Bit 5 */
    word BIT6        :1;                                       /* Timer Input Capture Holding Bit 6 */
    word BIT7        :1;                                       /* Timer Input Capture Holding Bit 7 */
    word BIT8        :1;                                       /* Timer Input Capture Holding Bit 8 */
    word BIT9        :1;                                       /* Timer Input Capture Holding Bit 9 */
    word BIT10       :1;                                       /* Timer Input Capture Holding Bit 10 */
    word BIT11       :1;                                       /* Timer Input Capture Holding Bit 11 */
    word BIT12       :1;                                       /* Timer Input Capture Holding Bit 12 */
    word BIT13       :1;                                       /* Timer Input Capture Holding Bit 13 */
    word BIT14       :1;                                       /* Timer Input Capture Holding Bit 14 */
    word BIT15       :1;                                       /* Timer Input Capture Holding Bit 15 */
  } Bits;
  struct {
    word grpBIT  :16;
  } MergedBits;
} TC2HSTR;
extern volatile TC2HSTR _TC2H @(REG_BASE + 0x0000007C);
#define TC2H _TC2H.Word
#define TC2H_BIT0 _TC2H.Bits.BIT0
#define TC2H_BIT1 _TC2H.Bits.BIT1
#define TC2H_BIT2 _TC2H.Bits.BIT2
#define TC2H_BIT3 _TC2H.Bits.BIT3
#define TC2H_BIT4 _TC2H.Bits.BIT4
#define TC2H_BIT5 _TC2H.Bits.BIT5
#define TC2H_BIT6 _TC2H.Bits.BIT6
#define TC2H_BIT7 _TC2H.Bits.BIT7
#define TC2H_BIT8 _TC2H.Bits.BIT8
#define TC2H_BIT9 _TC2H.Bits.BIT9
#define TC2H_BIT10 _TC2H.Bits.BIT10
#define TC2H_BIT11 _TC2H.Bits.BIT11
#define TC2H_BIT12 _TC2H.Bits.BIT12
#define TC2H_BIT13 _TC2H.Bits.BIT13
#define TC2H_BIT14 _TC2H.Bits.BIT14
#define TC2H_BIT15 _TC2H.Bits.BIT15
#define TC2H_BIT _TC2H.MergedBits.grpBIT


/*** TC3H - Timer Input Capture Holding Registers 3; 0x0000007E ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** TC3Hhi - Timer Input Capture Holding Registers 3 High; 0x0000007E ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Timer Input Capture Holding Bit 8 */
        byte BIT9        :1;                                       /* Timer Input Capture Holding Bit 9 */
        byte BIT10       :1;                                       /* Timer Input Capture Holding Bit 10 */
        byte BIT11       :1;                                       /* Timer Input Capture Holding Bit 11 */
        byte BIT12       :1;                                       /* Timer Input Capture Holding Bit 12 */
        byte BIT13       :1;                                       /* Timer Input Capture Holding Bit 13 */
        byte BIT14       :1;                                       /* Timer Input Capture Holding Bit 14 */
        byte BIT15       :1;                                       /* Timer Input Capture Holding Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } TC3HhiSTR;
    #define TC3Hhi _TC3H.Overlap_STR.TC3HhiSTR.Byte
    #define TC3Hhi_BIT8 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT8
    #define TC3Hhi_BIT9 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT9
    #define TC3Hhi_BIT10 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT10
    #define TC3Hhi_BIT11 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT11
    #define TC3Hhi_BIT12 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT12
    #define TC3Hhi_BIT13 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT13
    #define TC3Hhi_BIT14 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT14
    #define TC3Hhi_BIT15 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT15
    #define TC3Hhi_BIT_8 _TC3H.Overlap_STR.TC3HhiSTR.MergedBits.grpBIT_8
    #define TC3Hhi_BIT TC3Hhi_BIT_8
    
    /*** TC3Hlo - Timer Input Capture Holding Registers 3 Low; 0x0000007F ***/
    union {
      byte Byte;
      struct {
        byte BIT0        :1;                                       /* Timer Input Capture Holding Bit 0 */
        byte BIT1        :1;                                       /* Timer Input Capture Holding Bit 1 */
        byte BIT2        :1;                                       /* Timer Input Capture Holding Bit 2 */
        byte BIT3        :1;                                       /* Timer Input Capture Holding Bit 3 */
        byte BIT4        :1;                                       /* Timer Input Capture Holding Bit 4 */
        byte BIT5        :1;                                       /* Timer Input Capture Holding Bit 5 */
        byte BIT6        :1;                                       /* Timer Input Capture Holding Bit 6 */
        byte BIT7        :1;                                       /* Timer Input Capture Holding Bit 7 */
      } Bits;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } TC3HloSTR;
    #define TC3Hlo _TC3H.Overlap_STR.TC3HloSTR.Byte
    #define TC3Hlo_BIT0 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT0
    #define TC3Hlo_BIT1 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT1
    #define TC3Hlo_BIT2 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT2
    #define TC3Hlo_BIT3 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT3
    #define TC3Hlo_BIT4 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT4
    #define TC3Hlo_BIT5 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT5
    #define TC3Hlo_BIT6 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT6
    #define TC3Hlo_BIT7 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT7
    #define TC3Hlo_BIT _TC3H.Overlap_STR.TC3HloSTR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word BIT0        :1;                                       /* Timer Input Capture Holding Bit 0 */
    word BIT1        :1;                                       /* Timer Input Capture Holding Bit 1 */
    word BIT2        :1;                                       /* Timer Input Capture Holding Bit 2 */
    word BIT3        :1;                                       /* Timer Input Capture Holding Bit 3 */
    word BIT4        :1;                                       /* Timer Input Capture Holding Bit 4 */
    word BIT5        :1;                                       /* Timer Input Capture Holding Bit 5 */
    word BIT6        :1;                                       /* Timer Input Capture Holding Bit 6 */
    word BIT7        :1;                                       /* Timer Input Capture Holding Bit 7 */
    word BIT8        :1;                                       /* Timer Input Capture Holding Bit 8 */
    word BIT9        :1;                                       /* Timer Input Capture Holding Bit 9 */
    word BIT10       :1;                                       /* Timer Input Capture Holding Bit 10 */
    word BIT11       :1;                                       /* Timer Input Capture Holding Bit 11 */
    word BIT12       :1;                                       /* Timer Input Capture Holding Bit 12 */
    word BIT13       :1;                                       /* Timer Input Capture Holding Bit 13 */
    word BIT14       :1;                                       /* Timer Input Capture Holding Bit 14 */
    word BIT15       :1;                                       /* Timer Input Capture Holding Bit 15 */
  } Bits;
  struct {
    word grpBIT  :16;
  } MergedBits;
} TC3HSTR;
extern volatile TC3HSTR _TC3H @(REG_BASE + 0x0000007E);
#define TC3H _TC3H.Word
#define TC3H_BIT0 _TC3H.Bits.BIT0
#define TC3H_BIT1 _TC3H.Bits.BIT1
#define TC3H_BIT2 _TC3H.Bits.BIT2
#define TC3H_BIT3 _TC3H.Bits.BIT3
#define TC3H_BIT4 _TC3H.Bits.BIT4
#define TC3H_BIT5 _TC3H.Bits.BIT5
#define TC3H_BIT6 _TC3H.Bits.BIT6
#define TC3H_BIT7 _TC3H.Bits.BIT7
#define TC3H_BIT8 _TC3H.Bits.BIT8
#define TC3H_BIT9 _TC3H.Bits.BIT9
#define TC3H_BIT10 _TC3H.Bits.BIT10
#define TC3H_BIT11 _TC3H.Bits.BIT11
#define TC3H_BIT12 _TC3H.Bits.BIT12
#define TC3H_BIT13 _TC3H.Bits.BIT13
#define TC3H_BIT14 _TC3H.Bits.BIT14
#define TC3H_BIT15 _TC3H.Bits.BIT15
#define TC3H_BIT _TC3H.MergedBits.grpBIT


/*** ATD0CTL23 - ATD 0 Control Register 23; 0x00000082 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD0CTL2 - ATD 0 Control Register 2; 0x00000082 ***/
    union {
      byte Byte;
      struct {
        byte ASCIF       :1;                                       /* ATD 0 Sequence Complete Interrupt Flag */
        byte ASCIE       :1;                                       /* ATD 0 Sequence Complete Interrupt Enable */
        byte ETRIGE      :1;                                       /* External Trigger Mode enable */
        byte ETRIGP      :1;                                       /* External Trigger Polarity */
        byte ETRIGLE     :1;                                       /* External Trigger Level/Edge control */
        byte AWAI        :1;                                       /* ATD 0 Wait Mode */
        byte AFFC        :1;                                       /* ATD 0 Fast Conversion Complete Flag Clear */
        byte ADPU        :1;                                       /* ATD 0 Disable / Power Down */
      } Bits;
    } ATD0CTL2STR;
    #define ATD0CTL2 _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Byte
    #define ATD0CTL2_ASCIF _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIF
    #define ATD0CTL2_ASCIE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIE
    #define ATD0CTL2_ETRIGE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGE
    #define ATD0CTL2_ETRIGP _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGP
    #define ATD0CTL2_ETRIGLE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGLE
    #define ATD0CTL2_AWAI _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AWAI
    #define ATD0CTL2_AFFC _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AFFC
    #define ATD0CTL2_ADPU _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ADPU
    
    /*** ATD0CTL3 - ATD 0 Control Register 3; 0x00000083 ***/
    union {
      byte Byte;
      struct {
        byte FRZ0        :1;                                       /* Background Debug Freeze Enable */
        byte FRZ1        :1;                                       /* Background Debug Freeze Enable */
        byte FIFO        :1;                                       /* Result Register FIFO Mode */
        byte S1C         :1;                                       /* Conversion Sequence Length 1 */
        byte S2C         :1;                                       /* Conversion Sequence Length 2 */
        byte S4C         :1;                                       /* Conversion Sequence Length 4 */
        byte S8C         :1;                                       /* Conversion Sequence Length 8 */
        byte             :1; 
      } Bits;
      struct {
        byte grpFRZ :2;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
      } MergedBits;
    } ATD0CTL3STR;
    #define ATD0CTL3 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Byte
    #define ATD0CTL3_FRZ0 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ0
    #define ATD0CTL3_FRZ1 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ1
    #define ATD0CTL3_FIFO _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FIFO
    #define ATD0CTL3_S1C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S1C
    #define ATD0CTL3_S2C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S2C
    #define ATD0CTL3_S4C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S4C
    #define ATD0CTL3_S8C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S8C
    #define ATD0CTL3_FRZ _ATD0CTL23.Overlap_STR.ATD0CTL3STR.MergedBits.grpFRZ
    
  } Overlap_STR;

  struct {
    word FRZ0        :1;                                       /* Background Debug Freeze Enable */
    word FRZ1        :1;                                       /* Background Debug Freeze Enable */
    word FIFO        :1;                                       /* Result Register FIFO Mode */
    word S1C         :1;                                       /* Conversion Sequence Length 1 */
    word S2C         :1;                                       /* Conversion Sequence Length 2 */
    word S4C         :1;                                       /* Conversion Sequence Length 4 */
    word S8C         :1;                                       /* Conversion Sequence Length 8 */
    word             :1; 
    word ASCIF       :1;                                       /* ATD 0 Sequence Complete Interrupt Flag */
    word ASCIE       :1;                                       /* ATD 0 Sequence Complete Interrupt Enable */
    word ETRIGE      :1;                                       /* External Trigger Mode enable */
    word ETRIGP      :1;                                       /* External Trigger Polarity */
    word ETRIGLE     :1;                                       /* External Trigger Level/Edge control */
    word AWAI        :1;                                       /* ATD 0 Wait Mode */
    word AFFC        :1;                                       /* ATD 0 Fast Conversion Complete Flag Clear */
    word ADPU        :1;                                       /* ATD 0 Disable / Power Down */
  } Bits;
  struct {
    word grpFRZ  :2;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
  } MergedBits;
} ATD0CTL23STR;
extern volatile ATD0CTL23STR _ATD0CTL23 @(REG_BASE + 0x00000082);
#define ATD0CTL23 _ATD0CTL23.Word
#define ATD0CTL23_FRZ0 _ATD0CTL23.Bits.FRZ0
#define ATD0CTL23_FRZ1 _ATD0CTL23.Bits.FRZ1
#define ATD0CTL23_FIFO _ATD0CTL23.Bits.FIFO
#define ATD0CTL23_S1C _ATD0CTL23.Bits.S1C
#define ATD0CTL23_S2C _ATD0CTL23.Bits.S2C
#define ATD0CTL23_S4C _ATD0CTL23.Bits.S4C
#define ATD0CTL23_S8C _ATD0CTL23.Bits.S8C
#define ATD0CTL23_ASCIF _ATD0CTL23.Bits.ASCIF
#define ATD0CTL23_ASCIE _ATD0CTL23.Bits.ASCIE
#define ATD0CTL23_ETRIGE _ATD0CTL23.Bits.ETRIGE
#define ATD0CTL23_ETRIGP _ATD0CTL23.Bits.ETRIGP
#define ATD0CTL23_ETRIGLE _ATD0CTL23.Bits.ETRIGLE
#define ATD0CTL23_AWAI _ATD0CTL23.Bits.AWAI
#define ATD0CTL23_AFFC _ATD0CTL23.Bits.AFFC
#define ATD0CTL23_ADPU _ATD0CTL23.Bits.ADPU
#define ATD0CTL23_FRZ _ATD0CTL23.MergedBits.grpFRZ


/*** ATD0CTL45 - ATD 0 Control Register 45; 0x00000084 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD0CTL4 - ATD 0 Control Register 4; 0x00000084 ***/
    union {
      byte Byte;
      struct {
        byte PRS0        :1;                                       /* ATD 0 Clock Prescaler 0 */
        byte PRS1        :1;                                       /* ATD 0 Clock Prescaler 1 */
        byte PRS2        :1;                                       /* ATD 0 Clock Prescaler 2 */
        byte PRS3        :1;                                       /* ATD 0 Clock Prescaler 3 */
        byte PRS4        :1;                                       /* ATD 0 Clock Prescaler 4 */
        byte SMP0        :1;                                       /* Sample Time Select 0 */
        byte SMP1        :1;                                       /* Sample Time Select 1 */
        byte SRES8       :1;                                       /* ATD 0 Resolution Select */
      } Bits;
      struct {
        byte grpPRS :5;
        byte grpSMP :2;
        byte grpSRES_8 :1;
      } MergedBits;
    } ATD0CTL4STR;
    #define ATD0CTL4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Byte
    #define ATD0CTL4_PRS0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS0
    #define ATD0CTL4_PRS1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS1
    #define ATD0CTL4_PRS2 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS2
    #define ATD0CTL4_PRS3 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS3
    #define ATD0CTL4_PRS4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS4
    #define ATD0CTL4_SMP0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP0
    #define ATD0CTL4_SMP1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP1
    #define ATD0CTL4_SRES8 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SRES8
    #define ATD0CTL4_PRS _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpPRS
    #define ATD0CTL4_SMP _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpSMP
    
    /*** ATD0CTL5 - ATD 0 Control Register 5; 0x00000085 ***/
    union {
      byte Byte;
      struct {
        byte CA          :1;                                       /* Analog Input Channel Select Code A */
        byte CB          :1;                                       /* Analog Input Channel Select Code B */
        byte CC          :1;                                       /* Analog Input Channel Select Code C */
        byte             :1; 
        byte MULT        :1;                                       /* Multi-Channel Sample Mode */
        byte SCAN        :1;                                       /* Continuous Conversion Sequence Mode */
        byte DSGN        :1;                                       /* Signed/Unsigned Result Data Mode */
        byte DJM         :1;                                       /* Result Register Data Justification Mode */
      } Bits;
    } ATD0CTL5STR;
    #define ATD0CTL5 _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Byte
    #define ATD0CTL5_CA _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CA
    #define ATD0CTL5_CB _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CB
    #define ATD0CTL5_CC _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CC
    #define ATD0CTL5_MULT _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.MULT
    #define ATD0CTL5_SCAN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.SCAN
    #define ATD0CTL5_DSGN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DSGN
    #define ATD0CTL5_DJM _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DJM
    
  } Overlap_STR;

  struct {
    word CA          :1;                                       /* Analog Input Channel Select Code A */
    word CB          :1;                                       /* Analog Input Channel Select Code B */
    word CC          :1;                                       /* Analog Input Channel Select Code C */
    word             :1; 
    word MULT        :1;                                       /* Multi-Channel Sample Mode */
    word SCAN        :1;                                       /* Continuous Conversion Sequence Mode */
    word DSGN        :1;                                       /* Signed/Unsigned Result Data Mode */
    word DJM         :1;                                       /* Result Register Data Justification Mode */
    word PRS0        :1;                                       /* ATD 0 Clock Prescaler 0 */
    word PRS1        :1;                                       /* ATD 0 Clock Prescaler 1 */
    word PRS2        :1;                                       /* ATD 0 Clock Prescaler 2 */
    word PRS3        :1;                                       /* ATD 0 Clock Prescaler 3 */
    word PRS4        :1;                                       /* ATD 0 Clock Prescaler 4 */
    word SMP0        :1;                                       /* Sample Time Select 0 */
    word SMP1        :1;                                       /* Sample Time Select 1 */
    word SRES8       :1;                                       /* ATD 0 Resolution Select */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpPRS  :5;
    word grpSMP  :2;
    word grpSRES_8 :1;
  } MergedBits;
} ATD0CTL45STR;
extern volatile ATD0CTL45STR _ATD0CTL45 @(REG_BASE + 0x00000084);
#define ATD0CTL45 _ATD0CTL45.Word
#define ATD0CTL45_CA _ATD0CTL45.Bits.CA
#define ATD0CTL45_CB _ATD0CTL45.Bits.CB
#define ATD0CTL45_CC _ATD0CTL45.Bits.CC
#define ATD0CTL45_MULT _ATD0CTL45.Bits.MULT
#define ATD0CTL45_SCAN _ATD0CTL45.Bits.SCAN
#define ATD0CTL45_DSGN _ATD0CTL45.Bits.DSGN
#define ATD0CTL45_DJM _ATD0CTL45.Bits.DJM
#define ATD0CTL45_PRS0 _ATD0CTL45.Bits.PRS0
#define ATD0CTL45_PRS1 _ATD0CTL45.Bits.PRS1
#define ATD0CTL45_PRS2 _ATD0CTL45.Bits.PRS2
#define ATD0CTL45_PRS3 _ATD0CTL45.Bits.PRS3
#define ATD0CTL45_PRS4 _ATD0CTL45.Bits.PRS4
#define ATD0CTL45_SMP0 _ATD0CTL45.Bits.SMP0
#define ATD0CTL45_SMP1 _ATD0CTL45.Bits.SMP1
#define ATD0CTL45_SRES8 _ATD0CTL45.Bits.SRES8
#define ATD0CTL45_PRS _ATD0CTL45.MergedBits.grpPRS
#define ATD0CTL45_SMP _ATD0CTL45.MergedBits.grpSMP


/*** ATD0DR0 - ATD 0 Conversion Result Register 0; 0x00000090 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD0DR0H - ATD 0 Conversion Result Register 0 High; 0x00000090 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD0DR0HSTR;
    #define ATD0DR0H _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Byte
    #define ATD0DR0H_BIT8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT8
    #define ATD0DR0H_BIT9 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT9
    #define ATD0DR0H_BIT10 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT10
    #define ATD0DR0H_BIT11 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT11
    #define ATD0DR0H_BIT12 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT12
    #define ATD0DR0H_BIT13 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT13
    #define ATD0DR0H_BIT14 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT14
    #define ATD0DR0H_BIT15 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT15
    #define ATD0DR0H_BIT_8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.MergedBits.grpBIT_8
    #define ATD0DR0H_BIT ATD0DR0H_BIT_8
    
    /*** ATD0DR0L - ATD 0 Conversion Result Register 0 Low; 0x00000091 ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD0DR0LSTR;
    #define ATD0DR0L _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Byte
    #define ATD0DR0L_BIT6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT6
    #define ATD0DR0L_BIT7 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT7
    #define ATD0DR0L_BIT_6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.MergedBits.grpBIT_6
    #define ATD0DR0L_BIT ATD0DR0L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD0DR0STR;
extern volatile ATD0DR0STR _ATD0DR0 @(REG_BASE + 0x00000090);
#define ATD0DR0 _ATD0DR0.Word
#define ATD0DR0_BIT6 _ATD0DR0.Bits.BIT6
#define ATD0DR0_BIT7 _ATD0DR0.Bits.BIT7
#define ATD0DR0_BIT8 _ATD0DR0.Bits.BIT8
#define ATD0DR0_BIT9 _ATD0DR0.Bits.BIT9
#define ATD0DR0_BIT10 _ATD0DR0.Bits.BIT10
#define ATD0DR0_BIT11 _ATD0DR0.Bits.BIT11
#define ATD0DR0_BIT12 _ATD0DR0.Bits.BIT12
#define ATD0DR0_BIT13 _ATD0DR0.Bits.BIT13
#define ATD0DR0_BIT14 _ATD0DR0.Bits.BIT14
#define ATD0DR0_BIT15 _ATD0DR0.Bits.BIT15
#define ATD0DR0_BIT_6 _ATD0DR0.MergedBits.grpBIT_6
#define ATD0DR0_BIT ATD0DR0_BIT_6


/*** ATD0DR1 - ATD 0 Conversion Result Register 1; 0x00000092 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD0DR1H - ATD 0 Conversion Result Register 1 High; 0x00000092 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD0DR1HSTR;
    #define ATD0DR1H _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Byte
    #define ATD0DR1H_BIT8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT8
    #define ATD0DR1H_BIT9 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT9
    #define ATD0DR1H_BIT10 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT10
    #define ATD0DR1H_BIT11 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT11
    #define ATD0DR1H_BIT12 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT12
    #define ATD0DR1H_BIT13 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT13
    #define ATD0DR1H_BIT14 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT14
    #define ATD0DR1H_BIT15 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT15
    #define ATD0DR1H_BIT_8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.MergedBits.grpBIT_8
    #define ATD0DR1H_BIT ATD0DR1H_BIT_8
    
    /*** ATD0DR1L - ATD 0 Conversion Result Register 1 Low; 0x00000093 ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD0DR1LSTR;
    #define ATD0DR1L _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Byte
    #define ATD0DR1L_BIT6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT6
    #define ATD0DR1L_BIT7 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT7
    #define ATD0DR1L_BIT_6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.MergedBits.grpBIT_6
    #define ATD0DR1L_BIT ATD0DR1L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD0DR1STR;
extern volatile ATD0DR1STR _ATD0DR1 @(REG_BASE + 0x00000092);
#define ATD0DR1 _ATD0DR1.Word
#define ATD0DR1_BIT6 _ATD0DR1.Bits.BIT6
#define ATD0DR1_BIT7 _ATD0DR1.Bits.BIT7
#define ATD0DR1_BIT8 _ATD0DR1.Bits.BIT8
#define ATD0DR1_BIT9 _ATD0DR1.Bits.BIT9
#define ATD0DR1_BIT10 _ATD0DR1.Bits.BIT10
#define ATD0DR1_BIT11 _ATD0DR1.Bits.BIT11
#define ATD0DR1_BIT12 _ATD0DR1.Bits.BIT12
#define ATD0DR1_BIT13 _ATD0DR1.Bits.BIT13
#define ATD0DR1_BIT14 _ATD0DR1.Bits.BIT14
#define ATD0DR1_BIT15 _ATD0DR1.Bits.BIT15
#define ATD0DR1_BIT_6 _ATD0DR1.MergedBits.grpBIT_6
#define ATD0DR1_BIT ATD0DR1_BIT_6


/*** ATD0DR2 - ATD 0 Conversion Result Register 2; 0x00000094 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD0DR2H - ATD 0 Conversion Result Register 2 High; 0x00000094 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD0DR2HSTR;
    #define ATD0DR2H _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Byte
    #define ATD0DR2H_BIT8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT8
    #define ATD0DR2H_BIT9 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT9
    #define ATD0DR2H_BIT10 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT10
    #define ATD0DR2H_BIT11 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT11
    #define ATD0DR2H_BIT12 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT12
    #define ATD0DR2H_BIT13 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT13
    #define ATD0DR2H_BIT14 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT14
    #define ATD0DR2H_BIT15 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT15
    #define ATD0DR2H_BIT_8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.MergedBits.grpBIT_8
    #define ATD0DR2H_BIT ATD0DR2H_BIT_8
    
    /*** ATD0DR2L - ATD 0 Conversion Result Register 2 Low; 0x00000095 ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD0DR2LSTR;
    #define ATD0DR2L _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Byte
    #define ATD0DR2L_BIT6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT6
    #define ATD0DR2L_BIT7 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT7
    #define ATD0DR2L_BIT_6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.MergedBits.grpBIT_6
    #define ATD0DR2L_BIT ATD0DR2L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD0DR2STR;
extern volatile ATD0DR2STR _ATD0DR2 @(REG_BASE + 0x00000094);
#define ATD0DR2 _ATD0DR2.Word
#define ATD0DR2_BIT6 _ATD0DR2.Bits.BIT6
#define ATD0DR2_BIT7 _ATD0DR2.Bits.BIT7
#define ATD0DR2_BIT8 _ATD0DR2.Bits.BIT8
#define ATD0DR2_BIT9 _ATD0DR2.Bits.BIT9
#define ATD0DR2_BIT10 _ATD0DR2.Bits.BIT10
#define ATD0DR2_BIT11 _ATD0DR2.Bits.BIT11
#define ATD0DR2_BIT12 _ATD0DR2.Bits.BIT12
#define ATD0DR2_BIT13 _ATD0DR2.Bits.BIT13
#define ATD0DR2_BIT14 _ATD0DR2.Bits.BIT14
#define ATD0DR2_BIT15 _ATD0DR2.Bits.BIT15
#define ATD0DR2_BIT_6 _ATD0DR2.MergedBits.grpBIT_6
#define ATD0DR2_BIT ATD0DR2_BIT_6


/*** ATD0DR3 - ATD 0 Conversion Result Register 3; 0x00000096 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD0DR3H - ATD 0 Conversion Result Register 3 High; 0x00000096 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD0DR3HSTR;
    #define ATD0DR3H _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Byte
    #define ATD0DR3H_BIT8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT8
    #define ATD0DR3H_BIT9 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT9
    #define ATD0DR3H_BIT10 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT10
    #define ATD0DR3H_BIT11 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT11
    #define ATD0DR3H_BIT12 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT12
    #define ATD0DR3H_BIT13 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT13
    #define ATD0DR3H_BIT14 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT14
    #define ATD0DR3H_BIT15 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT15
    #define ATD0DR3H_BIT_8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.MergedBits.grpBIT_8
    #define ATD0DR3H_BIT ATD0DR3H_BIT_8
    
    /*** ATD0DR3L - ATD 0 Conversion Result Register 3 Low; 0x00000097 ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD0DR3LSTR;
    #define ATD0DR3L _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Byte
    #define ATD0DR3L_BIT6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT6
    #define ATD0DR3L_BIT7 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT7
    #define ATD0DR3L_BIT_6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.MergedBits.grpBIT_6
    #define ATD0DR3L_BIT ATD0DR3L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD0DR3STR;
extern volatile ATD0DR3STR _ATD0DR3 @(REG_BASE + 0x00000096);
#define ATD0DR3 _ATD0DR3.Word
#define ATD0DR3_BIT6 _ATD0DR3.Bits.BIT6
#define ATD0DR3_BIT7 _ATD0DR3.Bits.BIT7
#define ATD0DR3_BIT8 _ATD0DR3.Bits.BIT8
#define ATD0DR3_BIT9 _ATD0DR3.Bits.BIT9
#define ATD0DR3_BIT10 _ATD0DR3.Bits.BIT10
#define ATD0DR3_BIT11 _ATD0DR3.Bits.BIT11
#define ATD0DR3_BIT12 _ATD0DR3.Bits.BIT12
#define ATD0DR3_BIT13 _ATD0DR3.Bits.BIT13
#define ATD0DR3_BIT14 _ATD0DR3.Bits.BIT14
#define ATD0DR3_BIT15 _ATD0DR3.Bits.BIT15
#define ATD0DR3_BIT_6 _ATD0DR3.MergedBits.grpBIT_6
#define ATD0DR3_BIT ATD0DR3_BIT_6


/*** ATD0DR4 - ATD 0 Conversion Result Register 4; 0x00000098 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD0DR4H - ATD 0 Conversion Result Register 4 High; 0x00000098 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD0DR4HSTR;
    #define ATD0DR4H _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Byte
    #define ATD0DR4H_BIT8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT8
    #define ATD0DR4H_BIT9 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT9
    #define ATD0DR4H_BIT10 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT10
    #define ATD0DR4H_BIT11 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT11
    #define ATD0DR4H_BIT12 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT12
    #define ATD0DR4H_BIT13 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT13
    #define ATD0DR4H_BIT14 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT14
    #define ATD0DR4H_BIT15 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT15
    #define ATD0DR4H_BIT_8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.MergedBits.grpBIT_8
    #define ATD0DR4H_BIT ATD0DR4H_BIT_8
    
    /*** ATD0DR4L - ATD 0 Conversion Result Register 4 Low; 0x00000099 ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD0DR4LSTR;
    #define ATD0DR4L _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Byte
    #define ATD0DR4L_BIT6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT6
    #define ATD0DR4L_BIT7 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT7
    #define ATD0DR4L_BIT_6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.MergedBits.grpBIT_6
    #define ATD0DR4L_BIT ATD0DR4L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD0DR4STR;
extern volatile ATD0DR4STR _ATD0DR4 @(REG_BASE + 0x00000098);
#define ATD0DR4 _ATD0DR4.Word
#define ATD0DR4_BIT6 _ATD0DR4.Bits.BIT6
#define ATD0DR4_BIT7 _ATD0DR4.Bits.BIT7
#define ATD0DR4_BIT8 _ATD0DR4.Bits.BIT8
#define ATD0DR4_BIT9 _ATD0DR4.Bits.BIT9
#define ATD0DR4_BIT10 _ATD0DR4.Bits.BIT10
#define ATD0DR4_BIT11 _ATD0DR4.Bits.BIT11
#define ATD0DR4_BIT12 _ATD0DR4.Bits.BIT12
#define ATD0DR4_BIT13 _ATD0DR4.Bits.BIT13
#define ATD0DR4_BIT14 _ATD0DR4.Bits.BIT14
#define ATD0DR4_BIT15 _ATD0DR4.Bits.BIT15
#define ATD0DR4_BIT_6 _ATD0DR4.MergedBits.grpBIT_6
#define ATD0DR4_BIT ATD0DR4_BIT_6


/*** ATD0DR5 - ATD 0 Conversion Result Register 5; 0x0000009A ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD0DR5H - ATD 0 Conversion Result Register 5 High; 0x0000009A ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD0DR5HSTR;
    #define ATD0DR5H _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Byte
    #define ATD0DR5H_BIT8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT8
    #define ATD0DR5H_BIT9 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT9
    #define ATD0DR5H_BIT10 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT10
    #define ATD0DR5H_BIT11 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT11
    #define ATD0DR5H_BIT12 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT12
    #define ATD0DR5H_BIT13 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT13
    #define ATD0DR5H_BIT14 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT14
    #define ATD0DR5H_BIT15 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT15
    #define ATD0DR5H_BIT_8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.MergedBits.grpBIT_8
    #define ATD0DR5H_BIT ATD0DR5H_BIT_8
    
    /*** ATD0DR5L - ATD 0 Conversion Result Register 5 Low; 0x0000009B ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD0DR5LSTR;
    #define ATD0DR5L _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Byte
    #define ATD0DR5L_BIT6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT6
    #define ATD0DR5L_BIT7 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT7
    #define ATD0DR5L_BIT_6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.MergedBits.grpBIT_6
    #define ATD0DR5L_BIT ATD0DR5L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD0DR5STR;
extern volatile ATD0DR5STR _ATD0DR5 @(REG_BASE + 0x0000009A);
#define ATD0DR5 _ATD0DR5.Word
#define ATD0DR5_BIT6 _ATD0DR5.Bits.BIT6
#define ATD0DR5_BIT7 _ATD0DR5.Bits.BIT7
#define ATD0DR5_BIT8 _ATD0DR5.Bits.BIT8
#define ATD0DR5_BIT9 _ATD0DR5.Bits.BIT9
#define ATD0DR5_BIT10 _ATD0DR5.Bits.BIT10
#define ATD0DR5_BIT11 _ATD0DR5.Bits.BIT11
#define ATD0DR5_BIT12 _ATD0DR5.Bits.BIT12
#define ATD0DR5_BIT13 _ATD0DR5.Bits.BIT13
#define ATD0DR5_BIT14 _ATD0DR5.Bits.BIT14
#define ATD0DR5_BIT15 _ATD0DR5.Bits.BIT15
#define ATD0DR5_BIT_6 _ATD0DR5.MergedBits.grpBIT_6
#define ATD0DR5_BIT ATD0DR5_BIT_6


/*** ATD0DR6 - ATD 0 Conversion Result Register 6; 0x0000009C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD0DR6H - ATD 0 Conversion Result Register 6 High; 0x0000009C ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD0DR6HSTR;
    #define ATD0DR6H _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Byte
    #define ATD0DR6H_BIT8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT8
    #define ATD0DR6H_BIT9 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT9
    #define ATD0DR6H_BIT10 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT10
    #define ATD0DR6H_BIT11 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT11
    #define ATD0DR6H_BIT12 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT12
    #define ATD0DR6H_BIT13 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT13
    #define ATD0DR6H_BIT14 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT14
    #define ATD0DR6H_BIT15 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT15
    #define ATD0DR6H_BIT_8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.MergedBits.grpBIT_8
    #define ATD0DR6H_BIT ATD0DR6H_BIT_8
    
    /*** ATD0DR6L - ATD 0 Conversion Result Register 6 Low; 0x0000009D ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD0DR6LSTR;
    #define ATD0DR6L _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Byte
    #define ATD0DR6L_BIT6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT6
    #define ATD0DR6L_BIT7 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT7
    #define ATD0DR6L_BIT_6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.MergedBits.grpBIT_6
    #define ATD0DR6L_BIT ATD0DR6L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD0DR6STR;
extern volatile ATD0DR6STR _ATD0DR6 @(REG_BASE + 0x0000009C);
#define ATD0DR6 _ATD0DR6.Word
#define ATD0DR6_BIT6 _ATD0DR6.Bits.BIT6
#define ATD0DR6_BIT7 _ATD0DR6.Bits.BIT7
#define ATD0DR6_BIT8 _ATD0DR6.Bits.BIT8
#define ATD0DR6_BIT9 _ATD0DR6.Bits.BIT9
#define ATD0DR6_BIT10 _ATD0DR6.Bits.BIT10
#define ATD0DR6_BIT11 _ATD0DR6.Bits.BIT11
#define ATD0DR6_BIT12 _ATD0DR6.Bits.BIT12
#define ATD0DR6_BIT13 _ATD0DR6.Bits.BIT13
#define ATD0DR6_BIT14 _ATD0DR6.Bits.BIT14
#define ATD0DR6_BIT15 _ATD0DR6.Bits.BIT15
#define ATD0DR6_BIT_6 _ATD0DR6.MergedBits.grpBIT_6
#define ATD0DR6_BIT ATD0DR6_BIT_6


/*** ATD0DR7 - ATD 0 Conversion Result Register 7; 0x0000009E ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD0DR7H - ATD 0 Conversion Result Register 7 High; 0x0000009E ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD0DR7HSTR;
    #define ATD0DR7H _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Byte
    #define ATD0DR7H_BIT8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT8
    #define ATD0DR7H_BIT9 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT9
    #define ATD0DR7H_BIT10 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT10
    #define ATD0DR7H_BIT11 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT11
    #define ATD0DR7H_BIT12 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT12
    #define ATD0DR7H_BIT13 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT13
    #define ATD0DR7H_BIT14 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT14
    #define ATD0DR7H_BIT15 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT15
    #define ATD0DR7H_BIT_8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.MergedBits.grpBIT_8
    #define ATD0DR7H_BIT ATD0DR7H_BIT_8
    
    /*** ATD0DR7L - ATD 0 Conversion Result Register 7 Low; 0x0000009F ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD0DR7LSTR;
    #define ATD0DR7L _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Byte
    #define ATD0DR7L_BIT6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT6
    #define ATD0DR7L_BIT7 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT7
    #define ATD0DR7L_BIT_6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.MergedBits.grpBIT_6
    #define ATD0DR7L_BIT ATD0DR7L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD0DR7STR;
extern volatile ATD0DR7STR _ATD0DR7 @(REG_BASE + 0x0000009E);
#define ATD0DR7 _ATD0DR7.Word
#define ATD0DR7_BIT6 _ATD0DR7.Bits.BIT6
#define ATD0DR7_BIT7 _ATD0DR7.Bits.BIT7
#define ATD0DR7_BIT8 _ATD0DR7.Bits.BIT8
#define ATD0DR7_BIT9 _ATD0DR7.Bits.BIT9
#define ATD0DR7_BIT10 _ATD0DR7.Bits.BIT10
#define ATD0DR7_BIT11 _ATD0DR7.Bits.BIT11
#define ATD0DR7_BIT12 _ATD0DR7.Bits.BIT12
#define ATD0DR7_BIT13 _ATD0DR7.Bits.BIT13
#define ATD0DR7_BIT14 _ATD0DR7.Bits.BIT14
#define ATD0DR7_BIT15 _ATD0DR7.Bits.BIT15
#define ATD0DR7_BIT_6 _ATD0DR7.MergedBits.grpBIT_6
#define ATD0DR7_BIT ATD0DR7_BIT_6


/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000AC ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000AC ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMCNT0STR;
    #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte
    #define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT
    
    /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000AD ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMCNT1STR;
    #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte
    #define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMCNT01STR;
extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000AC);
#define PWMCNT01 _PWMCNT01.Word
#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT


/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000AE ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000AE ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMCNT2STR;
    #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte
    #define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT
    
    /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000AF ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMCNT3STR;
    #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte
    #define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMCNT23STR;
extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000AE);
#define PWMCNT23 _PWMCNT23.Word
#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT


/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000B0 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000B0 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMCNT4STR;
    #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte
    #define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT
    
    /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000B1 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMCNT5STR;
    #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte
    #define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMCNT45STR;
extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000B0);
#define PWMCNT45 _PWMCNT45.Word
#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT


/*** PWMCNT67 - PWM Channel Counter 67 Register; 0x000000B2 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMCNT6 - PWM Channel Counter 6 Register; 0x000000B2 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMCNT6STR;
    #define PWMCNT6 _PWMCNT67.Overlap_STR.PWMCNT6STR.Byte
    #define PWMCNT6_BIT _PWMCNT67.Overlap_STR.PWMCNT6STR.MergedBits.grpBIT
    
    /*** PWMCNT7 - PWM Channel Counter 7 Register; 0x000000B3 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMCNT7STR;
    #define PWMCNT7 _PWMCNT67.Overlap_STR.PWMCNT7STR.Byte
    #define PWMCNT7_BIT _PWMCNT67.Overlap_STR.PWMCNT7STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMCNT67STR;
extern volatile PWMCNT67STR _PWMCNT67 @(REG_BASE + 0x000000B2);
#define PWMCNT67 _PWMCNT67.Word
#define PWMCNT67_BIT _PWMCNT67.MergedBits.grpBIT


/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000B4 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000B4 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMPER0STR;
    #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte
    #define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT
    
    /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000B5 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMPER1STR;
    #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte
    #define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMPER01STR;
extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000B4);
#define PWMPER01 _PWMPER01.Word
#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT


/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000B6 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000B6 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMPER2STR;
    #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte
    #define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT
    
    /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000B7 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMPER3STR;
    #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte
    #define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMPER23STR;
extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000B6);
#define PWMPER23 _PWMPER23.Word
#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT


/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000B8 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000B8 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMPER4STR;
    #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte
    #define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT
    
    /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000B9 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMPER5STR;
    #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte
    #define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMPER45STR;
extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000B8);
#define PWMPER45 _PWMPER45.Word
#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT


/*** PWMPER67 - PWM Channel Period 67 Register; 0x000000BA ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMPER6 - PWM Channel Period 6 Register; 0x000000BA ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMPER6STR;
    #define PWMPER6 _PWMPER67.Overlap_STR.PWMPER6STR.Byte
    #define PWMPER6_BIT _PWMPER67.Overlap_STR.PWMPER6STR.MergedBits.grpBIT
    
    /*** PWMPER7 - PWM Channel Period 7 Register; 0x000000BB ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMPER7STR;
    #define PWMPER7 _PWMPER67.Overlap_STR.PWMPER7STR.Byte
    #define PWMPER7_BIT _PWMPER67.Overlap_STR.PWMPER7STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMPER67STR;
extern volatile PWMPER67STR _PWMPER67 @(REG_BASE + 0x000000BA);
#define PWMPER67 _PWMPER67.Word
#define PWMPER67_BIT _PWMPER67.MergedBits.grpBIT


/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000BC ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000BC ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMDTY0STR;
    #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte
    #define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT
    
    /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000BD ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMDTY1STR;
    #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte
    #define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMDTY01STR;
extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000BC);
#define PWMDTY01 _PWMDTY01.Word
#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT


/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000BE ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000BE ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMDTY2STR;
    #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte
    #define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT
    
    /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000BF ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMDTY3STR;
    #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte
    #define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMDTY23STR;
extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000BE);
#define PWMDTY23 _PWMDTY23.Word
#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT


/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000C0 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000C0 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMDTY4STR;
    #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte
    #define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT
    
    /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000C1 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMDTY5STR;
    #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte
    #define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMDTY45STR;
extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000C0);
#define PWMDTY45 _PWMDTY45.Word
#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT


/*** PWMDTY67 - PWM Channel Duty 67 Register; 0x000000C2 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** PWMDTY6 - PWM Channel Duty 6 Register; 0x000000C2 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMDTY6STR;
    #define PWMDTY6 _PWMDTY67.Overlap_STR.PWMDTY6STR.Byte
    #define PWMDTY6_BIT _PWMDTY67.Overlap_STR.PWMDTY6STR.MergedBits.grpBIT
    
    /*** PWMDTY7 - PWM Channel Duty 7 Register; 0x000000C3 ***/
    union {
      byte Byte;
      struct {
        byte grpBIT :8;
      } MergedBits;
    } PWMDTY7STR;
    #define PWMDTY7 _PWMDTY67.Overlap_STR.PWMDTY7STR.Byte
    #define PWMDTY7_BIT _PWMDTY67.Overlap_STR.PWMDTY7STR.MergedBits.grpBIT
    
  } Overlap_STR;

  struct {
    word grpBIT  :16;
  } MergedBits;
} PWMDTY67STR;
extern volatile PWMDTY67STR _PWMDTY67 @(REG_BASE + 0x000000C2);
#define PWMDTY67 _PWMDTY67.Word
#define PWMDTY67_BIT _PWMDTY67.MergedBits.grpBIT


/*** SCI0BD - SCI 0 Baud Rate Register; 0x000000C8 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 ***/
    union {
      byte Byte;
      struct {
        byte SBR8        :1;                                       /* SCI 0 baud rate Bit 8 */
        byte SBR9        :1;                                       /* SCI 0 baud rate Bit 9 */
        byte SBR10       :1;                                       /* SCI 0 baud rate Bit 10 */
        byte SBR11       :1;                                       /* SCI 0 baud rate Bit 11 */
        byte SBR12       :1;                                       /* SCI 0 baud rate Bit 12 */
        byte             :1; 
        byte             :1; 
        byte             :1; 
      } Bits;
      struct {
        byte grpSBR_8 :5;
        byte     :1;
        byte     :1;
        byte     :1;
      } MergedBits;
    } SCI0BDHSTR;
    #define SCI0BDH _SCI0BD.Overlap_STR.SCI0BDHSTR.Byte
    #define SCI0BDH_SBR8 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR8
    #define SCI0BDH_SBR9 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR9
    #define SCI0BDH_SBR10 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR10
    #define SCI0BDH_SBR11 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR11
    #define SCI0BDH_SBR12 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR12
    #define SCI0BDH_SBR_8 _SCI0BD.Overlap_STR.SCI0BDHSTR.MergedBits.grpSBR_8
    #define SCI0BDH_SBR SCI0BDH_SBR_8
    
    /*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 ***/
    union {
      byte Byte;
      struct {
        byte SBR0        :1;                                       /* SCI 0 baud rate Bit 0 */
        byte SBR1        :1;                                       /* SCI 0 baud rate Bit 1 */
        byte SBR2        :1;                                       /* SCI 0 baud rate Bit 2 */
        byte SBR3        :1;                                       /* SCI 0 baud rate Bit 3 */
        byte SBR4        :1;                                       /* SCI 0 baud rate Bit 4 */
        byte SBR5        :1;                                       /* SCI 0 baud rate Bit 5 */
        byte SBR6        :1;                                       /* SCI 0 baud rate Bit 6 */
        byte SBR7        :1;                                       /* SCI 0 baud rate Bit 7 */
      } Bits;
      struct {
        byte grpSBR :8;
      } MergedBits;
    } SCI0BDLSTR;
    #define SCI0BDL _SCI0BD.Overlap_STR.SCI0BDLSTR.Byte
    #define SCI0BDL_SBR0 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR0
    #define SCI0BDL_SBR1 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR1
    #define SCI0BDL_SBR2 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR2
    #define SCI0BDL_SBR3 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR3
    #define SCI0BDL_SBR4 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR4
    #define SCI0BDL_SBR5 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR5
    #define SCI0BDL_SBR6 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR6
    #define SCI0BDL_SBR7 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR7
    #define SCI0BDL_SBR _SCI0BD.Overlap_STR.SCI0BDLSTR.MergedBits.grpSBR
    
  } Overlap_STR;

  struct {
    word SBR0        :1;                                       /* SCI 0 baud rate Bit 0 */
    word SBR1        :1;                                       /* SCI 0 baud rate Bit 1 */
    word SBR2        :1;                                       /* SCI 0 baud rate Bit 2 */
    word SBR3        :1;                                       /* SCI 0 baud rate Bit 3 */
    word SBR4        :1;                                       /* SCI 0 baud rate Bit 4 */
    word SBR5        :1;                                       /* SCI 0 baud rate Bit 5 */
    word SBR6        :1;                                       /* SCI 0 baud rate Bit 6 */
    word SBR7        :1;                                       /* SCI 0 baud rate Bit 7 */
    word SBR8        :1;                                       /* SCI 0 baud rate Bit 8 */
    word SBR9        :1;                                       /* SCI 0 baud rate Bit 9 */
    word SBR10       :1;                                       /* SCI 0 baud rate Bit 10 */
    word SBR11       :1;                                       /* SCI 0 baud rate Bit 11 */
    word SBR12       :1;                                       /* SCI 0 baud rate Bit 12 */
    word             :1; 
    word             :1; 
    word             :1; 
  } Bits;
  struct {
    word grpSBR  :13;
    word         :1;
    word         :1;
    word         :1;
  } MergedBits;
} SCI0BDSTR;
extern volatile SCI0BDSTR _SCI0BD @(REG_BASE + 0x000000C8);
#define SCI0BD _SCI0BD.Word
#define SCI0BD_SBR0 _SCI0BD.Bits.SBR0
#define SCI0BD_SBR1 _SCI0BD.Bits.SBR1
#define SCI0BD_SBR2 _SCI0BD.Bits.SBR2
#define SCI0BD_SBR3 _SCI0BD.Bits.SBR3
#define SCI0BD_SBR4 _SCI0BD.Bits.SBR4
#define SCI0BD_SBR5 _SCI0BD.Bits.SBR5
#define SCI0BD_SBR6 _SCI0BD.Bits.SBR6
#define SCI0BD_SBR7 _SCI0BD.Bits.SBR7
#define SCI0BD_SBR8 _SCI0BD.Bits.SBR8
#define SCI0BD_SBR9 _SCI0BD.Bits.SBR9
#define SCI0BD_SBR10 _SCI0BD.Bits.SBR10
#define SCI0BD_SBR11 _SCI0BD.Bits.SBR11
#define SCI0BD_SBR12 _SCI0BD.Bits.SBR12
#define SCI0BD_SBR _SCI0BD.MergedBits.grpSBR


/*** SCI1BD - SCI 1 Baud Rate Register; 0x000000D0 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** SCI1BDH - SCI 1 Baud Rate Register High; 0x000000D0 ***/
    union {
      byte Byte;
      struct {
        byte SBR8        :1;                                       /* SCI 1 baud rate Bit 8 */
        byte SBR9        :1;                                       /* SCI 1 baud rate Bit 9 */
        byte SBR10       :1;                                       /* SCI 1 baud rate Bit 10 */
        byte SBR11       :1;                                       /* SCI 1 baud rate Bit 11 */
        byte SBR12       :1;                                       /* SCI 1 baud rate Bit 12 */
        byte             :1; 
        byte             :1; 
        byte             :1; 
      } Bits;
      struct {
        byte grpSBR_8 :5;
        byte     :1;
        byte     :1;
        byte     :1;
      } MergedBits;
    } SCI1BDHSTR;
    #define SCI1BDH _SCI1BD.Overlap_STR.SCI1BDHSTR.Byte
    #define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR8
    #define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR9
    #define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR10
    #define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR11
    #define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR12
    #define SCI1BDH_SBR_8 _SCI1BD.Overlap_STR.SCI1BDHSTR.MergedBits.grpSBR_8
    #define SCI1BDH_SBR SCI1BDH_SBR_8
    
    /*** SCI1BDL - SCI 1 Baud Rate Register Low; 0x000000D1 ***/
    union {
      byte Byte;
      struct {
        byte SBR0        :1;                                       /* SCI 1 baud rate Bit 0 */
        byte SBR1        :1;                                       /* SCI 1 baud rate Bit 1 */
        byte SBR2        :1;                                       /* SCI 1 baud rate Bit 2 */
        byte SBR3        :1;                                       /* SCI 1 baud rate Bit 3 */
        byte SBR4        :1;                                       /* SCI 1 baud rate Bit 4 */
        byte SBR5        :1;                                       /* SCI 1 baud rate Bit 5 */
        byte SBR6        :1;                                       /* SCI 1 baud rate Bit 6 */
        byte SBR7        :1;                                       /* SCI 1 baud rate Bit 7 */
      } Bits;
      struct {
        byte grpSBR :8;
      } MergedBits;
    } SCI1BDLSTR;
    #define SCI1BDL _SCI1BD.Overlap_STR.SCI1BDLSTR.Byte
    #define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR0
    #define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR1
    #define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR2
    #define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR3
    #define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR4
    #define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR5
    #define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR6
    #define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR7
    #define SCI1BDL_SBR _SCI1BD.Overlap_STR.SCI1BDLSTR.MergedBits.grpSBR
    
  } Overlap_STR;

  struct {
    word SBR0        :1;                                       /* SCI 1 baud rate Bit 0 */
    word SBR1        :1;                                       /* SCI 1 baud rate Bit 1 */
    word SBR2        :1;                                       /* SCI 1 baud rate Bit 2 */
    word SBR3        :1;                                       /* SCI 1 baud rate Bit 3 */
    word SBR4        :1;                                       /* SCI 1 baud rate Bit 4 */
    word SBR5        :1;                                       /* SCI 1 baud rate Bit 5 */
    word SBR6        :1;                                       /* SCI 1 baud rate Bit 6 */
    word SBR7        :1;                                       /* SCI 1 baud rate Bit 7 */
    word SBR8        :1;                                       /* SCI 1 baud rate Bit 8 */
    word SBR9        :1;                                       /* SCI 1 baud rate Bit 9 */
    word SBR10       :1;                                       /* SCI 1 baud rate Bit 10 */
    word SBR11       :1;                                       /* SCI 1 baud rate Bit 11 */
    word SBR12       :1;                                       /* SCI 1 baud rate Bit 12 */
    word             :1; 
    word             :1; 
    word             :1; 
  } Bits;
  struct {
    word grpSBR  :13;
    word         :1;
    word         :1;
    word         :1;
  } MergedBits;
} SCI1BDSTR;
extern volatile SCI1BDSTR _SCI1BD @(REG_BASE + 0x000000D0);
#define SCI1BD _SCI1BD.Word
#define SCI1BD_SBR0 _SCI1BD.Bits.SBR0
#define SCI1BD_SBR1 _SCI1BD.Bits.SBR1
#define SCI1BD_SBR2 _SCI1BD.Bits.SBR2
#define SCI1BD_SBR3 _SCI1BD.Bits.SBR3
#define SCI1BD_SBR4 _SCI1BD.Bits.SBR4
#define SCI1BD_SBR5 _SCI1BD.Bits.SBR5
#define SCI1BD_SBR6 _SCI1BD.Bits.SBR6
#define SCI1BD_SBR7 _SCI1BD.Bits.SBR7
#define SCI1BD_SBR8 _SCI1BD.Bits.SBR8
#define SCI1BD_SBR9 _SCI1BD.Bits.SBR9
#define SCI1BD_SBR10 _SCI1BD.Bits.SBR10
#define SCI1BD_SBR11 _SCI1BD.Bits.SBR11
#define SCI1BD_SBR12 _SCI1BD.Bits.SBR12
#define SCI1BD_SBR _SCI1BD.MergedBits.grpSBR


/*** ATD1CTL23 - ATD 1 Control Register 23; 0x00000122 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD1CTL2 - ATD 1 Control Register 2; 0x00000122 ***/
    union {
      byte Byte;
      struct {
        byte ASCIF       :1;                                       /* ATD 1 Sequence Complete Interrupt Flag */
        byte ASCIE       :1;                                       /* ATD 1 Sequence Complete Interrupt Enable */
        byte ETRIGE      :1;                                       /* External Trigger Mode enable */
        byte ETRIGP      :1;                                       /* External Trigger Polarity */
        byte ETRIGLE     :1;                                       /* External Trigger Level/Edge control */
        byte AWAI        :1;                                       /* ATD 1 Wait Mode */
        byte AFFC        :1;                                       /* ATD 1 Fast Conversion Complete Flag Clear */
        byte ADPU        :1;                                       /* ATD 1 Disable / Power Down */
      } Bits;
    } ATD1CTL2STR;
    #define ATD1CTL2 _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Byte
    #define ATD1CTL2_ASCIF _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIF
    #define ATD1CTL2_ASCIE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIE
    #define ATD1CTL2_ETRIGE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGE
    #define ATD1CTL2_ETRIGP _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGP
    #define ATD1CTL2_ETRIGLE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGLE
    #define ATD1CTL2_AWAI _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AWAI
    #define ATD1CTL2_AFFC _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AFFC
    #define ATD1CTL2_ADPU _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ADPU
    
    /*** ATD1CTL3 - ATD 1 Control Register 3; 0x00000123 ***/
    union {
      byte Byte;
      struct {
        byte FRZ0        :1;                                       /* Background Debug Freeze Enable */
        byte FRZ1        :1;                                       /* Background Debug Freeze Enable */
        byte FIFO        :1;                                       /* Result Register FIFO Mode */
        byte S1C         :1;                                       /* Conversion Sequence Length 1 */
        byte S2C         :1;                                       /* Conversion Sequence Length 2 */
        byte S4C         :1;                                       /* Conversion Sequence Length 4 */
        byte S8C         :1;                                       /* Conversion Sequence Length 8 */
        byte             :1; 
      } Bits;
      struct {
        byte grpFRZ :2;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
      } MergedBits;
    } ATD1CTL3STR;
    #define ATD1CTL3 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Byte
    #define ATD1CTL3_FRZ0 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ0
    #define ATD1CTL3_FRZ1 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ1
    #define ATD1CTL3_FIFO _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FIFO
    #define ATD1CTL3_S1C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S1C
    #define ATD1CTL3_S2C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S2C
    #define ATD1CTL3_S4C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S4C
    #define ATD1CTL3_S8C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S8C
    #define ATD1CTL3_FRZ _ATD1CTL23.Overlap_STR.ATD1CTL3STR.MergedBits.grpFRZ
    
  } Overlap_STR;

  struct {
    word FRZ0        :1;                                       /* Background Debug Freeze Enable */
    word FRZ1        :1;                                       /* Background Debug Freeze Enable */
    word FIFO        :1;                                       /* Result Register FIFO Mode */
    word S1C         :1;                                       /* Conversion Sequence Length 1 */
    word S2C         :1;                                       /* Conversion Sequence Length 2 */
    word S4C         :1;                                       /* Conversion Sequence Length 4 */
    word S8C         :1;                                       /* Conversion Sequence Length 8 */
    word             :1; 
    word ASCIF       :1;                                       /* ATD 1 Sequence Complete Interrupt Flag */
    word ASCIE       :1;                                       /* ATD 1 Sequence Complete Interrupt Enable */
    word ETRIGE      :1;                                       /* External Trigger Mode enable */
    word ETRIGP      :1;                                       /* External Trigger Polarity */
    word ETRIGLE     :1;                                       /* External Trigger Level/Edge control */
    word AWAI        :1;                                       /* ATD 1 Wait Mode */
    word AFFC        :1;                                       /* ATD 1 Fast Conversion Complete Flag Clear */
    word ADPU        :1;                                       /* ATD 1 Disable / Power Down */
  } Bits;
  struct {
    word grpFRZ  :2;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
  } MergedBits;
} ATD1CTL23STR;
extern volatile ATD1CTL23STR _ATD1CTL23 @(REG_BASE + 0x00000122);
#define ATD1CTL23 _ATD1CTL23.Word
#define ATD1CTL23_FRZ0 _ATD1CTL23.Bits.FRZ0
#define ATD1CTL23_FRZ1 _ATD1CTL23.Bits.FRZ1
#define ATD1CTL23_FIFO _ATD1CTL23.Bits.FIFO
#define ATD1CTL23_S1C _ATD1CTL23.Bits.S1C
#define ATD1CTL23_S2C _ATD1CTL23.Bits.S2C
#define ATD1CTL23_S4C _ATD1CTL23.Bits.S4C
#define ATD1CTL23_S8C _ATD1CTL23.Bits.S8C
#define ATD1CTL23_ASCIF _ATD1CTL23.Bits.ASCIF
#define ATD1CTL23_ASCIE _ATD1CTL23.Bits.ASCIE
#define ATD1CTL23_ETRIGE _ATD1CTL23.Bits.ETRIGE
#define ATD1CTL23_ETRIGP _ATD1CTL23.Bits.ETRIGP
#define ATD1CTL23_ETRIGLE _ATD1CTL23.Bits.ETRIGLE
#define ATD1CTL23_AWAI _ATD1CTL23.Bits.AWAI
#define ATD1CTL23_AFFC _ATD1CTL23.Bits.AFFC
#define ATD1CTL23_ADPU _ATD1CTL23.Bits.ADPU
#define ATD1CTL23_FRZ _ATD1CTL23.MergedBits.grpFRZ


/*** ATD1CTL45 - ATD 1 Control Register 45; 0x00000124 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD1CTL4 - ATD 1 Control Register 4; 0x00000124 ***/
    union {
      byte Byte;
      struct {
        byte PRS0        :1;                                       /* ATD 1 Clock Prescaler 0 */
        byte PRS1        :1;                                       /* ATD 1 Clock Prescaler 1 */
        byte PRS2        :1;                                       /* ATD 1 Clock Prescaler 2 */
        byte PRS3        :1;                                       /* ATD 1 Clock Prescaler 3 */
        byte PRS4        :1;                                       /* ATD 1 Clock Prescaler 4 */
        byte SMP0        :1;                                       /* Sample Time Select 0 */
        byte SMP1        :1;                                       /* Sample Time Select 1 */
        byte SRES8       :1;                                       /* ATD 1 Resolution Select */
      } Bits;
      struct {
        byte grpPRS :5;
        byte grpSMP :2;
        byte grpSRES_8 :1;
      } MergedBits;
    } ATD1CTL4STR;
    #define ATD1CTL4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Byte
    #define ATD1CTL4_PRS0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS0
    #define ATD1CTL4_PRS1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS1
    #define ATD1CTL4_PRS2 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS2
    #define ATD1CTL4_PRS3 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS3
    #define ATD1CTL4_PRS4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS4
    #define ATD1CTL4_SMP0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP0
    #define ATD1CTL4_SMP1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP1
    #define ATD1CTL4_SRES8 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SRES8
    #define ATD1CTL4_PRS _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpPRS
    #define ATD1CTL4_SMP _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpSMP
    
    /*** ATD1CTL5 - ATD 1 Control Register 5; 0x00000125 ***/
    union {
      byte Byte;
      struct {
        byte CA          :1;                                       /* Analog Input Channel Select Code A */
        byte CB          :1;                                       /* Analog Input Channel Select Code B */
        byte CC          :1;                                       /* Analog Input Channel Select Code C */
        byte             :1; 
        byte MULT        :1;                                       /* Multi-Channel Sample Mode */
        byte SCAN        :1;                                       /* Continuous Conversion Sequence Mode */
        byte DSGN        :1;                                       /* Signed/Unsigned Result Data Mode */
        byte DJM         :1;                                       /* Result Register Data Justification Mode */
      } Bits;
    } ATD1CTL5STR;
    #define ATD1CTL5 _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Byte
    #define ATD1CTL5_CA _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CA
    #define ATD1CTL5_CB _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CB
    #define ATD1CTL5_CC _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CC
    #define ATD1CTL5_MULT _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.MULT
    #define ATD1CTL5_SCAN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.SCAN
    #define ATD1CTL5_DSGN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DSGN
    #define ATD1CTL5_DJM _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DJM
    
  } Overlap_STR;

  struct {
    word CA          :1;                                       /* Analog Input Channel Select Code A */
    word CB          :1;                                       /* Analog Input Channel Select Code B */
    word CC          :1;                                       /* Analog Input Channel Select Code C */
    word             :1; 
    word MULT        :1;                                       /* Multi-Channel Sample Mode */
    word SCAN        :1;                                       /* Continuous Conversion Sequence Mode */
    word DSGN        :1;                                       /* Signed/Unsigned Result Data Mode */
    word DJM         :1;                                       /* Result Register Data Justification Mode */
    word PRS0        :1;                                       /* ATD 1 Clock Prescaler 0 */
    word PRS1        :1;                                       /* ATD 1 Clock Prescaler 1 */
    word PRS2        :1;                                       /* ATD 1 Clock Prescaler 2 */
    word PRS3        :1;                                       /* ATD 1 Clock Prescaler 3 */
    word PRS4        :1;                                       /* ATD 1 Clock Prescaler 4 */
    word SMP0        :1;                                       /* Sample Time Select 0 */
    word SMP1        :1;                                       /* Sample Time Select 1 */
    word SRES8       :1;                                       /* ATD 1 Resolution Select */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpPRS  :5;
    word grpSMP  :2;
    word grpSRES_8 :1;
  } MergedBits;
} ATD1CTL45STR;
extern volatile ATD1CTL45STR _ATD1CTL45 @(REG_BASE + 0x00000124);
#define ATD1CTL45 _ATD1CTL45.Word
#define ATD1CTL45_CA _ATD1CTL45.Bits.CA
#define ATD1CTL45_CB _ATD1CTL45.Bits.CB
#define ATD1CTL45_CC _ATD1CTL45.Bits.CC
#define ATD1CTL45_MULT _ATD1CTL45.Bits.MULT
#define ATD1CTL45_SCAN _ATD1CTL45.Bits.SCAN
#define ATD1CTL45_DSGN _ATD1CTL45.Bits.DSGN
#define ATD1CTL45_DJM _ATD1CTL45.Bits.DJM
#define ATD1CTL45_PRS0 _ATD1CTL45.Bits.PRS0
#define ATD1CTL45_PRS1 _ATD1CTL45.Bits.PRS1
#define ATD1CTL45_PRS2 _ATD1CTL45.Bits.PRS2
#define ATD1CTL45_PRS3 _ATD1CTL45.Bits.PRS3
#define ATD1CTL45_PRS4 _ATD1CTL45.Bits.PRS4
#define ATD1CTL45_SMP0 _ATD1CTL45.Bits.SMP0
#define ATD1CTL45_SMP1 _ATD1CTL45.Bits.SMP1
#define ATD1CTL45_SRES8 _ATD1CTL45.Bits.SRES8
#define ATD1CTL45_PRS _ATD1CTL45.MergedBits.grpPRS
#define ATD1CTL45_SMP _ATD1CTL45.MergedBits.grpSMP


/*** ATD1DR0 - ATD 1 Conversion Result Register 0; 0x00000130 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD1DR0H - ATD 1 Conversion Result Register 0 High; 0x00000130 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD1DR0HSTR;
    #define ATD1DR0H _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Byte
    #define ATD1DR0H_BIT8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT8
    #define ATD1DR0H_BIT9 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT9
    #define ATD1DR0H_BIT10 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT10
    #define ATD1DR0H_BIT11 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT11
    #define ATD1DR0H_BIT12 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT12
    #define ATD1DR0H_BIT13 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT13
    #define ATD1DR0H_BIT14 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT14
    #define ATD1DR0H_BIT15 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT15
    #define ATD1DR0H_BIT_8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.MergedBits.grpBIT_8
    #define ATD1DR0H_BIT ATD1DR0H_BIT_8
    
    /*** ATD1DR0L - ATD 1 Conversion Result Register 0 Low; 0x00000131 ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD1DR0LSTR;
    #define ATD1DR0L _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Byte
    #define ATD1DR0L_BIT6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT6
    #define ATD1DR0L_BIT7 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT7
    #define ATD1DR0L_BIT_6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.MergedBits.grpBIT_6
    #define ATD1DR0L_BIT ATD1DR0L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD1DR0STR;
extern volatile ATD1DR0STR _ATD1DR0 @(REG_BASE + 0x00000130);
#define ATD1DR0 _ATD1DR0.Word
#define ATD1DR0_BIT6 _ATD1DR0.Bits.BIT6
#define ATD1DR0_BIT7 _ATD1DR0.Bits.BIT7
#define ATD1DR0_BIT8 _ATD1DR0.Bits.BIT8
#define ATD1DR0_BIT9 _ATD1DR0.Bits.BIT9
#define ATD1DR0_BIT10 _ATD1DR0.Bits.BIT10
#define ATD1DR0_BIT11 _ATD1DR0.Bits.BIT11
#define ATD1DR0_BIT12 _ATD1DR0.Bits.BIT12
#define ATD1DR0_BIT13 _ATD1DR0.Bits.BIT13
#define ATD1DR0_BIT14 _ATD1DR0.Bits.BIT14
#define ATD1DR0_BIT15 _ATD1DR0.Bits.BIT15
#define ATD1DR0_BIT_6 _ATD1DR0.MergedBits.grpBIT_6
#define ATD1DR0_BIT ATD1DR0_BIT_6


/*** ATD1DR1 - ATD 1 Conversion Result Register 1; 0x00000132 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD1DR1H - ATD 1 Conversion Result Register 1 High; 0x00000132 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD1DR1HSTR;
    #define ATD1DR1H _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Byte
    #define ATD1DR1H_BIT8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT8
    #define ATD1DR1H_BIT9 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT9
    #define ATD1DR1H_BIT10 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT10
    #define ATD1DR1H_BIT11 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT11
    #define ATD1DR1H_BIT12 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT12
    #define ATD1DR1H_BIT13 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT13
    #define ATD1DR1H_BIT14 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT14
    #define ATD1DR1H_BIT15 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT15
    #define ATD1DR1H_BIT_8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.MergedBits.grpBIT_8
    #define ATD1DR1H_BIT ATD1DR1H_BIT_8
    
    /*** ATD1DR1L - ATD 1 Conversion Result Register 1 Low; 0x00000133 ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD1DR1LSTR;
    #define ATD1DR1L _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Byte
    #define ATD1DR1L_BIT6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT6
    #define ATD1DR1L_BIT7 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT7
    #define ATD1DR1L_BIT_6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.MergedBits.grpBIT_6
    #define ATD1DR1L_BIT ATD1DR1L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD1DR1STR;
extern volatile ATD1DR1STR _ATD1DR1 @(REG_BASE + 0x00000132);
#define ATD1DR1 _ATD1DR1.Word
#define ATD1DR1_BIT6 _ATD1DR1.Bits.BIT6
#define ATD1DR1_BIT7 _ATD1DR1.Bits.BIT7
#define ATD1DR1_BIT8 _ATD1DR1.Bits.BIT8
#define ATD1DR1_BIT9 _ATD1DR1.Bits.BIT9
#define ATD1DR1_BIT10 _ATD1DR1.Bits.BIT10
#define ATD1DR1_BIT11 _ATD1DR1.Bits.BIT11
#define ATD1DR1_BIT12 _ATD1DR1.Bits.BIT12
#define ATD1DR1_BIT13 _ATD1DR1.Bits.BIT13
#define ATD1DR1_BIT14 _ATD1DR1.Bits.BIT14
#define ATD1DR1_BIT15 _ATD1DR1.Bits.BIT15
#define ATD1DR1_BIT_6 _ATD1DR1.MergedBits.grpBIT_6
#define ATD1DR1_BIT ATD1DR1_BIT_6


/*** ATD1DR2 - ATD 1 Conversion Result Register 2; 0x00000134 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD1DR2H - ATD 1 Conversion Result Register 2 High; 0x00000134 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD1DR2HSTR;
    #define ATD1DR2H _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Byte
    #define ATD1DR2H_BIT8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT8
    #define ATD1DR2H_BIT9 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT9
    #define ATD1DR2H_BIT10 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT10
    #define ATD1DR2H_BIT11 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT11
    #define ATD1DR2H_BIT12 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT12
    #define ATD1DR2H_BIT13 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT13
    #define ATD1DR2H_BIT14 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT14
    #define ATD1DR2H_BIT15 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT15
    #define ATD1DR2H_BIT_8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.MergedBits.grpBIT_8
    #define ATD1DR2H_BIT ATD1DR2H_BIT_8
    
    /*** ATD1DR2L - ATD 1 Conversion Result Register 2 Low; 0x00000135 ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD1DR2LSTR;
    #define ATD1DR2L _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Byte
    #define ATD1DR2L_BIT6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT6
    #define ATD1DR2L_BIT7 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT7
    #define ATD1DR2L_BIT_6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.MergedBits.grpBIT_6
    #define ATD1DR2L_BIT ATD1DR2L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD1DR2STR;
extern volatile ATD1DR2STR _ATD1DR2 @(REG_BASE + 0x00000134);
#define ATD1DR2 _ATD1DR2.Word
#define ATD1DR2_BIT6 _ATD1DR2.Bits.BIT6
#define ATD1DR2_BIT7 _ATD1DR2.Bits.BIT7
#define ATD1DR2_BIT8 _ATD1DR2.Bits.BIT8
#define ATD1DR2_BIT9 _ATD1DR2.Bits.BIT9
#define ATD1DR2_BIT10 _ATD1DR2.Bits.BIT10
#define ATD1DR2_BIT11 _ATD1DR2.Bits.BIT11
#define ATD1DR2_BIT12 _ATD1DR2.Bits.BIT12
#define ATD1DR2_BIT13 _ATD1DR2.Bits.BIT13
#define ATD1DR2_BIT14 _ATD1DR2.Bits.BIT14
#define ATD1DR2_BIT15 _ATD1DR2.Bits.BIT15
#define ATD1DR2_BIT_6 _ATD1DR2.MergedBits.grpBIT_6
#define ATD1DR2_BIT ATD1DR2_BIT_6


/*** ATD1DR3 - ATD 1 Conversion Result Register 3; 0x00000136 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD1DR3H - ATD 1 Conversion Result Register 3 High; 0x00000136 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD1DR3HSTR;
    #define ATD1DR3H _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Byte
    #define ATD1DR3H_BIT8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT8
    #define ATD1DR3H_BIT9 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT9
    #define ATD1DR3H_BIT10 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT10
    #define ATD1DR3H_BIT11 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT11
    #define ATD1DR3H_BIT12 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT12
    #define ATD1DR3H_BIT13 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT13
    #define ATD1DR3H_BIT14 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT14
    #define ATD1DR3H_BIT15 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT15
    #define ATD1DR3H_BIT_8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.MergedBits.grpBIT_8
    #define ATD1DR3H_BIT ATD1DR3H_BIT_8
    
    /*** ATD1DR3L - ATD 1 Conversion Result Register 3 Low; 0x00000137 ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD1DR3LSTR;
    #define ATD1DR3L _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Byte
    #define ATD1DR3L_BIT6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT6
    #define ATD1DR3L_BIT7 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT7
    #define ATD1DR3L_BIT_6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.MergedBits.grpBIT_6
    #define ATD1DR3L_BIT ATD1DR3L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD1DR3STR;
extern volatile ATD1DR3STR _ATD1DR3 @(REG_BASE + 0x00000136);
#define ATD1DR3 _ATD1DR3.Word
#define ATD1DR3_BIT6 _ATD1DR3.Bits.BIT6
#define ATD1DR3_BIT7 _ATD1DR3.Bits.BIT7
#define ATD1DR3_BIT8 _ATD1DR3.Bits.BIT8
#define ATD1DR3_BIT9 _ATD1DR3.Bits.BIT9
#define ATD1DR3_BIT10 _ATD1DR3.Bits.BIT10
#define ATD1DR3_BIT11 _ATD1DR3.Bits.BIT11
#define ATD1DR3_BIT12 _ATD1DR3.Bits.BIT12
#define ATD1DR3_BIT13 _ATD1DR3.Bits.BIT13
#define ATD1DR3_BIT14 _ATD1DR3.Bits.BIT14
#define ATD1DR3_BIT15 _ATD1DR3.Bits.BIT15
#define ATD1DR3_BIT_6 _ATD1DR3.MergedBits.grpBIT_6
#define ATD1DR3_BIT ATD1DR3_BIT_6


/*** ATD1DR4 - ATD 1 Conversion Result Register 4; 0x00000138 ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD1DR4H - ATD 1 Conversion Result Register 4 High; 0x00000138 ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD1DR4HSTR;
    #define ATD1DR4H _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Byte
    #define ATD1DR4H_BIT8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT8
    #define ATD1DR4H_BIT9 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT9
    #define ATD1DR4H_BIT10 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT10
    #define ATD1DR4H_BIT11 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT11
    #define ATD1DR4H_BIT12 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT12
    #define ATD1DR4H_BIT13 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT13
    #define ATD1DR4H_BIT14 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT14
    #define ATD1DR4H_BIT15 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT15
    #define ATD1DR4H_BIT_8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.MergedBits.grpBIT_8
    #define ATD1DR4H_BIT ATD1DR4H_BIT_8
    
    /*** ATD1DR4L - ATD 1 Conversion Result Register 4 Low; 0x00000139 ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD1DR4LSTR;
    #define ATD1DR4L _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Byte
    #define ATD1DR4L_BIT6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT6
    #define ATD1DR4L_BIT7 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT7
    #define ATD1DR4L_BIT_6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.MergedBits.grpBIT_6
    #define ATD1DR4L_BIT ATD1DR4L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD1DR4STR;
extern volatile ATD1DR4STR _ATD1DR4 @(REG_BASE + 0x00000138);
#define ATD1DR4 _ATD1DR4.Word
#define ATD1DR4_BIT6 _ATD1DR4.Bits.BIT6
#define ATD1DR4_BIT7 _ATD1DR4.Bits.BIT7
#define ATD1DR4_BIT8 _ATD1DR4.Bits.BIT8
#define ATD1DR4_BIT9 _ATD1DR4.Bits.BIT9
#define ATD1DR4_BIT10 _ATD1DR4.Bits.BIT10
#define ATD1DR4_BIT11 _ATD1DR4.Bits.BIT11
#define ATD1DR4_BIT12 _ATD1DR4.Bits.BIT12
#define ATD1DR4_BIT13 _ATD1DR4.Bits.BIT13
#define ATD1DR4_BIT14 _ATD1DR4.Bits.BIT14
#define ATD1DR4_BIT15 _ATD1DR4.Bits.BIT15
#define ATD1DR4_BIT_6 _ATD1DR4.MergedBits.grpBIT_6
#define ATD1DR4_BIT ATD1DR4_BIT_6


/*** ATD1DR5 - ATD 1 Conversion Result Register 5; 0x0000013A ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD1DR5H - ATD 1 Conversion Result Register 5 High; 0x0000013A ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD1DR5HSTR;
    #define ATD1DR5H _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Byte
    #define ATD1DR5H_BIT8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT8
    #define ATD1DR5H_BIT9 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT9
    #define ATD1DR5H_BIT10 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT10
    #define ATD1DR5H_BIT11 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT11
    #define ATD1DR5H_BIT12 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT12
    #define ATD1DR5H_BIT13 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT13
    #define ATD1DR5H_BIT14 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT14
    #define ATD1DR5H_BIT15 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT15
    #define ATD1DR5H_BIT_8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.MergedBits.grpBIT_8
    #define ATD1DR5H_BIT ATD1DR5H_BIT_8
    
    /*** ATD1DR5L - ATD 1 Conversion Result Register 5 Low; 0x0000013B ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD1DR5LSTR;
    #define ATD1DR5L _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Byte
    #define ATD1DR5L_BIT6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT6
    #define ATD1DR5L_BIT7 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT7
    #define ATD1DR5L_BIT_6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.MergedBits.grpBIT_6
    #define ATD1DR5L_BIT ATD1DR5L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD1DR5STR;
extern volatile ATD1DR5STR _ATD1DR5 @(REG_BASE + 0x0000013A);
#define ATD1DR5 _ATD1DR5.Word
#define ATD1DR5_BIT6 _ATD1DR5.Bits.BIT6
#define ATD1DR5_BIT7 _ATD1DR5.Bits.BIT7
#define ATD1DR5_BIT8 _ATD1DR5.Bits.BIT8
#define ATD1DR5_BIT9 _ATD1DR5.Bits.BIT9
#define ATD1DR5_BIT10 _ATD1DR5.Bits.BIT10
#define ATD1DR5_BIT11 _ATD1DR5.Bits.BIT11
#define ATD1DR5_BIT12 _ATD1DR5.Bits.BIT12
#define ATD1DR5_BIT13 _ATD1DR5.Bits.BIT13
#define ATD1DR5_BIT14 _ATD1DR5.Bits.BIT14
#define ATD1DR5_BIT15 _ATD1DR5.Bits.BIT15
#define ATD1DR5_BIT_6 _ATD1DR5.MergedBits.grpBIT_6
#define ATD1DR5_BIT ATD1DR5_BIT_6


/*** ATD1DR6 - ATD 1 Conversion Result Register 6; 0x0000013C ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD1DR6H - ATD 1 Conversion Result Register 6 High; 0x0000013C ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD1DR6HSTR;
    #define ATD1DR6H _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Byte
    #define ATD1DR6H_BIT8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT8
    #define ATD1DR6H_BIT9 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT9
    #define ATD1DR6H_BIT10 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT10
    #define ATD1DR6H_BIT11 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT11
    #define ATD1DR6H_BIT12 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT12
    #define ATD1DR6H_BIT13 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT13
    #define ATD1DR6H_BIT14 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT14
    #define ATD1DR6H_BIT15 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT15
    #define ATD1DR6H_BIT_8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.MergedBits.grpBIT_8
    #define ATD1DR6H_BIT ATD1DR6H_BIT_8
    
    /*** ATD1DR6L - ATD 1 Conversion Result Register 6 Low; 0x0000013D ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD1DR6LSTR;
    #define ATD1DR6L _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Byte
    #define ATD1DR6L_BIT6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT6
    #define ATD1DR6L_BIT7 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT7
    #define ATD1DR6L_BIT_6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.MergedBits.grpBIT_6
    #define ATD1DR6L_BIT ATD1DR6L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD1DR6STR;
extern volatile ATD1DR6STR _ATD1DR6 @(REG_BASE + 0x0000013C);
#define ATD1DR6 _ATD1DR6.Word
#define ATD1DR6_BIT6 _ATD1DR6.Bits.BIT6
#define ATD1DR6_BIT7 _ATD1DR6.Bits.BIT7
#define ATD1DR6_BIT8 _ATD1DR6.Bits.BIT8
#define ATD1DR6_BIT9 _ATD1DR6.Bits.BIT9
#define ATD1DR6_BIT10 _ATD1DR6.Bits.BIT10
#define ATD1DR6_BIT11 _ATD1DR6.Bits.BIT11
#define ATD1DR6_BIT12 _ATD1DR6.Bits.BIT12
#define ATD1DR6_BIT13 _ATD1DR6.Bits.BIT13
#define ATD1DR6_BIT14 _ATD1DR6.Bits.BIT14
#define ATD1DR6_BIT15 _ATD1DR6.Bits.BIT15
#define ATD1DR6_BIT_6 _ATD1DR6.MergedBits.grpBIT_6
#define ATD1DR6_BIT ATD1DR6_BIT_6


/*** ATD1DR7 - ATD 1 Conversion Result Register 7; 0x0000013E ***/
typedef union {
  word Word;
   /* Overlapped registers: */
  struct {
    /*** ATD1DR7H - ATD 1 Conversion Result Register 7 High; 0x0000013E ***/
    union {
      byte Byte;
      struct {
        byte BIT8        :1;                                       /* Bit 8 */
        byte BIT9        :1;                                       /* Bit 9 */
        byte BIT10       :1;                                       /* Bit 10 */
        byte BIT11       :1;                                       /* Bit 11 */
        byte BIT12       :1;                                       /* Bit 12 */
        byte BIT13       :1;                                       /* Bit 13 */
        byte BIT14       :1;                                       /* Bit 14 */
        byte BIT15       :1;                                       /* Bit 15 */
      } Bits;
      struct {
        byte grpBIT_8 :8;
      } MergedBits;
    } ATD1DR7HSTR;
    #define ATD1DR7H _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Byte
    #define ATD1DR7H_BIT8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT8
    #define ATD1DR7H_BIT9 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT9
    #define ATD1DR7H_BIT10 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT10
    #define ATD1DR7H_BIT11 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT11
    #define ATD1DR7H_BIT12 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT12
    #define ATD1DR7H_BIT13 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT13
    #define ATD1DR7H_BIT14 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT14
    #define ATD1DR7H_BIT15 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT15
    #define ATD1DR7H_BIT_8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.MergedBits.grpBIT_8
    #define ATD1DR7H_BIT ATD1DR7H_BIT_8
    
    /*** ATD1DR7L - ATD 1 Conversion Result Register 7 Low; 0x0000013F ***/
    union {
      byte Byte;
      struct {
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte             :1; 
        byte BIT6        :1;                                       /* Bit 6 */
        byte BIT7        :1;                                       /* Bit 7 */
      } Bits;
      struct {
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte     :1;
        byte grpBIT_6 :2;
      } MergedBits;
    } ATD1DR7LSTR;
    #define ATD1DR7L _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Byte
    #define ATD1DR7L_BIT6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT6
    #define ATD1DR7L_BIT7 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT7
    #define ATD1DR7L_BIT_6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.MergedBits.grpBIT_6
    #define ATD1DR7L_BIT ATD1DR7L_BIT_6
    
  } Overlap_STR;

  struct {
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word BIT6        :1;                                       /* Bit 6 */
    word BIT7        :1;                                       /* Bit 7 */
    word BIT8        :1;                                       /* Bit 8 */
    word BIT9        :1;                                       /* Bit 9 */
    word BIT10       :1;                                       /* Bit 10 */
    word BIT11       :1;                                       /* Bit 11 */
    word BIT12       :1;                                       /* Bit 12 */
    word BIT13       :1;                                       /* Bit 13 */
    word BIT14       :1;                                       /* Bit 14 */
    word BIT15       :1;                                       /* Bit 15 */
  } Bits;
  struct {
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpBIT_6 :10;
  } MergedBits;
} ATD1DR7STR;
extern volatile ATD1DR7STR _ATD1DR7 @(REG_BASE + 0x0000013E);
#define ATD1DR7 _ATD1DR7.Word
#define ATD1DR7_BIT6 _ATD1DR7.Bits.BIT6
#define ATD1DR7_BIT7 _ATD1DR7.Bits.BIT7
#define ATD1DR7_BIT8 _ATD1DR7.Bits.BIT8
#define ATD1DR7_BIT9 _ATD1DR7.Bits.BIT9
#define ATD1DR7_BIT10 _ATD1DR7.Bits.BIT10
#define ATD1DR7_BIT11 _ATD1DR7.Bits.BIT11
#define ATD1DR7_BIT12 _ATD1DR7.Bits.BIT12
#define ATD1DR7_BIT13 _ATD1DR7.Bits.BIT13
#define ATD1DR7_BIT14 _ATD1DR7.Bits.BIT14
#define ATD1DR7_BIT15 _ATD1DR7.Bits.BIT15
#define ATD1DR7_BIT_6 _ATD1DR7.MergedBits.grpBIT_6
#define ATD1DR7_BIT ATD1DR7_BIT_6


/*** PORTE - Port E Register; 0x00000008 ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Port E Bit 0, XIRQ */
    byte BIT1        :1;                                       /* Port E Bit 1, IRQ */
    byte BIT2        :1;                                       /* Port E Bit 2, R/W */
    byte BIT3        :1;                                       /* Port E Bit 3, LSTRB, TAGLO */
    byte BIT4        :1;                                       /* Port E Bit 4, ECLK */
    byte BIT5        :1;                                       /* Port E Bit 5, MODA, IPIPE0, RCRTO */
    byte BIT6        :1;                                       /* Port E Bit 6, MODB, IPIPE1, SCGTO */
    byte BIT7        :1;                                       /* Port E Bit 7, XCLKS, NOACC */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} PORTESTR;
extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);
#define PORTE _PORTE.Byte
#define PORTE_BIT0 _PORTE.Bits.BIT0
#define PORTE_BIT1 _PORTE.Bits.BIT1
#define PORTE_BIT2 _PORTE.Bits.BIT2
#define PORTE_BIT3 _PORTE.Bits.BIT3
#define PORTE_BIT4 _PORTE.Bits.BIT4
#define PORTE_BIT5 _PORTE.Bits.BIT5
#define PORTE_BIT6 _PORTE.Bits.BIT6
#define PORTE_BIT7 _PORTE.Bits.BIT7
#define PORTE_BIT _PORTE.MergedBits.grpBIT


/*** DDRE - Port E Data Direction Register; 0x00000009 ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Data Direction Port A Bit 0 */
    byte BIT1        :1;                                       /* Data Direction Port A Bit 1 */
    byte BIT2        :1;                                       /* Data Direction Port A Bit 2 */
    byte BIT3        :1;                                       /* Data Direction Port A Bit 3 */
    byte BIT4        :1;                                       /* Data Direction Port A Bit 4 */
    byte BIT5        :1;                                       /* Data Direction Port A Bit 5 */
    byte BIT6        :1;                                       /* Data Direction Port A Bit 6 */
    byte BIT7        :1;                                       /* Data Direction Port A Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} DDRESTR;
extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);
#define DDRE _DDRE.Byte
#define DDRE_BIT0 _DDRE.Bits.BIT0
#define DDRE_BIT1 _DDRE.Bits.BIT1
#define DDRE_BIT2 _DDRE.Bits.BIT2
#define DDRE_BIT3 _DDRE.Bits.BIT3
#define DDRE_BIT4 _DDRE.Bits.BIT4
#define DDRE_BIT5 _DDRE.Bits.BIT5
#define DDRE_BIT6 _DDRE.Bits.BIT6
#define DDRE_BIT7 _DDRE.Bits.BIT7
#define DDRE_BIT _DDRE.MergedBits.grpBIT


/*** PEAR - Port E Assignment Register; 0x0000000A ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte RDWE        :1;                                       /* Read / Write Enable */
    byte LSTRE       :1;                                       /* Low Strobe (LSTRB) Enable */
    byte NECLK       :1;                                       /* No External E Clock */
    byte PIPOE       :1;                                       /* Pipe Status Signal Output Enable */
    byte             :1; 
    byte NOACCE      :1;                                       /* CPU No Access Output Enable */
  } Bits;
} PEARSTR;
extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A);
#define PEAR _PEAR.Byte
#define PEAR_RDWE _PEAR.Bits.RDWE
#define PEAR_LSTRE _PEAR.Bits.LSTRE
#define PEAR_NECLK _PEAR.Bits.NECLK
#define PEAR_PIPOE _PEAR.Bits.PIPOE
#define PEAR_NOACCE _PEAR.Bits.NOACCE


/*** MODE - Mode Register; 0x0000000B ***/
typedef union {
  byte Byte;
  struct {
    byte EME         :1;                                       /* Emulate Port E */
    byte EMK         :1;                                       /* Emulate Port K */
    byte             :1; 
    byte IVIS        :1;                                       /* Internal Visibility */
    byte             :1; 
    byte MODA        :1;                                       /* Mode Select Bit A */
    byte MODB        :1;                                       /* Mode Select Bit B */
    byte MODC        :1;                                       /* Mode Select Bit C */
  } Bits;
} MODESTR;
extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B);
#define MODE _MODE.Byte
#define MODE_EME _MODE.Bits.EME
#define MODE_EMK _MODE.Bits.EMK
#define MODE_IVIS _MODE.Bits.IVIS
#define MODE_MODA _MODE.Bits.MODA
#define MODE_MODB _MODE.Bits.MODB
#define MODE_MODC _MODE.Bits.MODC


/*** PUCR - Pull-Up Control Register; 0x0000000C ***/
typedef union {
  byte Byte;
  struct {
    byte PUPAE       :1;                                       /* Pull-Up Port A Enable */
    byte PUPBE       :1;                                       /* Pull-Up Port B Enable */
    byte             :1; 
    byte             :1; 
    byte PUPEE       :1;                                       /* Pull-Up Port E Enable */
    byte             :1; 
    byte             :1; 
    byte PUPKE       :1;                                       /* Pull-Up Port K Enable */
  } Bits;
} PUCRSTR;
extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C);
#define PUCR _PUCR.Byte
#define PUCR_PUPAE _PUCR.Bits.PUPAE
#define PUCR_PUPBE _PUCR.Bits.PUPBE
#define PUCR_PUPEE _PUCR.Bits.PUPEE
#define PUCR_PUPKE _PUCR.Bits.PUPKE


/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/
typedef union {
  byte Byte;
  struct {
    byte RDPA        :1;                                       /* Reduced Drive of Port A */
    byte RDPB        :1;                                       /* Reduced Drive of Port B */
    byte             :1; 
    byte             :1; 
    byte RDPE        :1;                                       /* Reduced Drive of Port E */
    byte             :1; 
    byte             :1; 
    byte RDPK        :1;                                       /* Reduced Drive of Port K */
  } Bits;
} RDRIVSTR;
extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D);
#define RDRIV _RDRIV.Byte
#define RDRIV_RDPA _RDRIV.Bits.RDPA
#define RDRIV_RDPB _RDRIV.Bits.RDPB
#define RDRIV_RDPE _RDRIV.Bits.RDPE
#define RDRIV_RDPK _RDRIV.Bits.RDPK


/*** EBICTL - External Bus Interface Control; 0x0000000E ***/
typedef union {
  byte Byte;
  struct {
    byte ESTR        :1;                                       /* E Stretches */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} EBICTLSTR;
extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E);
#define EBICTL _EBICTL.Byte
#define EBICTL_ESTR _EBICTL.Bits.ESTR


/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/
typedef union {
  byte Byte;
  struct {
    byte RAMHAL      :1;                                       /* Internal RAM map alignment */
    byte             :1; 
    byte             :1; 
    byte RAM11       :1;                                       /* Internal RAM map position Bit 11 */
    byte RAM12       :1;                                       /* Internal RAM map position Bit 12 */
    byte RAM13       :1;                                       /* Internal RAM map position Bit 13 */
    byte RAM14       :1;                                       /* Internal RAM map position Bit 14 */
    byte RAM15       :1;                                       /* Internal RAM map position Bit 15 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpRAM_11 :5;
  } MergedBits;
} INITRMSTR;
extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010);
#define INITRM _INITRM.Byte
#define INITRM_RAMHAL _INITRM.Bits.RAMHAL
#define INITRM_RAM11 _INITRM.Bits.RAM11
#define INITRM_RAM12 _INITRM.Bits.RAM12
#define INITRM_RAM13 _INITRM.Bits.RAM13
#define INITRM_RAM14 _INITRM.Bits.RAM14
#define INITRM_RAM15 _INITRM.Bits.RAM15
#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11
#define INITRM_RAM INITRM_RAM_11


/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte REG11       :1;                                       /* Internal register map position REG11 */
    byte REG12       :1;                                       /* Internal register map position REG12 */
    byte REG13       :1;                                       /* Internal register map position REG13 */
    byte REG14       :1;                                       /* Internal register map position REG14 */
    byte             :1; 
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpREG_11 :4;
    byte         :1;
  } MergedBits;
} INITRGSTR;
extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011);
#define INITRG _INITRG.Byte
#define INITRG_REG11 _INITRG.Bits.REG11
#define INITRG_REG12 _INITRG.Bits.REG12
#define INITRG_REG13 _INITRG.Bits.REG13
#define INITRG_REG14 _INITRG.Bits.REG14
#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11
#define INITRG_REG INITRG_REG_11


/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/
typedef union {
  byte Byte;
  struct {
    byte EEON        :1;                                       /* Internal EEPROM On */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte EE12        :1;                                       /* Internal EEPROM map position Bit 12 */
    byte EE13        :1;                                       /* Internal EEPROM map position Bit 13 */
    byte EE14        :1;                                       /* Internal EEPROM map position Bit 14 */
    byte EE15        :1;                                       /* Internal EEPROM map position Bit 15 */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpEE_12 :4;
  } MergedBits;
} INITEESTR;
extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012);
#define INITEE _INITEE.Byte
#define INITEE_EEON _INITEE.Bits.EEON
#define INITEE_EE12 _INITEE.Bits.EE12
#define INITEE_EE13 _INITEE.Bits.EE13
#define INITEE_EE14 _INITEE.Bits.EE14
#define INITEE_EE15 _INITEE.Bits.EE15
#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12
#define INITEE_EE INITEE_EE_12


/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/
typedef union {
  byte Byte;
  struct {
    byte ROMON       :1;                                       /* Enable Flash EEPROM */
    byte ROMHM       :1;                                       /* Flash EEPROM only in second half of memory map */
    byte EXSTR0      :1;                                       /* External Access Stretch Bit 0 */
    byte EXSTR1      :1;                                       /* External Access Stretch Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpEXSTR :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} MISCSTR;
extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013);
#define MISC _MISC.Byte
#define MISC_ROMON _MISC.Bits.ROMON
#define MISC_ROMHM _MISC.Bits.ROMHM
#define MISC_EXSTR0 _MISC.Bits.EXSTR0
#define MISC_EXSTR1 _MISC.Bits.EXSTR1
#define MISC_EXSTR _MISC.MergedBits.grpEXSTR


/*** MTST0 - MTST0; 0x00000014 ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* MTST0 Bit 0 */
    byte BIT1        :1;                                       /* MTST0 Bit 1 */
    byte BIT2        :1;                                       /* MTST0 Bit 2 */
    byte BIT3        :1;                                       /* MTST0 Bit 3 */
    byte BIT4        :1;                                       /* MTST0 Bit 4 */
    byte BIT5        :1;                                       /* MTST0 Bit 5 */
    byte BIT6        :1;                                       /* MTST0 Bit 6 */
    byte BIT7        :1;                                       /* MTST0 Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} MTST0STR;
extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014);
#define MTST0 _MTST0.Byte
#define MTST0_BIT0 _MTST0.Bits.BIT0
#define MTST0_BIT1 _MTST0.Bits.BIT1
#define MTST0_BIT2 _MTST0.Bits.BIT2
#define MTST0_BIT3 _MTST0.Bits.BIT3
#define MTST0_BIT4 _MTST0.Bits.BIT4
#define MTST0_BIT5 _MTST0.Bits.BIT5
#define MTST0_BIT6 _MTST0.Bits.BIT6
#define MTST0_BIT7 _MTST0.Bits.BIT7
#define MTST0_BIT _MTST0.MergedBits.grpBIT


/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/
typedef union {
  byte Byte;
  struct {
    byte ADR0        :1;                                       /* Test register select Bit 0 */
    byte ADR1        :1;                                       /* Test register select Bit 1 */
    byte ADR2        :1;                                       /* Test register select Bit 2 */
    byte ADR3        :1;                                       /* Test register select Bit 3 */
    byte WRTINT      :1;                                       /* Write to the Interrupt Test Registers */
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpADR  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ITCRSTR;
extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015);
#define ITCR _ITCR.Byte
#define ITCR_ADR0 _ITCR.Bits.ADR0
#define ITCR_ADR1 _ITCR.Bits.ADR1
#define ITCR_ADR2 _ITCR.Bits.ADR2
#define ITCR_ADR3 _ITCR.Bits.ADR3
#define ITCR_WRTINT _ITCR.Bits.WRTINT
#define ITCR_ADR _ITCR.MergedBits.grpADR


/*** ITEST - Interrupt Test Register; 0x00000016 ***/
typedef union {
  byte Byte;
  struct {
    byte INT0        :1;                                       /* Interrupt Test Register Bit 0 */
    byte INT2        :1;                                       /* Interrupt Test Register Bit 1 */
    byte INT4        :1;                                       /* Interrupt Test Register Bit 2 */
    byte INT6        :1;                                       /* Interrupt Test Register Bit 3 */
    byte INT8        :1;                                       /* Interrupt Test Register Bit 4 */
    byte INTA        :1;                                       /* Interrupt Test Register Bit 5 */
    byte INTC        :1;                                       /* Interrupt Test Register Bit 6 */
    byte INTE        :1;                                       /* Interrupt Test Register Bit 7 */
  } Bits;
} ITESTSTR;
extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016);
#define ITEST _ITEST.Byte
#define ITEST_INT0 _ITEST.Bits.INT0
#define ITEST_INT2 _ITEST.Bits.INT2
#define ITEST_INT4 _ITEST.Bits.INT4
#define ITEST_INT6 _ITEST.Bits.INT6
#define ITEST_INT8 _ITEST.Bits.INT8
#define ITEST_INTA _ITEST.Bits.INTA
#define ITEST_INTC _ITEST.Bits.INTC
#define ITEST_INTE _ITEST.Bits.INTE


/*** MTST1 - MTST1; 0x00000017 ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* MTST1 Bit 0 */
    byte BIT1        :1;                                       /* MTST1 Bit 1 */
    byte BIT2        :1;                                       /* MTST1 Bit 2 */
    byte BIT3        :1;                                       /* MTST1 Bit 3 */
    byte BIT4        :1;                                       /* MTST1 Bit 4 */
    byte BIT5        :1;                                       /* MTST1 Bit 5 */
    byte BIT6        :1;                                       /* MTST1 Bit 6 */
    byte BIT7        :1;                                       /* MTST1 Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} MTST1STR;
extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017);
#define MTST1 _MTST1.Byte
#define MTST1_BIT0 _MTST1.Bits.BIT0
#define MTST1_BIT1 _MTST1.Bits.BIT1
#define MTST1_BIT2 _MTST1.Bits.BIT2
#define MTST1_BIT3 _MTST1.Bits.BIT3
#define MTST1_BIT4 _MTST1.Bits.BIT4
#define MTST1_BIT5 _MTST1.Bits.BIT5
#define MTST1_BIT6 _MTST1.Bits.BIT6
#define MTST1_BIT7 _MTST1.Bits.BIT7
#define MTST1_BIT _MTST1.MergedBits.grpBIT


/*** PARTIDH - Part ID Register High; 0x0000001A ***/
typedef union {
  byte Byte;
  struct {
    byte ID15        :1;                                       /* Part ID Register Bit 15 */
    byte ID14        :1;                                       /* Part ID Register Bit 14 */
    byte ID13        :1;                                       /* Part ID Register Bit 13 */
    byte ID12        :1;                                       /* Part ID Register Bit 12 */
    byte ID11        :1;                                       /* Part ID Register Bit 11 */
    byte ID10        :1;                                       /* Part ID Register Bit 10 */
    byte ID9         :1;                                       /* Part ID Register Bit 9 */
    byte ID8         :1;                                       /* Part ID Register Bit 8 */
  } Bits;
} PARTIDHSTR;
extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A);
#define PARTIDH _PARTIDH.Byte
#define PARTIDH_ID15 _PARTIDH.Bits.ID15
#define PARTIDH_ID14 _PARTIDH.Bits.ID14
#define PARTIDH_ID13 _PARTIDH.Bits.ID13
#define PARTIDH_ID12 _PARTIDH.Bits.ID12
#define PARTIDH_ID11 _PARTIDH.Bits.ID11
#define PARTIDH_ID10 _PARTIDH.Bits.ID10
#define PARTIDH_ID9 _PARTIDH.Bits.ID9
#define PARTIDH_ID8 _PARTIDH.Bits.ID8


/*** PARTIDL - Part ID Register Low; 0x0000001B ***/
typedef union {
  byte Byte;
  struct {
    byte ID0         :1;                                       /* Part ID Register Bit 0 */
    byte ID1         :1;                                       /* Part ID Register Bit 1 */
    byte ID2         :1;                                       /* Part ID Register Bit 2 */
    byte ID3         :1;                                       /* Part ID Register Bit 3 */
    byte ID4         :1;                                       /* Part ID Register Bit 4 */
    byte ID5         :1;                                       /* Part ID Register Bit 5 */
    byte ID6         :1;                                       /* Part ID Register Bit 6 */
    byte ID7         :1;                                       /* Part ID Register Bit 7 */
  } Bits;
  struct {
    byte grpID   :8;
  } MergedBits;
} PARTIDLSTR;
extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B);
#define PARTIDL _PARTIDL.Byte
#define PARTIDL_ID0 _PARTIDL.Bits.ID0
#define PARTIDL_ID1 _PARTIDL.Bits.ID1
#define PARTIDL_ID2 _PARTIDL.Bits.ID2
#define PARTIDL_ID3 _PARTIDL.Bits.ID3
#define PARTIDL_ID4 _PARTIDL.Bits.ID4
#define PARTIDL_ID5 _PARTIDL.Bits.ID5
#define PARTIDL_ID6 _PARTIDL.Bits.ID6
#define PARTIDL_ID7 _PARTIDL.Bits.ID7
#define PARTIDL_ID _PARTIDL.MergedBits.grpID


/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/
typedef union {
  byte Byte;
  struct {
    byte ram_sw0     :1;                                       /* Allocated RAM Memory Space Bit 0 */
    byte ram_sw1     :1;                                       /* Allocated RAM Memory Space Bit 1 */
    byte ram_sw2     :1;                                       /* Allocated RAM Memory Space Bit 2 */
    byte             :1; 
    byte eep_sw0     :1;                                       /* Allocated EEPROM Memory Space Bit 0 */
    byte eep_sw1     :1;                                       /* Allocated EEPROM Memory Space Bit 1 */
    byte             :1; 
    byte reg_sw0     :1;                                       /* Allocated System Register Space */
  } Bits;
  struct {
    byte grpram_sw :3;
    byte         :1;
    byte grpeep_sw :2;
    byte         :1;
    byte grpreg_sw :1;
  } MergedBits;
} MEMSIZ0STR;
extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);
#define MEMSIZ0 _MEMSIZ0.Byte
#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0
#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1
#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2
#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0
#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1
#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0
#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw
#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw


/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/
typedef union {
  byte Byte;
  struct {
    byte pag_sw0     :1;                                       /* Allocated Off-Chip Memory Options Bit 0 */
    byte pag_sw1     :1;                                       /* Allocated Off-Chip Memory Options Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte rom_sw0     :1;                                       /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */
    byte rom_sw1     :1;                                       /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */
  } Bits;
  struct {
    byte grppag_sw :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grprom_sw :2;
  } MergedBits;
} MEMSIZ1STR;
extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);
#define MEMSIZ1 _MEMSIZ1.Byte
#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0
#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1
#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0
#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1
#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw
#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw


/*** INTCR - Interrupt Control Register; 0x0000001E ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte IRQEN       :1;                                       /* External IRQ Enable */
    byte IRQE        :1;                                       /* IRQ Select Edge Sensitive Only */
  } Bits;
} INTCRSTR;
extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);
#define INTCR _INTCR.Byte
#define INTCR_IRQEN _INTCR.Bits.IRQEN
#define INTCR_IRQE _INTCR.Bits.IRQE


/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte PSEL1       :1;                                       /* Highest Priority I Interrupt Bit 1 */
    byte PSEL2       :1;                                       /* Highest Priority I Interrupt Bit 2 */
    byte PSEL3       :1;                                       /* Highest Priority I Interrupt Bit 3 */
    byte PSEL4       :1;                                       /* Highest Priority I Interrupt Bit 4 */
    byte PSEL5       :1;                                       /* Highest Priority I Interrupt Bit 5 */
    byte PSEL6       :1;                                       /* Highest Priority I Interrupt Bit 6 */
    byte PSEL7       :1;                                       /* Highest Priority I Interrupt Bit 7 */
  } Bits;
  struct {
    byte         :1;
    byte grpPSEL_1 :7;
  } MergedBits;
} HPRIOSTR;
extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);
#define HPRIO _HPRIO.Byte
#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1
#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2
#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3
#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4
#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5
#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6
#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7
#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1
#define HPRIO_PSEL HPRIO_PSEL_1


/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BKTAG       :1;                                       /* Breakpoint on Tag */
    byte BKBDM       :1;                                       /* Breakpoint Background Debug Mode Enable */
    byte BKFULL      :1;                                       /* Full Breakpoint Mode Enable */
    byte BKEN        :1;                                       /* Breakpoint Enable */
  } Bits;
} BKPCT0STR;
extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028);
#define BKPCT0 _BKPCT0.Byte
#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG
#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM
#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL
#define BKPCT0_BKEN _BKPCT0.Bits.BKEN


/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/
typedef union {
  byte Byte;
  struct {
    byte BK1RW       :1;                                       /* R/W Compare Value 1 */
    byte BK1RWE      :1;                                       /* R/W Compare Enable 1 */
    byte BK0RW       :1;                                       /* R/W Compare Value 0 */
    byte BK0RWE      :1;                                       /* R/W Compare Enable 0 */
    byte BK1MBL      :1;                                       /* Breakpoint Mask Low Byte for Second Address */
    byte BK1MBH      :1;                                       /* Breakpoint Mask High Byte for Second Address */
    byte BK0MBL      :1;                                       /* Breakpoint Mask Low Byte for First Address */
    byte BK0MBH      :1;                                       /* Breakpoint Mask High Byte for First Address */
  } Bits;
} BKPCT1STR;
extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029);
#define BKPCT1 _BKPCT1.Byte
#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW
#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE
#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW
#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE
#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL
#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH
#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL
#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH


/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/
typedef union {
  byte Byte;
  struct {
    byte BK0V0       :1;                                       /* First Address Breakpoint Expansion Address Value Bit 0 */
    byte BK0V1       :1;                                       /* First Address Breakpoint Expansion Address Value Bit 1 */
    byte BK0V2       :1;                                       /* First Address Breakpoint Expansion Address Value Bit 2 */
    byte BK0V3       :1;                                       /* First Address Breakpoint Expansion Address Value Bit 3 */
    byte BK0V4       :1;                                       /* First Address Breakpoint Expansion Address Value Bit 4 */
    byte BK0V5       :1;                                       /* First Address Breakpoint Expansion Address Value Bit 5 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpBK0V :6;
    byte         :1;
    byte         :1;
  } MergedBits;
} BKP0XSTR;
extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A);
#define BKP0X _BKP0X.Byte
#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0
#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1
#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2
#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3
#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4
#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5
#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V


/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/
typedef union {
  byte Byte;
  struct {
    byte BIT8        :1;                                       /* First Address Breakpoint Register Bit 8 */
    byte BIT9        :1;                                       /* First Address Breakpoint Register Bit 9 */
    byte BIT10       :1;                                       /* First Address Breakpoint Register Bit 10 */
    byte BIT11       :1;                                       /* First Address Breakpoint Register Bit 11 */
    byte BIT12       :1;                                       /* First Address Breakpoint Register Bit 12 */
    byte BIT13       :1;                                       /* First Address Breakpoint Register Bit 13 */
    byte BIT14       :1;                                       /* First Address Breakpoint Register Bit 14 */
    byte BIT15       :1;                                       /* First Address Breakpoint Register Bit 15 */
  } Bits;
  struct {
    byte grpBIT_8 :8;
  } MergedBits;
} BKP0HSTR;
extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B);
#define BKP0H _BKP0H.Byte
#define BKP0H_BIT8 _BKP0H.Bits.BIT8
#define BKP0H_BIT9 _BKP0H.Bits.BIT9
#define BKP0H_BIT10 _BKP0H.Bits.BIT10
#define BKP0H_BIT11 _BKP0H.Bits.BIT11
#define BKP0H_BIT12 _BKP0H.Bits.BIT12
#define BKP0H_BIT13 _BKP0H.Bits.BIT13
#define BKP0H_BIT14 _BKP0H.Bits.BIT14
#define BKP0H_BIT15 _BKP0H.Bits.BIT15
#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8
#define BKP0H_BIT BKP0H_BIT_8


/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* First Address Breakpoint Register Bit 0 */
    byte BIT1        :1;                                       /* First Address Breakpoint Register Bit 1 */
    byte BIT2        :1;                                       /* First Address Breakpoint Register Bit 2 */
    byte BIT3        :1;                                       /* First Address Breakpoint Register Bit 3 */
    byte BIT4        :1;                                       /* First Address Breakpoint Register Bit 4 */
    byte BIT5        :1;                                       /* First Address Breakpoint Register Bit 5 */
    byte BIT6        :1;                                       /* First Address Breakpoint Register Bit 6 */
    byte BIT7        :1;                                       /* First Address Breakpoint Register Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} BKP0LSTR;
extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C);
#define BKP0L _BKP0L.Byte
#define BKP0L_BIT0 _BKP0L.Bits.BIT0
#define BKP0L_BIT1 _BKP0L.Bits.BIT1
#define BKP0L_BIT2 _BKP0L.Bits.BIT2
#define BKP0L_BIT3 _BKP0L.Bits.BIT3
#define BKP0L_BIT4 _BKP0L.Bits.BIT4
#define BKP0L_BIT5 _BKP0L.Bits.BIT5
#define BKP0L_BIT6 _BKP0L.Bits.BIT6
#define BKP0L_BIT7 _BKP0L.Bits.BIT7
#define BKP0L_BIT _BKP0L.MergedBits.grpBIT


/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/
typedef union {
  byte Byte;
  struct {
    byte BK1V0       :1;                                       /* Second Address Breakpoint Expansion Address Value Bit 0 */
    byte BK1V1       :1;                                       /* Second Address Breakpoint Expansion Address Value Bit 1 */
    byte BK1V2       :1;                                       /* Second Address Breakpoint Expansion Address Value Bit 2 */
    byte BK1V3       :1;                                       /* Second Address Breakpoint Expansion Address Value Bit 3 */
    byte BK1V4       :1;                                       /* Second Address Breakpoint Expansion Address Value Bit 4 */
    byte BK1V5       :1;                                       /* Second Address Breakpoint Expansion Address Value Bit 5 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpBK1V :6;
    byte         :1;
    byte         :1;
  } MergedBits;
} BKP1XSTR;
extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D);
#define BKP1X _BKP1X.Byte
#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0
#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1
#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2
#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3
#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4
#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5
#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V


/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/
typedef union {
  byte Byte;
  struct {
    byte BIT8        :1;                                       /* Data (Second Address) Breakpoint Register Bit 8 */
    byte BIT9        :1;                                       /* Data (Second Address) Breakpoint Register Bit 9 */
    byte BIT10       :1;                                       /* Data (Second Address) Breakpoint Register Bit 10 */
    byte BIT11       :1;                                       /* Data (Second Address) Breakpoint Register Bit 11 */
    byte BIT12       :1;                                       /* Data (Second Address) Breakpoint Register Bit 12 */
    byte BIT13       :1;                                       /* Data (Second Address) Breakpoint Register Bit 13 */
    byte BIT14       :1;                                       /* Data (Second Address) Breakpoint Register Bit 14 */
    byte BIT15       :1;                                       /* Data (Second Address) Breakpoint Register Bit 15 */
  } Bits;
  struct {
    byte grpBIT_8 :8;
  } MergedBits;
} BKP1HSTR;
extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E);
#define BKP1H _BKP1H.Byte
#define BKP1H_BIT8 _BKP1H.Bits.BIT8
#define BKP1H_BIT9 _BKP1H.Bits.BIT9
#define BKP1H_BIT10 _BKP1H.Bits.BIT10
#define BKP1H_BIT11 _BKP1H.Bits.BIT11
#define BKP1H_BIT12 _BKP1H.Bits.BIT12
#define BKP1H_BIT13 _BKP1H.Bits.BIT13
#define BKP1H_BIT14 _BKP1H.Bits.BIT14
#define BKP1H_BIT15 _BKP1H.Bits.BIT15
#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8
#define BKP1H_BIT BKP1H_BIT_8


/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Data (Second Address) Breakpoint Register Bit 0 */
    byte BIT1        :1;                                       /* Data (Second Address) Breakpoint Register Bit 1 */
    byte BIT2        :1;                                       /* Data (Second Address) Breakpoint Register Bit 2 */
    byte BIT3        :1;                                       /* Data (Second Address) Breakpoint Register Bit 3 */
    byte BIT4        :1;                                       /* Data (Second Address) Breakpoint Register Bit 4 */
    byte BIT5        :1;                                       /* Data (Second Address) Breakpoint Register Bit 5 */
    byte BIT6        :1;                                       /* Data (Second Address) Breakpoint Register Bit 6 */
    byte BIT7        :1;                                       /* Data (Second Address) Breakpoint Register Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} BKP1LSTR;
extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F);
#define BKP1L _BKP1L.Byte
#define BKP1L_BIT0 _BKP1L.Bits.BIT0
#define BKP1L_BIT1 _BKP1L.Bits.BIT1
#define BKP1L_BIT2 _BKP1L.Bits.BIT2
#define BKP1L_BIT3 _BKP1L.Bits.BIT3
#define BKP1L_BIT4 _BKP1L.Bits.BIT4
#define BKP1L_BIT5 _BKP1L.Bits.BIT5
#define BKP1L_BIT6 _BKP1L.Bits.BIT6
#define BKP1L_BIT7 _BKP1L.Bits.BIT7
#define BKP1L_BIT _BKP1L.MergedBits.grpBIT


/*** PPAGE - Page Index Register; 0x00000030 ***/
typedef union {
  byte Byte;
  struct {
    byte PIX0        :1;                                       /* Page Index Register Bit 0 */
    byte PIX1        :1;                                       /* Page Index Register Bit 1 */
    byte PIX2        :1;                                       /* Page Index Register Bit 2 */
    byte PIX3        :1;                                       /* Page Index Register Bit 3 */
    byte PIX4        :1;                                       /* Page Index Register Bit 4 */
    byte PIX5        :1;                                       /* Page Index Register Bit 5 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpPIX  :6;
    byte         :1;
    byte         :1;
  } MergedBits;
} PPAGESTR;
extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030);
#define PPAGE _PPAGE.Byte
#define PPAGE_PIX0 _PPAGE.Bits.PIX0
#define PPAGE_PIX1 _PPAGE.Bits.PIX1
#define PPAGE_PIX2 _PPAGE.Bits.PIX2
#define PPAGE_PIX3 _PPAGE.Bits.PIX3
#define PPAGE_PIX4 _PPAGE.Bits.PIX4
#define PPAGE_PIX5 _PPAGE.Bits.PIX5
#define PPAGE_PIX _PPAGE.MergedBits.grpPIX


/*** PORTK - Port K Data Register; 0x00000032 ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Port K Bit 0 */
    byte BIT1        :1;                                       /* Port K Bit 1 */
    byte BIT2        :1;                                       /* Port K Bit 2 */
    byte BIT3        :1;                                       /* Port K Bit 3 */
    byte BIT4        :1;                                       /* Port K Bit 4 */
    byte BIT5        :1;                                       /* Port K Bit 5 */
    byte             :1; 
    byte BIT7        :1;                                       /* Port K Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :6;
    byte         :1;
    byte grpBIT_7 :1;
  } MergedBits;
} PORTKSTR;
extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032);
#define PORTK _PORTK.Byte
#define PORTK_BIT0 _PORTK.Bits.BIT0
#define PORTK_BIT1 _PORTK.Bits.BIT1
#define PORTK_BIT2 _PORTK.Bits.BIT2
#define PORTK_BIT3 _PORTK.Bits.BIT3
#define PORTK_BIT4 _PORTK.Bits.BIT4
#define PORTK_BIT5 _PORTK.Bits.BIT5
#define PORTK_BIT7 _PORTK.Bits.BIT7
#define PORTK_BIT _PORTK.MergedBits.grpBIT


/*** DDRK - Port K Data Direction Register; 0x00000033 ***/
typedef union {
  byte Byte;
  struct {
    byte DDK0        :1;                                       /* Port K Data Direction Bit 0 */
    byte DDK1        :1;                                       /* Port K Data Direction Bit 1 */
    byte DDK2        :1;                                       /* Port K Data Direction Bit 2 */
    byte DDK3        :1;                                       /* Port K Data Direction Bit 3 */
    byte DDK4        :1;                                       /* Port K Data Direction Bit 4 */
    byte DDK5        :1;                                       /* Port K Data Direction Bit 5 */
    byte             :1; 
    byte DDK7        :1;                                       /* Port K Data Direction Bit 7 */
  } Bits;
  struct {
    byte grpDDK  :6;
    byte         :1;
    byte grpDDK_7 :1;
  } MergedBits;
} DDRKSTR;
extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033);
#define DDRK _DDRK.Byte
#define DDRK_DDK0 _DDRK.Bits.DDK0
#define DDRK_DDK1 _DDRK.Bits.DDK1
#define DDRK_DDK2 _DDRK.Bits.DDK2
#define DDRK_DDK3 _DDRK.Bits.DDK3
#define DDRK_DDK4 _DDRK.Bits.DDK4
#define DDRK_DDK5 _DDRK.Bits.DDK5
#define DDRK_DDK7 _DDRK.Bits.DDK7
#define DDRK_DDK _DDRK.MergedBits.grpDDK


/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/
typedef union {
  byte Byte;
  struct {
    byte SYN0        :1;                                       /* CRG Synthesizer Bit 0 */
    byte SYN1        :1;                                       /* CRG Synthesizer Bit 1 */
    byte SYN2        :1;                                       /* CRG Synthesizer Bit 2 */
    byte SYN3        :1;                                       /* CRG Synthesizer Bit 3 */
    byte SYN4        :1;                                       /* CRG Synthesizer Bit 4 */
    byte SYN5        :1;                                       /* CRG Synthesizer Bit 5 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpSYN  :6;
    byte         :1;
    byte         :1;
  } MergedBits;
} SYNRSTR;
extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034);
#define SYNR _SYNR.Byte
#define SYNR_SYN0 _SYNR.Bits.SYN0
#define SYNR_SYN1 _SYNR.Bits.SYN1
#define SYNR_SYN2 _SYNR.Bits.SYN2
#define SYNR_SYN3 _SYNR.Bits.SYN3
#define SYNR_SYN4 _SYNR.Bits.SYN4
#define SYNR_SYN5 _SYNR.Bits.SYN5
#define SYNR_SYN _SYNR.MergedBits.grpSYN


/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/
typedef union {
  byte Byte;
  struct {
    byte REFDV0      :1;                                       /* CRG Reference Divider Bit 0 */
    byte REFDV1      :1;                                       /* CRG Reference Divider Bit 1 */
    byte REFDV2      :1;                                       /* CRG Reference Divider Bit 2 */
    byte REFDV3      :1;                                       /* CRG Reference Divider Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpREFDV :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} REFDVSTR;
extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035);
#define REFDV _REFDV.Byte
#define REFDV_REFDV0 _REFDV.Bits.REFDV0
#define REFDV_REFDV1 _REFDV.Bits.REFDV1
#define REFDV_REFDV2 _REFDV.Bits.REFDV2
#define REFDV_REFDV3 _REFDV.Bits.REFDV3
#define REFDV_REFDV _REFDV.MergedBits.grpREFDV


/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/
typedef union {
  byte Byte;
  struct {
    byte TOUT0       :1;                                       /* CRG Test Flags Bit 0 */
    byte TOUT1       :1;                                       /* CRG Test Flags Bit 1 */
    byte TOUT2       :1;                                       /* CRG Test Flags Bit 2 */
    byte TOUT3       :1;                                       /* CRG Test Flags Bit 3 */
    byte TOUT4       :1;                                       /* CRG Test Flags Bit 4 */
    byte TOUT5       :1;                                       /* CRG Test Flags Bit 5 */
    byte TOUT6       :1;                                       /* CRG Test Flags Bit 6 */
    byte TOUT7       :1;                                       /* CRG Test Flags Bit 7 */
  } Bits;
  struct {
    byte grpTOUT :8;
  } MergedBits;
} CTFLGSTR;
extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036);
#define CTFLG _CTFLG.Byte
#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0
#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1
#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2
#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3
#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4
#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5
#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6
#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7
#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT


/*** CRGFLG - CRG Flags Register; 0x00000037 ***/
typedef union {
  byte Byte;
  struct {
    byte SCM         :1;                                       /* Self-clock mode Status */
    byte SCMIF       :1;                                       /* Self-clock mode Interrupt Flag */
    byte TRACK       :1;                                       /* Track Status */
    byte LOCK        :1;                                       /* Lock Status */
    byte LOCKIF      :1;                                       /* PLL Lock Interrupt Flag */
    byte             :1; 
    byte PORF        :1;                                       /* Power on Reset Flag */
    byte RTIF        :1;                                       /* Real Time Interrupt Flag */
  } Bits;
} CRGFLGSTR;
extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037);
#define CRGFLG _CRGFLG.Byte
#define CRGFLG_SCM _CRGFLG.Bits.SCM
#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF
#define CRGFLG_TRACK _CRGFLG.Bits.TRACK
#define CRGFLG_LOCK _CRGFLG.Bits.LOCK
#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF
#define CRGFLG_PORF _CRGFLG.Bits.PORF
#define CRGFLG_RTIF _CRGFLG.Bits.RTIF


/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte SCMIE       :1;                                       /* Self-clock mode Interrupt Enable */
    byte             :1; 
    byte             :1; 
    byte LOCKIE      :1;                                       /* Lock Interrupt Enable */
    byte             :1; 
    byte             :1; 
    byte RTIE        :1;                                       /* Real Time Interrupt Enable */
  } Bits;
} CRGINTSTR;
extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038);
#define CRGINT _CRGINT.Byte
#define CRGINT_SCMIE _CRGINT.Bits.SCMIE
#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE
#define CRGINT_RTIE _CRGINT.Bits.RTIE


/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/
typedef union {
  byte Byte;
  struct {
    byte COPWAI      :1;                                       /* COP stops in WAIT mode */
    byte RTIWAI      :1;                                       /* RTI stops in WAIT mode */
    byte CWAI        :1;                                       /* CLK24 and CLK23 stop in WAIT mode */
    byte PLLWAI      :1;                                       /* PLL stops in WAIT mode */
    byte ROAWAI      :1;                                       /* Reduced Oscillator Amplitude in WAIT mode */
    byte SYSWAI      :1;                                       /* System clocks stop in WAIT mode */
    byte PSTP        :1;                                       /* Pseudo Stop */
    byte PLLSEL      :1;                                       /* PLL selected for system clock */
  } Bits;
} CLKSELSTR;
extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039);
#define CLKSEL _CLKSEL.Byte
#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI
#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI
#define CLKSEL_CWAI _CLKSEL.Bits.CWAI
#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI
#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI
#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI
#define CLKSEL_PSTP _CLKSEL.Bits.PSTP
#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL


/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/
typedef union {
  byte Byte;
  struct {
    byte SCME        :1;                                       /* Self-clock mode enable */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte ACQ         :1;                                       /* Acquisition */
    byte AUTO        :1;                                       /* Automatic Bandwidth Control */
    byte PLLON       :1;                                       /* Phase Lock Loop On */
    byte CME         :1;                                       /* Crystal Monitor Enable */
  } Bits;
} PLLCTLSTR;
extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A);
#define PLLCTL _PLLCTL.Byte
#define PLLCTL_SCME _PLLCTL.Bits.SCME
#define PLLCTL_ACQ _PLLCTL.Bits.ACQ
#define PLLCTL_AUTO _PLLCTL.Bits.AUTO
#define PLLCTL_PLLON _PLLCTL.Bits.PLLON
#define PLLCTL_CME _PLLCTL.Bits.CME


/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/
typedef union {
  byte Byte;
  struct {
    byte RTR0        :1;                                       /* Real Time Interrupt Modulus Counter Select */
    byte RTR1        :1;                                       /* Real Time Interrupt Modulus Counter Select */
    byte RTR2        :1;                                       /* Real Time Interrupt Modulus Counter Select */
    byte RTR3        :1;                                       /* Real Time Interrupt Modulus Counter Select */
    byte RTR4        :1;                                       /* Real Time Interrupt Prescale Rate Select */
    byte RTR5        :1;                                       /* Real Time Interrupt Prescale Rate Select */
    byte RTR6        :1;                                       /* Real Time Interrupt Prescale Rate Select */
    byte             :1; 
  } Bits;
  struct {
    byte grpRTR  :7;
    byte         :1;
  } MergedBits;
} RTICTLSTR;
extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B);
#define RTICTL _RTICTL.Byte
#define RTICTL_RTR0 _RTICTL.Bits.RTR0
#define RTICTL_RTR1 _RTICTL.Bits.RTR1
#define RTICTL_RTR2 _RTICTL.Bits.RTR2
#define RTICTL_RTR3 _RTICTL.Bits.RTR3
#define RTICTL_RTR4 _RTICTL.Bits.RTR4
#define RTICTL_RTR5 _RTICTL.Bits.RTR5
#define RTICTL_RTR6 _RTICTL.Bits.RTR6
#define RTICTL_RTR _RTICTL.MergedBits.grpRTR


/*** COPCTL - CRG COP Control Register; 0x0000003C ***/
typedef union {
  byte Byte;
  struct {
    byte CR0         :1;                                       /* COP Watchdog Timer Rate select Bit 0 */
    byte CR1         :1;                                       /* COP Watchdog Timer Rate select Bit 1 */
    byte CR2         :1;                                       /* COP Watchdog Timer Rate select Bit 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte RSBCK       :1;                                       /* COP and RTI stop in Active BDM mode Bit */
    byte WCOP        :1;                                       /* Window COP mode */
  } Bits;
  struct {
    byte grpCR   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} COPCTLSTR;
extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C);
#define COPCTL _COPCTL.Byte
#define COPCTL_CR0 _COPCTL.Bits.CR0
#define COPCTL_CR1 _COPCTL.Bits.CR1
#define COPCTL_CR2 _COPCTL.Bits.CR2
#define COPCTL_RSBCK _COPCTL.Bits.RSBCK
#define COPCTL_WCOP _COPCTL.Bits.WCOP
#define COPCTL_CR _COPCTL.MergedBits.grpCR


/*** FORBYP - Crg force and bypass test register; 0x0000003D ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Bit 0 */
    byte BIT1        :1;                                       /* Bit 1 */
    byte BIT2        :1;                                       /* Bit 2 */
    byte BIT3        :1;                                       /* Bit 3 */
    byte BIT4        :1;                                       /* Bit 4 */
    byte BIT5        :1;                                       /* Bit 5 */
    byte BIT6        :1;                                       /* Bit 6 */
    byte BIT7        :1;                                       /* Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} FORBYPSTR;
extern volatile FORBYPSTR _FORBYP @(REG_BASE + 0x0000003D);
#define FORBYP _FORBYP.Byte
#define FORBYP_BIT0 _FORBYP.Bits.BIT0
#define FORBYP_BIT1 _FORBYP.Bits.BIT1
#define FORBYP_BIT2 _FORBYP.Bits.BIT2
#define FORBYP_BIT3 _FORBYP.Bits.BIT3
#define FORBYP_BIT4 _FORBYP.Bits.BIT4
#define FORBYP_BIT5 _FORBYP.Bits.BIT5
#define FORBYP_BIT6 _FORBYP.Bits.BIT6
#define FORBYP_BIT7 _FORBYP.Bits.BIT7
#define FORBYP_BIT _FORBYP.MergedBits.grpBIT


/*** CTCTL - CRG Test Control Register; 0x0000003E ***/
typedef union {
  byte Byte;
  struct {
    byte TCTL0       :1;                                       /* CRG Test Control Bit 0 */
    byte TCTL1       :1;                                       /* CRG Test Control Bit 1 */
    byte TCTL2       :1;                                       /* CRG Test Control Bit 2 */
    byte TCTL3       :1;                                       /* CRG Test Control Bit 3 */
    byte TCTL4       :1;                                       /* CRG Test Control Bit 4 */
    byte TCTL5       :1;                                       /* CRG Test Control Bit 5 */
    byte TCTL6       :1;                                       /* CRG Test Control Bit 6 */
    byte TCTL7       :1;                                       /* CRG Test Control Bit 7 */
  } Bits;
  struct {
    byte grpTCTL :8;
  } MergedBits;
} CTCTLSTR;
extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E);
#define CTCTL _CTCTL.Byte
#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0
#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1
#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2
#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3
#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4
#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5
#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6
#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7
#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL


/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* CRG COP Timer Arm/Reset Bit 0 */
    byte BIT1        :1;                                       /* CRG COP Timer Arm/Reset Bit 1 */
    byte BIT2        :1;                                       /* CRG COP Timer Arm/Reset Bit 2 */
    byte BIT3        :1;                                       /* CRG COP Timer Arm/Reset Bit 3 */
    byte BIT4        :1;                                       /* CRG COP Timer Arm/Reset Bit 4 */
    byte BIT5        :1;                                       /* CRG COP Timer Arm/Reset Bit 5 */
    byte BIT6        :1;                                       /* CRG COP Timer Arm/Reset Bit 6 */
    byte BIT7        :1;                                       /* CRG COP Timer Arm/Reset Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} ARMCOPSTR;
extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F);
#define ARMCOP _ARMCOP.Byte
#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0
#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1
#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2
#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3
#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4
#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5
#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6
#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7
#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT


/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/
typedef union {
  byte Byte;
  struct {
    byte IOS0        :1;                                       /* Input Capture or Output Compare Channel Configuration Bit 0 */
    byte IOS1        :1;                                       /* Input Capture or Output Compare Channel Configuration Bit 1 */
    byte IOS2        :1;                                       /* Input Capture or Output Compare Channel Configuration Bit 2 */
    byte IOS3        :1;                                       /* Input Capture or Output Compare Channel Configuration Bit 3 */
    byte IOS4        :1;                                       /* Input Capture or Output Compare Channel Configuration Bit 4 */
    byte IOS5        :1;                                       /* Input Capture or Output Compare Channel Configuration Bit 5 */
    byte IOS6        :1;                                       /* Input Capture or Output Compare Channel Configuration Bit 6 */
    byte IOS7        :1;                                       /* Input Capture or Output Compare Channel Configuration Bit 7 */
  } Bits;
  struct {
    byte grpIOS  :8;
  } MergedBits;
} TIOSSTR;
extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040);
#define TIOS _TIOS.Byte
#define TIOS_IOS0 _TIOS.Bits.IOS0
#define TIOS_IOS1 _TIOS.Bits.IOS1
#define TIOS_IOS2 _TIOS.Bits.IOS2
#define TIOS_IOS3 _TIOS.Bits.IOS3
#define TIOS_IOS4 _TIOS.Bits.IOS4
#define TIOS_IOS5 _TIOS.Bits.IOS5
#define TIOS_IOS6 _TIOS.Bits.IOS6
#define TIOS_IOS7 _TIOS.Bits.IOS7
#define TIOS_IOS _TIOS.MergedBits.grpIOS


/*** CFORC - Timer Compare Force Register; 0x00000041 ***/
typedef union {
  byte Byte;
  struct {
    byte FOC0        :1;                                       /* Force Output Compare Action for Channel 0 */
    byte FOC1        :1;                                       /* Force Output Compare Action for Channel 1 */
    byte FOC2        :1;                                       /* Force Output Compare Action for Channel 2 */
    byte FOC3        :1;                                       /* Force Output Compare Action for Channel 3 */
    byte FOC4        :1;                                       /* Force Output Compare Action for Channel 4 */
    byte FOC5        :1;                                       /* Force Output Compare Action for Channel 5 */
    byte FOC6        :1;                                       /* Force Output Compare Action for Channel 6 */
    byte FOC7        :1;                                       /* Force Output Compare Action for Channel 7 */
  } Bits;
  struct {
    byte grpFOC  :8;
  } MergedBits;
} CFORCSTR;
extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041);
#define CFORC _CFORC.Byte
#define CFORC_FOC0 _CFORC.Bits.FOC0
#define CFORC_FOC1 _CFORC.Bits.FOC1
#define CFORC_FOC2 _CFORC.Bits.FOC2
#define CFORC_FOC3 _CFORC.Bits.FOC3
#define CFORC_FOC4 _CFORC.Bits.FOC4
#define CFORC_FOC5 _CFORC.Bits.FOC5
#define CFORC_FOC6 _CFORC.Bits.FOC6
#define CFORC_FOC7 _CFORC.Bits.FOC7
#define CFORC_FOC _CFORC.MergedBits.grpFOC


/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/
typedef union {
  byte Byte;
  struct {
    byte OC7M0       :1;                                       /* Output Compare 7 Mask Bit 0 */
    byte OC7M1       :1;                                       /* Output Compare 7 Mask Bit 1 */
    byte OC7M2       :1;                                       /* Output Compare 7 Mask Bit 2 */
    byte OC7M3       :1;                                       /* Output Compare 7 Mask Bit 3 */
    byte OC7M4       :1;                                       /* Output Compare 7 Mask Bit 4 */
    byte OC7M5       :1;                                       /* Output Compare 7 Mask Bit 5 */
    byte OC7M6       :1;                                       /* Output Compare 7 Mask Bit 6 */
    byte OC7M7       :1;                                       /* Output Compare 7 Mask Bit 7 */
  } Bits;
  struct {
    byte grpOC7M :8;
  } MergedBits;
} OC7MSTR;
extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042);
#define OC7M _OC7M.Byte
#define OC7M_OC7M0 _OC7M.Bits.OC7M0
#define OC7M_OC7M1 _OC7M.Bits.OC7M1
#define OC7M_OC7M2 _OC7M.Bits.OC7M2
#define OC7M_OC7M3 _OC7M.Bits.OC7M3
#define OC7M_OC7M4 _OC7M.Bits.OC7M4
#define OC7M_OC7M5 _OC7M.Bits.OC7M5
#define OC7M_OC7M6 _OC7M.Bits.OC7M6
#define OC7M_OC7M7 _OC7M.Bits.OC7M7
#define OC7M_OC7M _OC7M.MergedBits.grpOC7M


/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/
typedef union {
  byte Byte;
  struct {
    byte grpOC7D :8;
  } MergedBits;
} OC7DSTR;
extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043);
#define OC7D _OC7D.Byte
#define OC7D_OC7D _OC7D.MergedBits.grpOC7D


/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte TFFCA       :1;                                       /* Timer Fast Flag Clear All */
    byte TSFRZ       :1;                                       /* Timer and Modulus Counter Stop While in Freeze Mode */
    byte TSWAI       :1;                                       /* Timer Module Stops While in Wait */
    byte TEN         :1;                                       /* Timer Enable */
  } Bits;
} TSCR1STR;
extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046);
#define TSCR1 _TSCR1.Byte
#define TSCR1_TFFCA _TSCR1.Bits.TFFCA
#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ
#define TSCR1_TSWAI _TSCR1.Bits.TSWAI
#define TSCR1_TEN _TSCR1.Bits.TEN


/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/
typedef union {
  byte Byte;
  struct {
    byte TOV0        :1;                                       /* Toggle On Overflow Bit 0 */
    byte TOV1        :1;                                       /* Toggle On Overflow Bit 1 */
    byte TOV2        :1;                                       /* Toggle On Overflow Bit 2 */
    byte TOV3        :1;                                       /* Toggle On Overflow Bit 3 */
    byte TOV4        :1;                                       /* Toggle On Overflow Bit 4 */
    byte TOV5        :1;                                       /* Toggle On Overflow Bit 5 */
    byte TOV6        :1;                                       /* Toggle On Overflow Bit 6 */
    byte TOV7        :1;                                       /* Toggle On Overflow Bit 7 */
  } Bits;
  struct {
    byte grpTOV  :8;
  } MergedBits;
} TTOVSTR;
extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047);
#define TTOV _TTOV.Byte
#define TTOV_TOV0 _TTOV.Bits.TOV0
#define TTOV_TOV1 _TTOV.Bits.TOV1
#define TTOV_TOV2 _TTOV.Bits.TOV2
#define TTOV_TOV3 _TTOV.Bits.TOV3
#define TTOV_TOV4 _TTOV.Bits.TOV4
#define TTOV_TOV5 _TTOV.Bits.TOV5
#define TTOV_TOV6 _TTOV.Bits.TOV6
#define TTOV_TOV7 _TTOV.Bits.TOV7
#define TTOV_TOV _TTOV.MergedBits.grpTOV


/*** TCTL1 - Timer Control Registers 1; 0x00000048 ***/
typedef union {
  byte Byte;
  struct {
    byte OL4         :1;                                       /* Output Level Bit 4 */
    byte OM4         :1;                                       /* Output Mode Bit 4 */
    byte OL5         :1;                                       /* Output Level Bit 5 */
    byte OM5         :1;                                       /* Output Mode Bit 5 */
    byte OL6         :1;                                       /* Output Level Bit 6 */
    byte OM6         :1;                                       /* Output Mode Bit 6 */
    byte OL7         :1;                                       /* Output Level Bit 7 */
    byte OM7         :1;                                       /* Output Mode Bit 7 */
  } Bits;
} TCTL1STR;
extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048);
#define TCTL1 _TCTL1.Byte
#define TCTL1_OL4 _TCTL1.Bits.OL4
#define TCTL1_OM4 _TCTL1.Bits.OM4
#define TCTL1_OL5 _TCTL1.Bits.OL5
#define TCTL1_OM5 _TCTL1.Bits.OM5
#define TCTL1_OL6 _TCTL1.Bits.OL6
#define TCTL1_OM6 _TCTL1.Bits.OM6
#define TCTL1_OL7 _TCTL1.Bits.OL7
#define TCTL1_OM7 _TCTL1.Bits.OM7


/*** TCTL2 - Timer Control Registers 2; 0x00000049 ***/
typedef union {
  byte Byte;
  struct {
    byte OL0         :1;                                       /* Output Level Bit 0 */
    byte OM0         :1;                                       /* Output Mode Bit 0 */
    byte OL1         :1;                                       /* Output Level Bit 1 */
    byte OM1         :1;                                       /* Output Mode Bit 1 */
    byte OL2         :1;                                       /* Output Level Bit 2 */
    byte OM2         :1;                                       /* Output Mode Bit 2 */
    byte OL3         :1;                                       /* Output Level Bit 3 */
    byte OM3         :1;                                       /* Output Mode Bit 3 */
  } Bits;
} TCTL2STR;
extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049);
#define TCTL2 _TCTL2.Byte
#define TCTL2_OL0 _TCTL2.Bits.OL0
#define TCTL2_OM0 _TCTL2.Bits.OM0
#define TCTL2_OL1 _TCTL2.Bits.OL1
#define TCTL2_OM1 _TCTL2.Bits.OM1
#define TCTL2_OL2 _TCTL2.Bits.OL2
#define TCTL2_OM2 _TCTL2.Bits.OM2
#define TCTL2_OL3 _TCTL2.Bits.OL3
#define TCTL2_OM3 _TCTL2.Bits.OM3


/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/
typedef union {
  byte Byte;
  struct {
    byte EDG4A       :1;                                       /* Input Capture Edge Control 4A */
    byte EDG4B       :1;                                       /* Input Capture Edge Control 4B */
    byte EDG5A       :1;                                       /* Input Capture Edge Control 5A */
    byte EDG5B       :1;                                       /* Input Capture Edge Control 5B */
    byte EDG6A       :1;                                       /* Input Capture Edge Control 6A */
    byte EDG6B       :1;                                       /* Input Capture Edge Control 6B */
    byte EDG7A       :1;                                       /* Input Capture Edge Control 7A */
    byte EDG7B       :1;                                       /* Input Capture Edge Control 7B */
  } Bits;
} TCTL3STR;
extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A);
#define TCTL3 _TCTL3.Byte
#define TCTL3_EDG4A _TCTL3.Bits.EDG4A
#define TCTL3_EDG4B _TCTL3.Bits.EDG4B
#define TCTL3_EDG5A _TCTL3.Bits.EDG5A
#define TCTL3_EDG5B _TCTL3.Bits.EDG5B
#define TCTL3_EDG6A _TCTL3.Bits.EDG6A
#define TCTL3_EDG6B _TCTL3.Bits.EDG6B
#define TCTL3_EDG7A _TCTL3.Bits.EDG7A
#define TCTL3_EDG7B _TCTL3.Bits.EDG7B


/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/
typedef union {
  byte Byte;
  struct {
    byte EDG0A       :1;                                       /* Input Capture Edge Control 0A */
    byte EDG0B       :1;                                       /* Input Capture Edge Control 0B */
    byte EDG1A       :1;                                       /* Input Capture Edge Control 1A */
    byte EDG1B       :1;                                       /* Input Capture Edge Control 1B */
    byte EDG2A       :1;                                       /* Input Capture Edge Control 2A */
    byte EDG2B       :1;                                       /* Input Capture Edge Control 2B */
    byte EDG3A       :1;                                       /* Input Capture Edge Control 3A */
    byte EDG3B       :1;                                       /* Input Capture Edge Control 3B */
  } Bits;
} TCTL4STR;
extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B);
#define TCTL4 _TCTL4.Byte
#define TCTL4_EDG0A _TCTL4.Bits.EDG0A
#define TCTL4_EDG0B _TCTL4.Bits.EDG0B
#define TCTL4_EDG1A _TCTL4.Bits.EDG1A
#define TCTL4_EDG1B _TCTL4.Bits.EDG1B
#define TCTL4_EDG2A _TCTL4.Bits.EDG2A
#define TCTL4_EDG2B _TCTL4.Bits.EDG2B
#define TCTL4_EDG3A _TCTL4.Bits.EDG3A
#define TCTL4_EDG3B _TCTL4.Bits.EDG3B


/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/
typedef union {
  byte Byte;
  struct {
    byte C0I         :1;                                       /* Input Capture/Output Compare Interrupt Enable Bit 0 */
    byte C1I         :1;                                       /* Input Capture/Output Compare Interrupt Enable Bit 1 */
    byte C2I         :1;                                       /* Input Capture/Output Compare Interrupt Enable Bit 2 */
    byte C3I         :1;                                       /* Input Capture/Output Compare Interrupt Enable Bit 3 */
    byte C4I         :1;                                       /* Input Capture/Output Compare Interrupt Enable Bit 4 */
    byte C5I         :1;                                       /* Input Capture/Output Compare Interrupt Enable Bit 5 */
    byte C6I         :1;                                       /* Input Capture/Output Compare Interrupt Enable Bit 6 */
    byte C7I         :1;                                       /* Input Capture/Output Compare Interrupt Enable Bit 7 */
  } Bits;
} TIESTR;
extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C);
#define TIE _TIE.Byte
#define TIE_C0I _TIE.Bits.C0I
#define TIE_C1I _TIE.Bits.C1I
#define TIE_C2I _TIE.Bits.C2I
#define TIE_C3I _TIE.Bits.C3I
#define TIE_C4I _TIE.Bits.C4I
#define TIE_C5I _TIE.Bits.C5I
#define TIE_C6I _TIE.Bits.C6I
#define TIE_C7I _TIE.Bits.C7I


/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/
typedef union {
  byte Byte;
  struct {
    byte PR0         :1;                                       /* Timer Prescaler Select Bit 0 */
    byte PR1         :1;                                       /* Timer Prescaler Select Bit 1 */
    byte PR2         :1;                                       /* Timer Prescaler Select Bit 2 */
    byte TCRE        :1;                                       /* Timer Counter Reset Enable */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte TOI         :1;                                       /* Timer Overflow Interrupt Enable */
  } Bits;
  struct {
    byte grpPR   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} TSCR2STR;
extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D);
#define TSCR2 _TSCR2.Byte
#define TSCR2_PR0 _TSCR2.Bits.PR0
#define TSCR2_PR1 _TSCR2.Bits.PR1
#define TSCR2_PR2 _TSCR2.Bits.PR2
#define TSCR2_TCRE _TSCR2.Bits.TCRE
#define TSCR2_TOI _TSCR2.Bits.TOI
#define TSCR2_PR _TSCR2.MergedBits.grpPR


/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/
typedef union {
  byte Byte;
  struct {
    byte C0F         :1;                                       /* Input Capture/Output Compare Channel Flag 0 */
    byte C1F         :1;                                       /* Input Capture/Output Compare Channel Flag 1 */
    byte C2F         :1;                                       /* Input Capture/Output Compare Channel Flag 2 */
    byte C3F         :1;                                       /* Input Capture/Output Compare Channel Flag 3 */
    byte C4F         :1;                                       /* Input Capture/Output Compare Channel Flag 4 */
    byte C5F         :1;                                       /* Input Capture/Output Compare Channel Flag 5 */
    byte C6F         :1;                                       /* Input Capture/Output Compare Channel Flag 6 */
    byte C7F         :1;                                       /* Input Capture/Output Compare Channel Flag 7 */
  } Bits;
} TFLG1STR;
extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E);
#define TFLG1 _TFLG1.Byte
#define TFLG1_C0F _TFLG1.Bits.C0F
#define TFLG1_C1F _TFLG1.Bits.C1F
#define TFLG1_C2F _TFLG1.Bits.C2F
#define TFLG1_C3F _TFLG1.Bits.C3F
#define TFLG1_C4F _TFLG1.Bits.C4F
#define TFLG1_C5F _TFLG1.Bits.C5F
#define TFLG1_C6F _TFLG1.Bits.C6F
#define TFLG1_C7F _TFLG1.Bits.C7F


/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte TOF         :1;                                       /* Timer Overflow Flag */
  } Bits;
} TFLG2STR;
extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F);
#define TFLG2 _TFLG2.Byte
#define TFLG2_TOF _TFLG2.Bits.TOF


/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/
typedef union {
  byte Byte;
  struct {
    byte PAI         :1;                                       /* Pulse Accumulator Input Interrupt enable */
    byte PAOVI       :1;                                       /* Pulse Accumulator A Overflow Interrupt enable */
    byte CLK0        :1;                                       /* Clock Select Bit 0 */
    byte CLK1        :1;                                       /* Clock Select Bit 1 */
    byte PEDGE       :1;                                       /* Pulse Accumulator Edge Control */
    byte PAMOD       :1;                                       /* Pulse Accumulator Mode */
    byte PAEN        :1;                                       /* Pulse Accumulator A System Enable */
    byte             :1; 
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpCLK  :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} PACTLSTR;
extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060);
#define PACTL _PACTL.Byte
#define PACTL_PAI _PACTL.Bits.PAI
#define PACTL_PAOVI _PACTL.Bits.PAOVI
#define PACTL_CLK0 _PACTL.Bits.CLK0
#define PACTL_CLK1 _PACTL.Bits.CLK1
#define PACTL_PEDGE _PACTL.Bits.PEDGE
#define PACTL_PAMOD _PACTL.Bits.PAMOD
#define PACTL_PAEN _PACTL.Bits.PAEN
#define PACTL_CLK _PACTL.MergedBits.grpCLK


/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/
typedef union {
  byte Byte;
  struct {
    byte PAIF        :1;                                       /* Pulse Accumulator Input edge Flag */
    byte PAOVF       :1;                                       /* Pulse Accumulator A Overflow Flag */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} PAFLGSTR;
extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061);
#define PAFLG _PAFLG.Byte
#define PAFLG_PAIF _PAFLG.Bits.PAIF
#define PAFLG_PAOVF _PAFLG.Bits.PAOVF


/*** MCCTL - Modulus Down Counter underflow; 0x00000066 ***/
typedef union {
  byte Byte;
  struct {
    byte MCPR0       :1;                                       /* Modulus Counter Prescaler select 0 */
    byte MCPR1       :1;                                       /* Modulus Counter Prescaler select 1 */
    byte MCEN        :1;                                       /* Modulus Down-Counter Enable */
    byte FLMC        :1;                                       /* Force Load Register into the Modulus Counter Count Register */
    byte ICLAT       :1;                                       /* Input Capture Force Latch Action */
    byte RDMCL       :1;                                       /* Read Modulus Down-Counter Load */
    byte MODMC       :1;                                       /* Modulus Mode Enable */
    byte MCZI        :1;                                       /* Modulus Counter Underflow Interrupt Enable */
  } Bits;
  struct {
    byte grpMCPR :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} MCCTLSTR;
extern volatile MCCTLSTR _MCCTL @(REG_BASE + 0x00000066);
#define MCCTL _MCCTL.Byte
#define MCCTL_MCPR0 _MCCTL.Bits.MCPR0
#define MCCTL_MCPR1 _MCCTL.Bits.MCPR1
#define MCCTL_MCEN _MCCTL.Bits.MCEN
#define MCCTL_FLMC _MCCTL.Bits.FLMC
#define MCCTL_ICLAT _MCCTL.Bits.ICLAT
#define MCCTL_RDMCL _MCCTL.Bits.RDMCL
#define MCCTL_MODMC _MCCTL.Bits.MODMC
#define MCCTL_MCZI _MCCTL.Bits.MCZI
#define MCCTL_MCPR _MCCTL.MergedBits.grpMCPR


/*** MCFLG - 16-Bit Modulus Down Counter Flag Register; 0x00000067 ***/
typedef union {
  byte Byte;
  struct {
    byte POLF0       :1;                                       /* First Input Capture Polarity Status 0 */
    byte POLF1       :1;                                       /* First Input Capture Polarity Status 1 */
    byte POLF2       :1;                                       /* First Input Capture Polarity Status 2 */
    byte POLF3       :1;                                       /* First Input Capture Polarity Status 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte MCZF        :1;                                       /* Modulus Counter Underflow Flag */
  } Bits;
  struct {
    byte grpPOLF :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} MCFLGSTR;
extern volatile MCFLGSTR _MCFLG @(REG_BASE + 0x00000067);
#define MCFLG _MCFLG.Byte
#define MCFLG_POLF0 _MCFLG.Bits.POLF0
#define MCFLG_POLF1 _MCFLG.Bits.POLF1
#define MCFLG_POLF2 _MCFLG.Bits.POLF2
#define MCFLG_POLF3 _MCFLG.Bits.POLF3
#define MCFLG_MCZF _MCFLG.Bits.MCZF
#define MCFLG_POLF _MCFLG.MergedBits.grpPOLF


/*** ICPAR - Input Control Pulse Accumulator Register; 0x00000068 ***/
typedef union {
  byte Byte;
  struct {
    byte PA0EN       :1;                                       /* 8-Bit Pulse Accumulator 0 Enable */
    byte PA1EN       :1;                                       /* 8-Bit Pulse Accumulator 1 Enable */
    byte PA2EN       :1;                                       /* 8-Bit Pulse Accumulator 2 Enable */
    byte PA3EN       :1;                                       /* 8-Bit Pulse Accumulator 3 Enable */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} ICPARSTR;
extern volatile ICPARSTR _ICPAR @(REG_BASE + 0x00000068);
#define ICPAR _ICPAR.Byte
#define ICPAR_PA0EN _ICPAR.Bits.PA0EN
#define ICPAR_PA1EN _ICPAR.Bits.PA1EN
#define ICPAR_PA2EN _ICPAR.Bits.PA2EN
#define ICPAR_PA3EN _ICPAR.Bits.PA3EN


/*** DLYCT - Delay Counter Control Register; 0x00000069 ***/
typedef union {
  byte Byte;
  struct {
    byte DLY0        :1;                                       /* Delay Counter Select 0 */
    byte DLY1        :1;                                       /* Delay Counter Select 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDLY  :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DLYCTSTR;
extern volatile DLYCTSTR _DLYCT @(REG_BASE + 0x00000069);
#define DLYCT _DLYCT.Byte
#define DLYCT_DLY0 _DLYCT.Bits.DLY0
#define DLYCT_DLY1 _DLYCT.Bits.DLY1
#define DLYCT_DLY _DLYCT.MergedBits.grpDLY


/*** ICOVW - Input Control Overwrite Register; 0x0000006A ***/
typedef union {
  byte Byte;
  struct {
    byte NOVW0       :1;                                       /* No Input Capture Overwrite 0 */
    byte NOVW1       :1;                                       /* No Input Capture Overwrite 1 */
    byte NOVW2       :1;                                       /* No Input Capture Overwrite 2 */
    byte NOVW3       :1;                                       /* No Input Capture Overwrite 3 */
    byte NOVW4       :1;                                       /* No Input Capture Overwrite 4 */
    byte NOVW5       :1;                                       /* No Input Capture Overwrite 5 */
    byte NOVW6       :1;                                       /* No Input Capture Overwrite 6 */
    byte NOVW7       :1;                                       /* No Input Capture Overwrite 7 */
  } Bits;
  struct {
    byte grpNOVW :8;
  } MergedBits;
} ICOVWSTR;
extern volatile ICOVWSTR _ICOVW @(REG_BASE + 0x0000006A);
#define ICOVW _ICOVW.Byte
#define ICOVW_NOVW0 _ICOVW.Bits.NOVW0
#define ICOVW_NOVW1 _ICOVW.Bits.NOVW1
#define ICOVW_NOVW2 _ICOVW.Bits.NOVW2
#define ICOVW_NOVW3 _ICOVW.Bits.NOVW3
#define ICOVW_NOVW4 _ICOVW.Bits.NOVW4
#define ICOVW_NOVW5 _ICOVW.Bits.NOVW5
#define ICOVW_NOVW6 _ICOVW.Bits.NOVW6
#define ICOVW_NOVW7 _ICOVW.Bits.NOVW7
#define ICOVW_NOVW _ICOVW.MergedBits.grpNOVW


/*** ICSYS - Input Control System Control Register; 0x0000006B ***/
typedef union {
  byte Byte;
  struct {
    byte LATQ        :1;                                       /* Input Control Latch or Queue Mode Enable */
    byte BUFEN       :1;                                       /* IC Buffer Enable */
    byte PACMX       :1;                                       /* 8-Bit Pulse Accumulators Maximum Count */
    byte TFMOD       :1;                                       /* Timer Flag-setting Mode */
    byte SH04        :1;                                       /* Share Input action of Input Capture Channels 0 and 4 */
    byte SH15        :1;                                       /* Share Input action of Input Capture Channels 1 and 5 */
    byte SH26        :1;                                       /* Share Input action of Input Capture Channels 2 and 6 */
    byte SH37        :1;                                       /* Share Input action of Input Capture Channels 3 and 7 */
  } Bits;
} ICSYSSTR;
extern volatile ICSYSSTR _ICSYS @(REG_BASE + 0x0000006B);
#define ICSYS _ICSYS.Byte
#define ICSYS_LATQ _ICSYS.Bits.LATQ
#define ICSYS_BUFEN _ICSYS.Bits.BUFEN
#define ICSYS_PACMX _ICSYS.Bits.PACMX
#define ICSYS_TFMOD _ICSYS.Bits.TFMOD
#define ICSYS_SH04 _ICSYS.Bits.SH04
#define ICSYS_SH15 _ICSYS.Bits.SH15
#define ICSYS_SH26 _ICSYS.Bits.SH26
#define ICSYS_SH37 _ICSYS.Bits.SH37


/*** TIMTST - Timer Test Register; 0x0000006D ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte TCBYP       :1;                                       /* Main Timer Divider Chain Bypass */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} TIMTSTSTR;
extern volatile TIMTSTSTR _TIMTST @(REG_BASE + 0x0000006D);
#define TIMTST _TIMTST.Byte
#define TIMTST_TCBYP _TIMTST.Bits.TCBYP


/*** PBCTL - 16-Bit Pulse Accumulator B Control Register; 0x00000070 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte PBOVI       :1;                                       /* Pulse Accumulator B Overflow Interrupt enable */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte PBEN        :1;                                       /* Pulse Accumulator B System Enable */
    byte             :1; 
  } Bits;
} PBCTLSTR;
extern volatile PBCTLSTR _PBCTL @(REG_BASE + 0x00000070);
#define PBCTL _PBCTL.Byte
#define PBCTL_PBOVI _PBCTL.Bits.PBOVI
#define PBCTL_PBEN _PBCTL.Bits.PBEN


/*** PBFLG - Pulse Accumulator B Flag Register; 0x00000071 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte PBOVF       :1;                                       /* Pulse Accumulator B Overflow Flag */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} PBFLGSTR;
extern volatile PBFLGSTR _PBFLG @(REG_BASE + 0x00000071);
#define PBFLG _PBFLG.Byte
#define PBFLG_PBOVF _PBFLG.Bits.PBOVF


/*** ATD0STAT0 - ATD 0 Status Register 0; 0x00000086 ***/
typedef union {
  byte Byte;
  struct {
    byte CC0         :1;                                       /* Conversion Counter 0 */
    byte CC1         :1;                                       /* Conversion Counter 1 */
    byte CC2         :1;                                       /* Conversion Counter 2 */
    byte             :1; 
    byte FIFOR       :1;                                       /* FIFO Over Run Flag */
    byte ETORF       :1;                                       /* External Trigger Overrun Flag */
    byte             :1; 
    byte SCF         :1;                                       /* Sequence Complete Flag */
  } Bits;
  struct {
    byte grpCC   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ATD0STAT0STR;
extern volatile ATD0STAT0STR _ATD0STAT0 @(REG_BASE + 0x00000086);
#define ATD0STAT0 _ATD0STAT0.Byte
#define ATD0STAT0_CC0 _ATD0STAT0.Bits.CC0
#define ATD0STAT0_CC1 _ATD0STAT0.Bits.CC1
#define ATD0STAT0_CC2 _ATD0STAT0.Bits.CC2
#define ATD0STAT0_FIFOR _ATD0STAT0.Bits.FIFOR
#define ATD0STAT0_ETORF _ATD0STAT0.Bits.ETORF
#define ATD0STAT0_SCF _ATD0STAT0.Bits.SCF
#define ATD0STAT0_CC _ATD0STAT0.MergedBits.grpCC


/*** ATD0STAT1 - ATD 0 Status Register 1; 0x0000008B ***/
typedef union {
  byte Byte;
  struct {
    byte CCF0        :1;                                       /* Conversion Complete Flag 0 */
    byte CCF1        :1;                                       /* Conversion Complete Flag 1 */
    byte CCF2        :1;                                       /* Conversion Complete Flag 2 */
    byte CCF3        :1;                                       /* Conversion Complete Flag 3 */
    byte CCF4        :1;                                       /* Conversion Complete Flag 4 */
    byte CCF5        :1;                                       /* Conversion Complete Flag 5 */
    byte CCF6        :1;                                       /* Conversion Complete Flag 6 */
    byte CCF7        :1;                                       /* Conversion Complete Flag 7 */
  } Bits;
  struct {
    byte grpCCF  :8;
  } MergedBits;
} ATD0STAT1STR;
extern volatile ATD0STAT1STR _ATD0STAT1 @(REG_BASE + 0x0000008B);
#define ATD0STAT1 _ATD0STAT1.Byte
#define ATD0STAT1_CCF0 _ATD0STAT1.Bits.CCF0
#define ATD0STAT1_CCF1 _ATD0STAT1.Bits.CCF1
#define ATD0STAT1_CCF2 _ATD0STAT1.Bits.CCF2
#define ATD0STAT1_CCF3 _ATD0STAT1.Bits.CCF3
#define ATD0STAT1_CCF4 _ATD0STAT1.Bits.CCF4
#define ATD0STAT1_CCF5 _ATD0STAT1.Bits.CCF5
#define ATD0STAT1_CCF6 _ATD0STAT1.Bits.CCF6
#define ATD0STAT1_CCF7 _ATD0STAT1.Bits.CCF7
#define ATD0STAT1_CCF _ATD0STAT1.MergedBits.grpCCF


/*** ATD0DIEN - ATD 0 Input Enable Mask Register; 0x0000008D ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Disable/Enable Digital Input Buffer Bit 0 */
    byte BIT1        :1;                                       /* Disable/Enable Digital Input Buffer Bit 1 */
    byte BIT2        :1;                                       /* Disable/Enable Digital Input Buffer Bit 2 */
    byte BIT3        :1;                                       /* Disable/Enable Digital Input Buffer Bit 3 */
    byte BIT4        :1;                                       /* Disable/Enable Digital Input Buffer Bit 4 */
    byte BIT5        :1;                                       /* Disable/Enable Digital Input Buffer Bit 5 */
    byte BIT6        :1;                                       /* Disable/Enable Digital Input Buffer Bit 6 */
    byte BIT7        :1;                                       /* Disable/Enable Digital Input Buffer Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} ATD0DIENSTR;
extern volatile ATD0DIENSTR _ATD0DIEN @(REG_BASE + 0x0000008D);
#define ATD0DIEN _ATD0DIEN.Byte
#define ATD0DIEN_BIT0 _ATD0DIEN.Bits.BIT0
#define ATD0DIEN_BIT1 _ATD0DIEN.Bits.BIT1
#define ATD0DIEN_BIT2 _ATD0DIEN.Bits.BIT2
#define ATD0DIEN_BIT3 _ATD0DIEN.Bits.BIT3
#define ATD0DIEN_BIT4 _ATD0DIEN.Bits.BIT4
#define ATD0DIEN_BIT5 _ATD0DIEN.Bits.BIT5
#define ATD0DIEN_BIT6 _ATD0DIEN.Bits.BIT6
#define ATD0DIEN_BIT7 _ATD0DIEN.Bits.BIT7
#define ATD0DIEN_BIT _ATD0DIEN.MergedBits.grpBIT


/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* AN0 */
    byte BIT1        :1;                                       /* AN1 */
    byte BIT2        :1;                                       /* AN2 */
    byte BIT3        :1;                                       /* AN3 */
    byte BIT4        :1;                                       /* AN4 */
    byte BIT5        :1;                                       /* AN5 */
    byte BIT6        :1;                                       /* AN6 */
    byte BIT7        :1;                                       /* AN7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} PORTAD0STR;
extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F);
#define PORTAD0 _PORTAD0.Byte
#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0
#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1
#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2
#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3
#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4
#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5
#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6
#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7
#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT


/*** PWME - PWM Enable Register; 0x000000A0 ***/
typedef union {
  byte Byte;
  struct {
    byte PWME0       :1;                                       /* Pulse Width Channel 0 Enable */
    byte PWME1       :1;                                       /* Pulse Width Channel 1 Enable */
    byte PWME2       :1;                                       /* Pulse Width Channel 2 Enable */
    byte PWME3       :1;                                       /* Pulse Width Channel 3 Enable */
    byte PWME4       :1;                                       /* Pulse Width Channel 4 Enable */
    byte PWME5       :1;                                       /* Pulse Width Channel 5 Enable */
    byte PWME6       :1;                                       /* Pulse Width Channel 6 Enable */
    byte PWME7       :1;                                       /* Pulse Width Channel 7 Enable */
  } Bits;
  struct {
    byte grpPWME :8;
  } MergedBits;
} PWMESTR;
extern volatile PWMESTR _PWME @(REG_BASE + 0x000000A0);
#define PWME _PWME.Byte
#define PWME_PWME0 _PWME.Bits.PWME0
#define PWME_PWME1 _PWME.Bits.PWME1
#define PWME_PWME2 _PWME.Bits.PWME2
#define PWME_PWME3 _PWME.Bits.PWME3
#define PWME_PWME4 _PWME.Bits.PWME4
#define PWME_PWME5 _PWME.Bits.PWME5
#define PWME_PWME6 _PWME.Bits.PWME6
#define PWME_PWME7 _PWME.Bits.PWME7
#define PWME_PWME _PWME.MergedBits.grpPWME


/*** PWMPOL - PWM Polarity Register; 0x000000A1 ***/
typedef union {
  byte Byte;
  struct {
    byte PPOL0       :1;                                       /* Pulse Width Channel 0 Polarity */
    byte PPOL1       :1;                                       /* Pulse Width Channel 1 Polarity */
    byte PPOL2       :1;                                       /* Pulse Width Channel 2 Polarity */
    byte PPOL3       :1;                                       /* Pulse Width Channel 3 Polarity */
    byte PPOL4       :1;                                       /* Pulse Width Channel 4 Polarity */
    byte PPOL5       :1;                                       /* Pulse Width Channel 5 Polarity */
    byte PPOL6       :1;                                       /* Pulse Width Channel 6 Polarity */
    byte PPOL7       :1;                                       /* Pulse Width Channel 7 Polarity */
  } Bits;
  struct {
    byte grpPPOL :8;
  } MergedBits;
} PWMPOLSTR;
extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000A1);
#define PWMPOL _PWMPOL.Byte
#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0
#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1
#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2
#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3
#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4
#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5
#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6
#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7
#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL


/*** PWMCLK - PWM Clock Select Register; 0x000000A2 ***/
typedef union {
  byte Byte;
  struct {
    byte PCLK0       :1;                                       /* Pulse Width Channel 0 Clock Select */
    byte PCLK1       :1;                                       /* Pulse Width Channel 1 Clock Select */
    byte PCLK2       :1;                                       /* Pulse Width Channel 2 Clock Select */
    byte PCLK3       :1;                                       /* Pulse Width Channel 3 Clock Select */
    byte PCLK4       :1;                                       /* Pulse Width Channel 4 Clock Select */
    byte PCLK5       :1;                                       /* Pulse Width Channel 5 Clock Select */
    byte PCLK6       :1;                                       /* Pulse Width Channel 6 Clock Select */
    byte PCLK7       :1;                                       /* Pulse Width Channel 7 Clock Select */
  } Bits;
  struct {
    byte grpPCLK :8;
  } MergedBits;
} PWMCLKSTR;
extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000A2);
#define PWMCLK _PWMCLK.Byte
#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0
#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1
#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2
#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3
#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4
#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5
#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6
#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7
#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK


/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000A3 ***/
typedef union {
  byte Byte;
  struct {
    byte PCKA0       :1;                                       /* Prescaler Select for Clock A 0 */
    byte PCKA1       :1;                                       /* Prescaler Select for Clock A 1 */
    byte PCKA2       :1;                                       /* Prescaler Select for Clock A 2 */
    byte             :1; 
    byte PCKB0       :1;                                       /* Prescaler Select for Clock B 0 */
    byte PCKB1       :1;                                       /* Prescaler Select for Clock B 1 */
    byte PCKB2       :1;                                       /* Prescaler Select for Clock B 2 */
    byte             :1; 
  } Bits;
  struct {
    byte grpPCKA :3;
    byte         :1;
    byte grpPCKB :3;
    byte         :1;
  } MergedBits;
} PWMPRCLKSTR;
extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000A3);
#define PWMPRCLK _PWMPRCLK.Byte
#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0
#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1
#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2
#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0
#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1
#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2
#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA
#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB


/*** PWMCAE - PWM Center Align Enable Register; 0x000000A4 ***/
typedef union {
  byte Byte;
  struct {
    byte CAE0        :1;                                       /* Center Aligned Output Mode on channel 0 */
    byte CAE1        :1;                                       /* Center Aligned Output Mode on channel 1 */
    byte CAE2        :1;                                       /* Center Aligned Output Mode on channel 2 */
    byte CAE3        :1;                                       /* Center Aligned Output Mode on channel 3 */
    byte CAE4        :1;                                       /* Center Aligned Output Mode on channel 4 */
    byte CAE5        :1;                                       /* Center Aligned Output Mode on channel 5 */
    byte CAE6        :1;                                       /* Center Aligned Output Mode on channel 6 */
    byte CAE7        :1;                                       /* Center Aligned Output Mode on channel 7 */
  } Bits;
  struct {
    byte grpCAE  :8;
  } MergedBits;
} PWMCAESTR;
extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000A4);
#define PWMCAE _PWMCAE.Byte
#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0
#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1
#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2
#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3
#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4
#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5
#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6
#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7
#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE


/*** PWMCTL - PWM Control Register; 0x000000A5 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte PFRZ        :1;                                       /* PWM Counters Stop in Freeze Mode */
    byte PSWAI       :1;                                       /* PWM Stops in Wait Mode */
    byte CON01       :1;                                       /* Concatenate channels 0 and 1 */
    byte CON23       :1;                                       /* Concatenate channels 2 and 3 */
    byte CON45       :1;                                       /* Concatenate channels 4 and 5 */
    byte CON67       :1;                                       /* Concatenate channels 6 and 7 */
  } Bits;
} PWMCTLSTR;
extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000A5);
#define PWMCTL _PWMCTL.Byte
#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ
#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI
#define PWMCTL_CON01 _PWMCTL.Bits.CON01
#define PWMCTL_CON23 _PWMCTL.Bits.CON23
#define PWMCTL_CON45 _PWMCTL.Bits.CON45
#define PWMCTL_CON67 _PWMCTL.Bits.CON67


/*** PWMSCLA - PWM Scale A Register; 0x000000A8 ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* PWM Scale A Bit 0 */
    byte BIT1        :1;                                       /* PWM Scale A Bit 1 */
    byte BIT2        :1;                                       /* PWM Scale A Bit 2 */
    byte BIT3        :1;                                       /* PWM Scale A Bit 3 */
    byte BIT4        :1;                                       /* PWM Scale A Bit 4 */
    byte BIT5        :1;                                       /* PWM Scale A Bit 5 */
    byte BIT6        :1;                                       /* PWM Scale A Bit 6 */
    byte BIT7        :1;                                       /* PWM Scale A Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} PWMSCLASTR;
extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000A8);
#define PWMSCLA _PWMSCLA.Byte
#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0
#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1
#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2
#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3
#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4
#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5
#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6
#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7
#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT


/*** PWMSCLB - PWM Scale B Register; 0x000000A9 ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* PWM Scale B Bit 0 */
    byte BIT1        :1;                                       /* PWM Scale B Bit 1 */
    byte BIT2        :1;                                       /* PWM Scale B Bit 2 */
    byte BIT3        :1;                                       /* PWM Scale B Bit 3 */
    byte BIT4        :1;                                       /* PWM Scale B Bit 4 */
    byte BIT5        :1;                                       /* PWM Scale B Bit 5 */
    byte BIT6        :1;                                       /* PWM Scale B Bit 6 */
    byte BIT7        :1;                                       /* PWM Scale B Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} PWMSCLBSTR;
extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000A9);
#define PWMSCLB _PWMSCLB.Byte
#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0
#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1
#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2
#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3
#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4
#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5
#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6
#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7
#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT


/*** PWMSDN - PWM Shutdown Register; 0x000000C4 ***/
typedef union {
  byte Byte;
  struct {
    byte PWM7ENA     :1;                                       /* PWM emergency shutdown Enable */
    byte PWM7INL     :1;                                       /* PWM shutdown active input level for ch. 7 */
    byte PWM7IN      :1;                                       /* PWM channel 7 input status */
    byte             :1; 
    byte PWMLVL      :1;                                       /* PWM shutdown output Level */
    byte PWMRSTRT    :1;                                       /* PWM Restart */
    byte PWMIE       :1;                                       /* PWM Interrupt Enable */
    byte PWMIF       :1;                                       /* PWM Interrupt Flag */
  } Bits;
} PWMSDNSTR;
extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000C4);
#define PWMSDN _PWMSDN.Byte
#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA
#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL
#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN
#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL
#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT
#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE
#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF


/*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA ***/
typedef union {
  byte Byte;
  struct {
    byte PT          :1;                                       /* Parity Type Bit */
    byte PE          :1;                                       /* Parity Enable Bit */
    byte ILT         :1;                                       /* Idle Line Type Bit */
    byte WAKE        :1;                                       /* Wakeup Condition Bit */
    byte M           :1;                                       /* Data Format Mode Bit */
    byte RSRC        :1;                                       /* Receiver Source Bit */
    byte SCISWAI     :1;                                       /* SCI 0 Stop in Wait Mode Bit */
    byte LOOPS       :1;                                       /* Loop Select Bit */
  } Bits;
} SCI0CR1STR;
extern volatile SCI0CR1STR _SCI0CR1 @(REG_BASE + 0x000000CA);
#define SCI0CR1 _SCI0CR1.Byte
#define SCI0CR1_PT _SCI0CR1.Bits.PT
#define SCI0CR1_PE _SCI0CR1.Bits.PE
#define SCI0CR1_ILT _SCI0CR1.Bits.ILT
#define SCI0CR1_WAKE _SCI0CR1.Bits.WAKE
#define SCI0CR1_M _SCI0CR1.Bits.M
#define SCI0CR1_RSRC _SCI0CR1.Bits.RSRC
#define SCI0CR1_SCISWAI _SCI0CR1.Bits.SCISWAI
#define SCI0CR1_LOOPS _SCI0CR1.Bits.LOOPS


/*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB ***/
typedef union {
  byte Byte;
  struct {
    byte SBK         :1;                                       /* Send Break Bit */
    byte RWU         :1;                                       /* Receiver Wakeup Bit */
    byte RE          :1;                                       /* Receiver Enable Bit */
    byte TE          :1;                                       /* Transmitter Enable Bit */
    byte ILIE        :1;                                       /* Idle Line Interrupt Enable Bit */
    byte RIE         :1;                                       /* Receiver Full Interrupt Enable Bit */
    byte TCIE        :1;                                       /* Transmission Complete Interrupt Enable Bit */
    byte SCTIE       :1;                                       /* Transmitter Interrupt Enable Bit */
  } Bits;
} SCI0CR2STR;
extern volatile SCI0CR2STR _SCI0CR2 @(REG_BASE + 0x000000CB);
#define SCI0CR2 _SCI0CR2.Byte
#define SCI0CR2_SBK _SCI0CR2.Bits.SBK
#define SCI0CR2_RWU _SCI0CR2.Bits.RWU
#define SCI0CR2_RE _SCI0CR2.Bits.RE
#define SCI0CR2_TE _SCI0CR2.Bits.TE
#define SCI0CR2_ILIE _SCI0CR2.Bits.ILIE
#define SCI0CR2_RIE _SCI0CR2.Bits.RIE
#define SCI0CR2_TCIE _SCI0CR2.Bits.TCIE
#define SCI0CR2_SCTIE _SCI0CR2.Bits.SCTIE


/*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC ***/
typedef union {
  byte Byte;
  struct {
    byte PF          :1;                                       /* Parity Error Flag */
    byte FE          :1;                                       /* Framing Error Flag */
    byte NF          :1;                                       /* Noise Flag */
    byte OR          :1;                                       /* Overrun Flag */
    byte IDLE        :1;                                       /* Idle Line Flag */
    byte RDRF        :1;                                       /* Receive Data Register Full Flag */
    byte TC          :1;                                       /* Transmit Complete Flag */
    byte TDRE        :1;                                       /* Transmit Data Register Empty Flag */
  } Bits;
} SCI0SR1STR;
extern volatile SCI0SR1STR _SCI0SR1 @(REG_BASE + 0x000000CC);
#define SCI0SR1 _SCI0SR1.Byte
#define SCI0SR1_PF _SCI0SR1.Bits.PF
#define SCI0SR1_FE _SCI0SR1.Bits.FE
#define SCI0SR1_NF _SCI0SR1.Bits.NF
#define SCI0SR1_OR _SCI0SR1.Bits.OR
#define SCI0SR1_IDLE _SCI0SR1.Bits.IDLE
#define SCI0SR1_RDRF _SCI0SR1.Bits.RDRF
#define SCI0SR1_TC _SCI0SR1.Bits.TC
#define SCI0SR1_TDRE _SCI0SR1.Bits.TDRE


/*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD ***/
typedef union {
  byte Byte;
  struct {
    byte RAF         :1;                                       /* Receiver Active Flag */
    byte TXDIR       :1;                                       /* Transmitter pin data direction in Single-Wire mode */
    byte BRK13       :1;                                       /* Break Transmit character length */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SCI0SR2STR;
extern volatile SCI0SR2STR _SCI0SR2 @(REG_BASE + 0x000000CD);
#define SCI0SR2 _SCI0SR2.Byte
#define SCI0SR2_RAF _SCI0SR2.Bits.RAF
#define SCI0SR2_TXDIR _SCI0SR2.Bits.TXDIR
#define SCI0SR2_BRK13 _SCI0SR2.Bits.BRK13


/*** SCI0DRH - SCI 0 Data Register High; 0x000000CE ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte T8          :1;                                       /* Transmit Bit 8 */
    byte R8          :1;                                       /* Received Bit 8 */
  } Bits;
} SCI0DRHSTR;
extern volatile SCI0DRHSTR _SCI0DRH @(REG_BASE + 0x000000CE);
#define SCI0DRH _SCI0DRH.Byte
#define SCI0DRH_T8 _SCI0DRH.Bits.T8
#define SCI0DRH_R8 _SCI0DRH.Bits.R8


/*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF ***/
typedef union {
  byte Byte;
  struct {
    byte R0_T0       :1;                                       /* Received bit 0 or Transmit bit 0 */
    byte R1_T1       :1;                                       /* Received bit 1 or Transmit bit 1 */
    byte R2_T2       :1;                                       /* Received bit 2 or Transmit bit 2 */
    byte R3_T3       :1;                                       /* Received bit 3 or Transmit bit 3 */
    byte R4_T4       :1;                                       /* Received bit 4 or Transmit bit 4 */
    byte R5_T5       :1;                                       /* Received bit 5 or Transmit bit 5 */
    byte R6_T6       :1;                                       /* Received bit 6 or Transmit bit 6 */
    byte R7_T7       :1;                                       /* Received bit 7 or Transmit bit 7 */
  } Bits;
} SCI0DRLSTR;
extern volatile SCI0DRLSTR _SCI0DRL @(REG_BASE + 0x000000CF);
#define SCI0DRL _SCI0DRL.Byte
#define SCI0DRL_R0_T0 _SCI0DRL.Bits.R0_T0
#define SCI0DRL_R1_T1 _SCI0DRL.Bits.R1_T1
#define SCI0DRL_R2_T2 _SCI0DRL.Bits.R2_T2
#define SCI0DRL_R3_T3 _SCI0DRL.Bits.R3_T3
#define SCI0DRL_R4_T4 _SCI0DRL.Bits.R4_T4
#define SCI0DRL_R5_T5 _SCI0DRL.Bits.R5_T5
#define SCI0DRL_R6_T6 _SCI0DRL.Bits.R6_T6
#define SCI0DRL_R7_T7 _SCI0DRL.Bits.R7_T7


/*** SCI1CR1 - SCI 1 Control Register 1; 0x000000D2 ***/
typedef union {
  byte Byte;
  struct {
    byte PT          :1;                                       /* Parity Type Bit */
    byte PE          :1;                                       /* Parity Enable Bit */
    byte ILT         :1;                                       /* Idle Line Type Bit */
    byte WAKE        :1;                                       /* Wakeup Condition Bit */
    byte M           :1;                                       /* Data Format Mode Bit */
    byte RSRC        :1;                                       /* Receiver Source Bit */
    byte SCISWAI     :1;                                       /* SCI 1 Stop in Wait Mode Bit */
    byte LOOPS       :1;                                       /* Loop Select Bit */
  } Bits;
} SCI1CR1STR;
extern volatile SCI1CR1STR _SCI1CR1 @(REG_BASE + 0x000000D2);
#define SCI1CR1 _SCI1CR1.Byte
#define SCI1CR1_PT _SCI1CR1.Bits.PT
#define SCI1CR1_PE _SCI1CR1.Bits.PE
#define SCI1CR1_ILT _SCI1CR1.Bits.ILT
#define SCI1CR1_WAKE _SCI1CR1.Bits.WAKE
#define SCI1CR1_M _SCI1CR1.Bits.M
#define SCI1CR1_RSRC _SCI1CR1.Bits.RSRC
#define SCI1CR1_SCISWAI _SCI1CR1.Bits.SCISWAI
#define SCI1CR1_LOOPS _SCI1CR1.Bits.LOOPS


/*** SCI1CR2 - SCI 1 Control Register 2; 0x000000D3 ***/
typedef union {
  byte Byte;
  struct {
    byte SBK         :1;                                       /* Send Break Bit */
    byte RWU         :1;                                       /* Receiver Wakeup Bit */
    byte RE          :1;                                       /* Receiver Enable Bit */
    byte TE          :1;                                       /* Transmitter Enable Bit */
    byte ILIE        :1;                                       /* Idle Line Interrupt Enable Bit */
    byte RIE         :1;                                       /* Receiver Full Interrupt Enable Bit */
    byte TCIE        :1;                                       /* Transmission Complete Interrupt Enable Bit */
    byte SCTIE       :1;                                       /* Transmitter Interrupt Enable Bit */
  } Bits;
} SCI1CR2STR;
extern volatile SCI1CR2STR _SCI1CR2 @(REG_BASE + 0x000000D3);
#define SCI1CR2 _SCI1CR2.Byte
#define SCI1CR2_SBK _SCI1CR2.Bits.SBK
#define SCI1CR2_RWU _SCI1CR2.Bits.RWU
#define SCI1CR2_RE _SCI1CR2.Bits.RE
#define SCI1CR2_TE _SCI1CR2.Bits.TE
#define SCI1CR2_ILIE _SCI1CR2.Bits.ILIE
#define SCI1CR2_RIE _SCI1CR2.Bits.RIE
#define SCI1CR2_TCIE _SCI1CR2.Bits.TCIE
#define SCI1CR2_SCTIE _SCI1CR2.Bits.SCTIE


/*** SCI1SR1 - SCI 1 Status Register 1; 0x000000D4 ***/
typedef union {
  byte Byte;
  struct {
    byte PF          :1;                                       /* Parity Error Flag */
    byte FE          :1;                                       /* Framing Error Flag */
    byte NF          :1;                                       /* Noise Flag */
    byte OR          :1;                                       /* Overrun Flag */
    byte IDLE        :1;                                       /* Idle Line Flag */
    byte RDRF        :1;                                       /* Receive Data Register Full Flag */
    byte TC          :1;                                       /* Transmit Complete Flag */
    byte TDRE        :1;                                       /* Transmit Data Register Empty Flag */
  } Bits;
} SCI1SR1STR;
extern volatile SCI1SR1STR _SCI1SR1 @(REG_BASE + 0x000000D4);
#define SCI1SR1 _SCI1SR1.Byte
#define SCI1SR1_PF _SCI1SR1.Bits.PF
#define SCI1SR1_FE _SCI1SR1.Bits.FE
#define SCI1SR1_NF _SCI1SR1.Bits.NF
#define SCI1SR1_OR _SCI1SR1.Bits.OR
#define SCI1SR1_IDLE _SCI1SR1.Bits.IDLE
#define SCI1SR1_RDRF _SCI1SR1.Bits.RDRF
#define SCI1SR1_TC _SCI1SR1.Bits.TC
#define SCI1SR1_TDRE _SCI1SR1.Bits.TDRE


/*** SCI1SR2 - SCI 1 Status Register 2; 0x000000D5 ***/
typedef union {
  byte Byte;
  struct {
    byte RAF         :1;                                       /* Receiver Active Flag */
    byte TXDIR       :1;                                       /* Transmitter pin data direction in Single-Wire mode */
    byte BRK13       :1;                                       /* Break Transmit character length */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SCI1SR2STR;
extern volatile SCI1SR2STR _SCI1SR2 @(REG_BASE + 0x000000D5);
#define SCI1SR2 _SCI1SR2.Byte
#define SCI1SR2_RAF _SCI1SR2.Bits.RAF
#define SCI1SR2_TXDIR _SCI1SR2.Bits.TXDIR
#define SCI1SR2_BRK13 _SCI1SR2.Bits.BRK13


/*** SCI1DRH - SCI 1 Data Register High; 0x000000D6 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte T8          :1;                                       /* Transmit Bit 8 */
    byte R8          :1;                                       /* Received Bit 8 */
  } Bits;
} SCI1DRHSTR;
extern volatile SCI1DRHSTR _SCI1DRH @(REG_BASE + 0x000000D6);
#define SCI1DRH _SCI1DRH.Byte
#define SCI1DRH_T8 _SCI1DRH.Bits.T8
#define SCI1DRH_R8 _SCI1DRH.Bits.R8


/*** SCI1DRL - SCI 1 Data Register Low; 0x000000D7 ***/
typedef union {
  byte Byte;
  struct {
    byte R0_T0       :1;                                       /* Received bit 0 or Transmit bit 0 */
    byte R1_T1       :1;                                       /* Received bit 1 or Transmit bit 1 */
    byte R2_T2       :1;                                       /* Received bit 2 or Transmit bit 2 */
    byte R3_T3       :1;                                       /* Received bit 3 or Transmit bit 3 */
    byte R4_T4       :1;                                       /* Received bit 4 or Transmit bit 4 */
    byte R5_T5       :1;                                       /* Received bit 5 or Transmit bit 5 */
    byte R6_T6       :1;                                       /* Received bit 6 or Transmit bit 6 */
    byte R7_T7       :1;                                       /* Received bit 7 or Transmit bit 7 */
  } Bits;
} SCI1DRLSTR;
extern volatile SCI1DRLSTR _SCI1DRL @(REG_BASE + 0x000000D7);
#define SCI1DRL _SCI1DRL.Byte
#define SCI1DRL_R0_T0 _SCI1DRL.Bits.R0_T0
#define SCI1DRL_R1_T1 _SCI1DRL.Bits.R1_T1
#define SCI1DRL_R2_T2 _SCI1DRL.Bits.R2_T2
#define SCI1DRL_R3_T3 _SCI1DRL.Bits.R3_T3
#define SCI1DRL_R4_T4 _SCI1DRL.Bits.R4_T4
#define SCI1DRL_R5_T5 _SCI1DRL.Bits.R5_T5
#define SCI1DRL_R6_T6 _SCI1DRL.Bits.R6_T6
#define SCI1DRL_R7_T7 _SCI1DRL.Bits.R7_T7


/*** SPI0CR1 - SPI 0 Control Register; 0x000000D8 ***/
typedef union {
  byte Byte;
  struct {
    byte LSBFE       :1;                                       /* SPI 0 LSB-First Enable */
    byte SSOE        :1;                                       /* Slave Select Output Enable */
    byte CPHA        :1;                                       /* SPI 0 Clock Phase Bit */
    byte CPOL        :1;                                       /* SPI 0 Clock Polarity Bit */
    byte MSTR        :1;                                       /* SPI 0 Master/Slave Mode Select Bit */
    byte SPTIE       :1;                                       /* SPI 0 Transmit Interrupt Enable */
    byte SPE         :1;                                       /* SPI 0 System Enable Bit */
    byte SPIE        :1;                                       /* SPI 0 Interrupt Enable Bit */
  } Bits;
} SPI0CR1STR;
extern volatile SPI0CR1STR _SPI0CR1 @(REG_BASE + 0x000000D8);
#define SPI0CR1 _SPI0CR1.Byte
#define SPI0CR1_LSBFE _SPI0CR1.Bits.LSBFE
#define SPI0CR1_SSOE _SPI0CR1.Bits.SSOE
#define SPI0CR1_CPHA _SPI0CR1.Bits.CPHA
#define SPI0CR1_CPOL _SPI0CR1.Bits.CPOL
#define SPI0CR1_MSTR _SPI0CR1.Bits.MSTR
#define SPI0CR1_SPTIE _SPI0CR1.Bits.SPTIE
#define SPI0CR1_SPE _SPI0CR1.Bits.SPE
#define SPI0CR1_SPIE _SPI0CR1.Bits.SPIE


/*** SPI0CR2 - SPI 0 Control Register 2; 0x000000D9 ***/
typedef union {
  byte Byte;
  struct {
    byte SPC0        :1;                                       /* Serial Pin Control Bit 0 */
    byte SPISWAI     :1;                                       /* SPI 0 Stop in Wait Mode Bit */
    byte             :1; 
    byte BIDIROE     :1;                                       /* Output enable in the Bidirectional mode of operation */
    byte MODFEN      :1;                                       /* Mode Fault Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SPI0CR2STR;
extern volatile SPI0CR2STR _SPI0CR2 @(REG_BASE + 0x000000D9);
#define SPI0CR2 _SPI0CR2.Byte
#define SPI0CR2_SPC0 _SPI0CR2.Bits.SPC0
#define SPI0CR2_SPISWAI _SPI0CR2.Bits.SPISWAI
#define SPI0CR2_BIDIROE _SPI0CR2.Bits.BIDIROE
#define SPI0CR2_MODFEN _SPI0CR2.Bits.MODFEN


/*** SPI0BR - SPI 0 Baud Rate Register; 0x000000DA ***/
typedef union {
  byte Byte;
  struct {
    byte SPR0        :1;                                       /* SPI 0 Baud Rate Selection Bit 0 */
    byte SPR1        :1;                                       /* SPI 0 Baud Rate Selection Bit 1 */
    byte SPR2        :1;                                       /* SPI 0 Baud Rate Selection Bit 2 */
    byte             :1; 
    byte SPPR0       :1;                                       /* SPI 0 Baud Rate Preselection Bits 0 */
    byte SPPR1       :1;                                       /* SPI 0 Baud Rate Preselection Bits 1 */
    byte SPPR2       :1;                                       /* SPI 0 Baud Rate Preselection Bits 2 */
    byte             :1; 
  } Bits;
  struct {
    byte grpSPR  :3;
    byte         :1;
    byte grpSPPR :3;
    byte         :1;
  } MergedBits;
} SPI0BRSTR;
extern volatile SPI0BRSTR _SPI0BR @(REG_BASE + 0x000000DA);
#define SPI0BR _SPI0BR.Byte
#define SPI0BR_SPR0 _SPI0BR.Bits.SPR0
#define SPI0BR_SPR1 _SPI0BR.Bits.SPR1
#define SPI0BR_SPR2 _SPI0BR.Bits.SPR2
#define SPI0BR_SPPR0 _SPI0BR.Bits.SPPR0
#define SPI0BR_SPPR1 _SPI0BR.Bits.SPPR1
#define SPI0BR_SPPR2 _SPI0BR.Bits.SPPR2
#define SPI0BR_SPR _SPI0BR.MergedBits.grpSPR
#define SPI0BR_SPPR _SPI0BR.MergedBits.grpSPPR


/*** SPI0SR - SPI 0 Status Register; 0x000000DB ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte MODF        :1;                                       /* Mode Fault Flag */
    byte SPTEF       :1;                                       /* SPI 0 Transmit Empty Interrupt Flag */
    byte             :1; 
    byte SPIF        :1;                                       /* SPIF Receive Interrupt Flag */
  } Bits;
} SPI0SRSTR;
extern volatile SPI0SRSTR _SPI0SR @(REG_BASE + 0x000000DB);
#define SPI0SR _SPI0SR.Byte
#define SPI0SR_MODF _SPI0SR.Bits.MODF
#define SPI0SR_SPTEF _SPI0SR.Bits.SPTEF
#define SPI0SR_SPIF _SPI0SR.Bits.SPIF


/*** SPI0DR - SPI 0 Data Register; 0x000000DD ***/
typedef union {
  byte Byte;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} SPI0DRSTR;
extern volatile SPI0DRSTR _SPI0DR @(REG_BASE + 0x000000DD);
#define SPI0DR _SPI0DR.Byte
#define SPI0DR_BIT _SPI0DR.MergedBits.grpBIT


/*** IBAD - IIC Address Register; 0x000000E0 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte ADR1        :1;                                       /* Slave Address Bit 1 */
    byte ADR2        :1;                                       /* Slave Address Bit 2 */
    byte ADR3        :1;                                       /* Slave Address Bit 3 */
    byte ADR4        :1;                                       /* Slave Address Bit 4 */
    byte ADR5        :1;                                       /* Slave Address Bit 5 */
    byte ADR6        :1;                                       /* Slave Address Bit 6 */
    byte ADR7        :1;                                       /* Slave Address Bit 7 */
  } Bits;
  struct {
    byte         :1;
    byte grpADR_1 :7;
  } MergedBits;
} IBADSTR;
extern volatile IBADSTR _IBAD @(REG_BASE + 0x000000E0);
#define IBAD _IBAD.Byte
#define IBAD_ADR1 _IBAD.Bits.ADR1
#define IBAD_ADR2 _IBAD.Bits.ADR2
#define IBAD_ADR3 _IBAD.Bits.ADR3
#define IBAD_ADR4 _IBAD.Bits.ADR4
#define IBAD_ADR5 _IBAD.Bits.ADR5
#define IBAD_ADR6 _IBAD.Bits.ADR6
#define IBAD_ADR7 _IBAD.Bits.ADR7
#define IBAD_ADR_1 _IBAD.MergedBits.grpADR_1
#define IBAD_ADR IBAD_ADR_1


/*** IBFD - IIC Frequency Divider Register; 0x000000E1 ***/
typedef union {
  byte Byte;
  struct {
    byte IBC0        :1;                                       /* I-Bus Clock Rate 0 */
    byte IBC1        :1;                                       /* I-Bus Clock Rate 1 */
    byte IBC2        :1;                                       /* I-Bus Clock Rate 2 */
    byte IBC3        :1;                                       /* I-Bus Clock Rate 3 */
    byte IBC4        :1;                                       /* I-Bus Clock Rate 4 */
    byte IBC5        :1;                                       /* I-Bus Clock Rate 5 */
    byte IBC6        :1;                                       /* I-Bus Clock Rate 6 */
    byte IBC7        :1;                                       /* I-Bus Clock Rate 7 */
  } Bits;
  struct {
    byte grpIBC  :8;
  } MergedBits;
} IBFDSTR;
extern volatile IBFDSTR _IBFD @(REG_BASE + 0x000000E1);
#define IBFD _IBFD.Byte
#define IBFD_IBC0 _IBFD.Bits.IBC0
#define IBFD_IBC1 _IBFD.Bits.IBC1
#define IBFD_IBC2 _IBFD.Bits.IBC2
#define IBFD_IBC3 _IBFD.Bits.IBC3
#define IBFD_IBC4 _IBFD.Bits.IBC4
#define IBFD_IBC5 _IBFD.Bits.IBC5
#define IBFD_IBC6 _IBFD.Bits.IBC6
#define IBFD_IBC7 _IBFD.Bits.IBC7
#define IBFD_IBC _IBFD.MergedBits.grpIBC


/*** IBCR - IIC Control Register; 0x000000E2 ***/
typedef union {
  byte Byte;
  struct {
    byte IBSWAI      :1;                                       /* I-Bus Interface Stop in WAIT mode */
    byte             :1; 
    byte RSTA        :1;                                       /* Repeat Start */
    byte TXAK        :1;                                       /* Transmit Acknowledge enable */
    byte TX_RX       :1;                                       /* Transmit/Receive mode select bit */
    byte MS_SL       :1;                                       /* Master/Slave mode select bit */
    byte IBIE        :1;                                       /* I-Bus Interrupt Enable */
    byte IBEN        :1;                                       /* I-Bus Enable */
  } Bits;
} IBCRSTR;
extern volatile IBCRSTR _IBCR @(REG_BASE + 0x000000E2);
#define IBCR _IBCR.Byte
#define IBCR_IBSWAI _IBCR.Bits.IBSWAI
#define IBCR_RSTA _IBCR.Bits.RSTA
#define IBCR_TXAK _IBCR.Bits.TXAK
#define IBCR_TX_RX _IBCR.Bits.TX_RX
#define IBCR_MS_SL _IBCR.Bits.MS_SL
#define IBCR_IBIE _IBCR.Bits.IBIE
#define IBCR_IBEN _IBCR.Bits.IBEN


/*** IBSR - IIC Status Register; 0x000000E3 ***/
typedef union {
  byte Byte;
  struct {
    byte RXAK        :1;                                       /* Received Acknowledge */
    byte IBIF        :1;                                       /* I-Bus Interrupt */
    byte SRW         :1;                                       /* Slave Read/Write */
    byte             :1; 
    byte IBAL        :1;                                       /* Arbitration Lost */
    byte IBB         :1;                                       /* Bus busy bit */
    byte IAAS        :1;                                       /* Addressed as a slave bit */
    byte TCF         :1;                                       /* Data transferring bit */
  } Bits;
} IBSRSTR;
extern volatile IBSRSTR _IBSR @(REG_BASE + 0x000000E3);
#define IBSR _IBSR.Byte
#define IBSR_RXAK _IBSR.Bits.RXAK
#define IBSR_IBIF _IBSR.Bits.IBIF
#define IBSR_SRW _IBSR.Bits.SRW
#define IBSR_IBAL _IBSR.Bits.IBAL
#define IBSR_IBB _IBSR.Bits.IBB
#define IBSR_IAAS _IBSR.Bits.IAAS
#define IBSR_TCF _IBSR.Bits.TCF


/*** IBDR - IIC Data I/O Register; 0x000000E4 ***/
typedef union {
  byte Byte;
  struct {
    byte D0          :1;                                       /* IIC Data Bit 0 */
    byte D1          :1;                                       /* IIC Data Bit 1 */
    byte D2          :1;                                       /* IIC Data Bit 2 */
    byte D3          :1;                                       /* IIC Data Bit 3 */
    byte D4          :1;                                       /* IIC Data Bit 4 */
    byte D5          :1;                                       /* IIC Data Bit 5 */
    byte D6          :1;                                       /* IIC Data Bit 6 */
    byte D7          :1;                                       /* IIC Data Bit 7 */
  } Bits;
  struct {
    byte grpD    :8;
  } MergedBits;
} IBDRSTR;
extern volatile IBDRSTR _IBDR @(REG_BASE + 0x000000E4);
#define IBDR _IBDR.Byte
#define IBDR_D0 _IBDR.Bits.D0
#define IBDR_D1 _IBDR.Bits.D1
#define IBDR_D2 _IBDR.Bits.D2
#define IBDR_D3 _IBDR.Bits.D3
#define IBDR_D4 _IBDR.Bits.D4
#define IBDR_D5 _IBDR.Bits.D5
#define IBDR_D6 _IBDR.Bits.D6
#define IBDR_D7 _IBDR.Bits.D7
#define IBDR_D _IBDR.MergedBits.grpD


/*** DLCBCR1 - BDLC Control Register 1; 0x000000E8 ***/
typedef union {
  byte Byte;
  struct {
    byte WCM         :1;                                       /* Wait Clock Mode */
    byte IE          :1;                                       /* Interrupt Enable */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte CLKS        :1;                                       /* Clock Select */
    byte IMSG        :1;                                       /* Ignore Message */
  } Bits;
} DLCBCR1STR;
extern volatile DLCBCR1STR _DLCBCR1 @(REG_BASE + 0x000000E8);
#define DLCBCR1 _DLCBCR1.Byte
#define DLCBCR1_WCM _DLCBCR1.Bits.WCM
#define DLCBCR1_IE _DLCBCR1.Bits.IE
#define DLCBCR1_CLKS _DLCBCR1.Bits.CLKS
#define DLCBCR1_IMSG _DLCBCR1.Bits.IMSG


/*** DLCBSVR - BDLC State Vector Register; 0x000000E9 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte I0          :1;                                       /* Interrupt State Vector Bit 0 */
    byte I1          :1;                                       /* Interrupt State Vector Bit 1 */
    byte I2          :1;                                       /* Interrupt State Vector Bit 2 */
    byte I3          :1;                                       /* Interrupt State Vector Bit 3 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpI    :4;
    byte         :1;
    byte         :1;
  } MergedBits;
} DLCBSVRSTR;
extern volatile DLCBSVRSTR _DLCBSVR @(REG_BASE + 0x000000E9);
#define DLCBSVR _DLCBSVR.Byte
#define DLCBSVR_I0 _DLCBSVR.Bits.I0
#define DLCBSVR_I1 _DLCBSVR.Bits.I1
#define DLCBSVR_I2 _DLCBSVR.Bits.I2
#define DLCBSVR_I3 _DLCBSVR.Bits.I3
#define DLCBSVR_I _DLCBSVR.MergedBits.grpI


/*** DLCBCR2 - BDLC Control Register 2; 0x000000EA ***/
typedef union {
  byte Byte;
  struct {
    byte TMIFR0      :1;                                       /* Transmit In-Frame Response Control 0 */
    byte TMIFR1      :1;                                       /* Transmit In-Frame Response Control 1 */
    byte TSIFR       :1;                                       /* Transmit In-Frame Response Control 2 */
    byte TEOD        :1;                                       /* Transmit End of Data */
    byte NBFS        :1;                                       /* Normalization Bit Format Select */
    byte RX4XE       :1;                                       /* Receive 4X Enable */
    byte DLOOP       :1;                                       /* Digital Loopback Mode */
    byte SMRST       :1;                                       /* State Machine Reset */
  } Bits;
  struct {
    byte grpTMIFR :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DLCBCR2STR;
extern volatile DLCBCR2STR _DLCBCR2 @(REG_BASE + 0x000000EA);
#define DLCBCR2 _DLCBCR2.Byte
#define DLCBCR2_TMIFR0 _DLCBCR2.Bits.TMIFR0
#define DLCBCR2_TMIFR1 _DLCBCR2.Bits.TMIFR1
#define DLCBCR2_TSIFR _DLCBCR2.Bits.TSIFR
#define DLCBCR2_TEOD _DLCBCR2.Bits.TEOD
#define DLCBCR2_NBFS _DLCBCR2.Bits.NBFS
#define DLCBCR2_RX4XE _DLCBCR2.Bits.RX4XE
#define DLCBCR2_DLOOP _DLCBCR2.Bits.DLOOP
#define DLCBCR2_SMRST _DLCBCR2.Bits.SMRST
#define DLCBCR2_TMIFR _DLCBCR2.MergedBits.grpTMIFR


/*** DLCBDR - BDLC Data Register; 0x000000EB ***/
typedef union {
  byte Byte;
  struct {
    byte D0          :1;                                       /* Receive/Transmit Data Bit 0 */
    byte D1          :1;                                       /* Receive/Transmit Data Bit 1 */
    byte D2          :1;                                       /* Receive/Transmit Data Bit 2 */
    byte D3          :1;                                       /* Receive/Transmit Data Bit 3 */
    byte D4          :1;                                       /* Receive/Transmit Data Bit 4 */
    byte D5          :1;                                       /* Receive/Transmit Data Bit 5 */
    byte D6          :1;                                       /* Receive/Transmit Data Bit 6 */
    byte D7          :1;                                       /* Receive/Transmit Data Bit 7 */
  } Bits;
  struct {
    byte grpD    :8;
  } MergedBits;
} DLCBDRSTR;
extern volatile DLCBDRSTR _DLCBDR @(REG_BASE + 0x000000EB);
#define DLCBDR _DLCBDR.Byte
#define DLCBDR_D0 _DLCBDR.Bits.D0
#define DLCBDR_D1 _DLCBDR.Bits.D1
#define DLCBDR_D2 _DLCBDR.Bits.D2
#define DLCBDR_D3 _DLCBDR.Bits.D3
#define DLCBDR_D4 _DLCBDR.Bits.D4
#define DLCBDR_D5 _DLCBDR.Bits.D5
#define DLCBDR_D6 _DLCBDR.Bits.D6
#define DLCBDR_D7 _DLCBDR.Bits.D7
#define DLCBDR_D _DLCBDR.MergedBits.grpD


/*** DLCBARD - BDLC Analog Round Trip Delay Register; 0x000000EC ***/
typedef union {
  byte Byte;
  struct {
    byte BO0         :1;                                       /* BDLC Analog Roundtrip Delay Offset Field 0 */
    byte BO1         :1;                                       /* BDLC Analog Roundtrip Delay Offset Field 1 */
    byte BO2         :1;                                       /* BDLC Analog Roundtrip Delay Offset Field 2 */
    byte BO3         :1;                                       /* BDLC Analog Roundtrip Delay Offset Field 3 */
    byte             :1; 
    byte             :1; 
    byte RXPOL       :1;                                       /* Receive Pin Polarity */
    byte             :1; 
  } Bits;
  struct {
    byte grpBO   :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DLCBARDSTR;
extern volatile DLCBARDSTR _DLCBARD @(REG_BASE + 0x000000EC);
#define DLCBARD _DLCBARD.Byte
#define DLCBARD_BO0 _DLCBARD.Bits.BO0
#define DLCBARD_BO1 _DLCBARD.Bits.BO1
#define DLCBARD_BO2 _DLCBARD.Bits.BO2
#define DLCBARD_BO3 _DLCBARD.Bits.BO3
#define DLCBARD_RXPOL _DLCBARD.Bits.RXPOL
#define DLCBARD_BO _DLCBARD.MergedBits.grpBO


/*** DLCBRSR - BDLC Rate Select Register; 0x000000ED ***/
typedef union {
  byte Byte;
  struct {
    byte R0          :1;                                       /* Rate Select 0 */
    byte R1          :1;                                       /* Rate Select 1 */
    byte R2          :1;                                       /* Rate Select 2 */
    byte R3          :1;                                       /* Rate Select 3 */
    byte R4          :1;                                       /* Rate Select 4 */
    byte R5          :1;                                       /* Rate Select 5 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpR    :6;
    byte         :1;
    byte         :1;
  } MergedBits;
} DLCBRSRSTR;
extern volatile DLCBRSRSTR _DLCBRSR @(REG_BASE + 0x000000ED);
#define DLCBRSR _DLCBRSR.Byte
#define DLCBRSR_R0 _DLCBRSR.Bits.R0
#define DLCBRSR_R1 _DLCBRSR.Bits.R1
#define DLCBRSR_R2 _DLCBRSR.Bits.R2
#define DLCBRSR_R3 _DLCBRSR.Bits.R3
#define DLCBRSR_R4 _DLCBRSR.Bits.R4
#define DLCBRSR_R5 _DLCBRSR.Bits.R5
#define DLCBRSR_R _DLCBRSR.MergedBits.grpR


/*** DLCSCR - BDLC Control Register; 0x000000EE ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte BDLCE       :1;                                       /* BDLC Enable */
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} DLCSCRSTR;
extern volatile DLCSCRSTR _DLCSCR @(REG_BASE + 0x000000EE);
#define DLCSCR _DLCSCR.Byte
#define DLCSCR_BDLCE _DLCSCR.Bits.BDLCE


/*** SPI1CR1 - SPI 1 Control Register; 0x000000F0 ***/
typedef union {
  byte Byte;
  struct {
    byte LSBFE       :1;                                       /* SPI 1 LSB-First Enable */
    byte SSOE        :1;                                       /* Slave Select Output Enable */
    byte CPHA        :1;                                       /* SPI 1 Clock Phase Bit */
    byte CPOL        :1;                                       /* SPI 1 Clock Polarity Bit */
    byte MSTR        :1;                                       /* SPI 1 Master/Slave Mode Select Bit */
    byte SPTIE       :1;                                       /* SPI 1 Transmit Interrupt Enable */
    byte SPE         :1;                                       /* SPI 1 System Enable Bit */
    byte SPIE        :1;                                       /* SPI 1 Interrupt Enable Bit */
  } Bits;
} SPI1CR1STR;
extern volatile SPI1CR1STR _SPI1CR1 @(REG_BASE + 0x000000F0);
#define SPI1CR1 _SPI1CR1.Byte
#define SPI1CR1_LSBFE _SPI1CR1.Bits.LSBFE
#define SPI1CR1_SSOE _SPI1CR1.Bits.SSOE
#define SPI1CR1_CPHA _SPI1CR1.Bits.CPHA
#define SPI1CR1_CPOL _SPI1CR1.Bits.CPOL
#define SPI1CR1_MSTR _SPI1CR1.Bits.MSTR
#define SPI1CR1_SPTIE _SPI1CR1.Bits.SPTIE
#define SPI1CR1_SPE _SPI1CR1.Bits.SPE
#define SPI1CR1_SPIE _SPI1CR1.Bits.SPIE


/*** SPI1CR2 - SPI 1 Control Register 2; 0x000000F1 ***/
typedef union {
  byte Byte;
  struct {
    byte SPC0        :1;                                       /* Serial Pin Control Bit 0 */
    byte SPISWAI     :1;                                       /* SPI 1 Stop in Wait Mode Bit */
    byte             :1; 
    byte BIDIROE     :1;                                       /* Output enable in the Bidirectional mode of operation */
    byte MODFEN      :1;                                       /* Mode Fault Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SPI1CR2STR;
extern volatile SPI1CR2STR _SPI1CR2 @(REG_BASE + 0x000000F1);
#define SPI1CR2 _SPI1CR2.Byte
#define SPI1CR2_SPC0 _SPI1CR2.Bits.SPC0
#define SPI1CR2_SPISWAI _SPI1CR2.Bits.SPISWAI
#define SPI1CR2_BIDIROE _SPI1CR2.Bits.BIDIROE
#define SPI1CR2_MODFEN _SPI1CR2.Bits.MODFEN


/*** SPI1BR - SPI 1 Baud Rate Register; 0x000000F2 ***/
typedef union {
  byte Byte;
  struct {
    byte SPR0        :1;                                       /* SPI 1 Baud Rate Selection Bit 0 */
    byte SPR1        :1;                                       /* SPI 1 Baud Rate Selection Bit 1 */
    byte SPR2        :1;                                       /* SPI 1 Baud Rate Selection Bit 2 */
    byte             :1; 
    byte SPPR0       :1;                                       /* SPI 1 Baud Rate Preselection Bits 0 */
    byte SPPR1       :1;                                       /* SPI 1 Baud Rate Preselection Bits 1 */
    byte SPPR2       :1;                                       /* SPI 1 Baud Rate Preselection Bits 2 */
    byte             :1; 
  } Bits;
  struct {
    byte grpSPR  :3;
    byte         :1;
    byte grpSPPR :3;
    byte         :1;
  } MergedBits;
} SPI1BRSTR;
extern volatile SPI1BRSTR _SPI1BR @(REG_BASE + 0x000000F2);
#define SPI1BR _SPI1BR.Byte
#define SPI1BR_SPR0 _SPI1BR.Bits.SPR0
#define SPI1BR_SPR1 _SPI1BR.Bits.SPR1
#define SPI1BR_SPR2 _SPI1BR.Bits.SPR2
#define SPI1BR_SPPR0 _SPI1BR.Bits.SPPR0
#define SPI1BR_SPPR1 _SPI1BR.Bits.SPPR1
#define SPI1BR_SPPR2 _SPI1BR.Bits.SPPR2
#define SPI1BR_SPR _SPI1BR.MergedBits.grpSPR
#define SPI1BR_SPPR _SPI1BR.MergedBits.grpSPPR


/*** SPI1SR - SPI 1 Status Register; 0x000000F3 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte MODF        :1;                                       /* Mode Fault Flag */
    byte SPTEF       :1;                                       /* SPI 1 Transmit Empty Interrupt Flag */
    byte             :1; 
    byte SPIF        :1;                                       /* SPIF Receive Interrupt Flag */
  } Bits;
} SPI1SRSTR;
extern volatile SPI1SRSTR _SPI1SR @(REG_BASE + 0x000000F3);
#define SPI1SR _SPI1SR.Byte
#define SPI1SR_MODF _SPI1SR.Bits.MODF
#define SPI1SR_SPTEF _SPI1SR.Bits.SPTEF
#define SPI1SR_SPIF _SPI1SR.Bits.SPIF


/*** SPI1DR - SPI 1 Data Register; 0x000000F5 ***/
typedef union {
  byte Byte;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} SPI1DRSTR;
extern volatile SPI1DRSTR _SPI1DR @(REG_BASE + 0x000000F5);
#define SPI1DR _SPI1DR.Byte
#define SPI1DR_BIT _SPI1DR.MergedBits.grpBIT


/*** SPI2CR1 - SPI 2 Control Register; 0x000000F8 ***/
typedef union {
  byte Byte;
  struct {
    byte LSBFE       :1;                                       /* SPI 2 LSB-First Enable */
    byte SSOE        :1;                                       /* Slave Select Output Enable */
    byte CPHA        :1;                                       /* SPI 2 Clock Phase Bit */
    byte CPOL        :1;                                       /* SPI 2 Clock Polarity Bit */
    byte MSTR        :1;                                       /* SPI 2 Master/Slave Mode Select Bit */
    byte SPTIE       :1;                                       /* SPI 2 Transmit Interrupt Enable */
    byte SPE         :1;                                       /* SPI 2 System Enable Bit */
    byte SPIE        :1;                                       /* SPI 2 Interrupt Enable Bit */
  } Bits;
} SPI2CR1STR;
extern volatile SPI2CR1STR _SPI2CR1 @(REG_BASE + 0x000000F8);
#define SPI2CR1 _SPI2CR1.Byte
#define SPI2CR1_LSBFE _SPI2CR1.Bits.LSBFE
#define SPI2CR1_SSOE _SPI2CR1.Bits.SSOE
#define SPI2CR1_CPHA _SPI2CR1.Bits.CPHA
#define SPI2CR1_CPOL _SPI2CR1.Bits.CPOL
#define SPI2CR1_MSTR _SPI2CR1.Bits.MSTR
#define SPI2CR1_SPTIE _SPI2CR1.Bits.SPTIE
#define SPI2CR1_SPE _SPI2CR1.Bits.SPE
#define SPI2CR1_SPIE _SPI2CR1.Bits.SPIE


/*** SPI2CR2 - SPI 2 Control Register 2; 0x000000F9 ***/
typedef union {
  byte Byte;
  struct {
    byte SPC0        :1;                                       /* Serial Pin Control Bit 0 */
    byte SPISWAI     :1;                                       /* SPI 2 Stop in Wait Mode Bit */
    byte             :1; 
    byte BIDIROE     :1;                                       /* Output enable in the Bidirectional mode of operation */
    byte MODFEN      :1;                                       /* Mode Fault Enable Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} SPI2CR2STR;
extern volatile SPI2CR2STR _SPI2CR2 @(REG_BASE + 0x000000F9);
#define SPI2CR2 _SPI2CR2.Byte
#define SPI2CR2_SPC0 _SPI2CR2.Bits.SPC0
#define SPI2CR2_SPISWAI _SPI2CR2.Bits.SPISWAI
#define SPI2CR2_BIDIROE _SPI2CR2.Bits.BIDIROE
#define SPI2CR2_MODFEN _SPI2CR2.Bits.MODFEN


/*** SPI2BR - SPI 2 Baud Rate Register; 0x000000FA ***/
typedef union {
  byte Byte;
  struct {
    byte SPR0        :1;                                       /* SPI 2 Baud Rate Selection Bit 0 */
    byte SPR1        :1;                                       /* SPI 2 Baud Rate Selection Bit 1 */
    byte SPR2        :1;                                       /* SPI 2 Baud Rate Selection Bit 2 */
    byte             :1; 
    byte SPPR0       :1;                                       /* SPI 2 Baud Rate Preselection Bits 0 */
    byte SPPR1       :1;                                       /* SPI 2 Baud Rate Preselection Bits 1 */
    byte SPPR2       :1;                                       /* SPI 2 Baud Rate Preselection Bits 2 */
    byte             :1; 
  } Bits;
  struct {
    byte grpSPR  :3;
    byte         :1;
    byte grpSPPR :3;
    byte         :1;
  } MergedBits;
} SPI2BRSTR;
extern volatile SPI2BRSTR _SPI2BR @(REG_BASE + 0x000000FA);
#define SPI2BR _SPI2BR.Byte
#define SPI2BR_SPR0 _SPI2BR.Bits.SPR0
#define SPI2BR_SPR1 _SPI2BR.Bits.SPR1
#define SPI2BR_SPR2 _SPI2BR.Bits.SPR2
#define SPI2BR_SPPR0 _SPI2BR.Bits.SPPR0
#define SPI2BR_SPPR1 _SPI2BR.Bits.SPPR1
#define SPI2BR_SPPR2 _SPI2BR.Bits.SPPR2
#define SPI2BR_SPR _SPI2BR.MergedBits.grpSPR
#define SPI2BR_SPPR _SPI2BR.MergedBits.grpSPPR


/*** SPI2SR - SPI 2 Status Register; 0x000000FB ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte MODF        :1;                                       /* Mode Fault Flag */
    byte SPTEF       :1;                                       /* SPI 2 Transmit Empty Interrupt Flag */
    byte             :1; 
    byte SPIF        :1;                                       /* SPIF Receive Interrupt Flag */
  } Bits;
} SPI2SRSTR;
extern volatile SPI2SRSTR _SPI2SR @(REG_BASE + 0x000000FB);
#define SPI2SR _SPI2SR.Byte
#define SPI2SR_MODF _SPI2SR.Bits.MODF
#define SPI2SR_SPTEF _SPI2SR.Bits.SPTEF
#define SPI2SR_SPIF _SPI2SR.Bits.SPIF


/*** SPI2DR - SPI 2 Data Register; 0x000000FD ***/
typedef union {
  byte Byte;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} SPI2DRSTR;
extern volatile SPI2DRSTR _SPI2DR @(REG_BASE + 0x000000FD);
#define SPI2DR _SPI2DR.Byte
#define SPI2DR_BIT _SPI2DR.MergedBits.grpBIT


/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/
typedef union {
  byte Byte;
  struct {
    byte FDIV0       :1;                                       /* Flash Clock Divider Bit 0 */
    byte FDIV1       :1;                                       /* Flash Clock Divider Bit 1 */
    byte FDIV2       :1;                                       /* Flash Clock Divider Bit 2 */
    byte FDIV3       :1;                                       /* Flash Clock Divider Bit 3 */
    byte FDIV4       :1;                                       /* Flash Clock Divider Bit 4 */
    byte FDIV5       :1;                                       /* Flash Clock Divider Bit 5 */
    byte PRDIV8      :1;                                       /* Enable Prescaler by 8 */
    byte FDIVLD      :1;                                       /* Flash Clock Divider Loaded */
  } Bits;
  struct {
    byte grpFDIV :6;
    byte grpPRDIV_8 :1;
    byte         :1;
  } MergedBits;
} FCLKDIVSTR;
extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100);
#define FCLKDIV _FCLKDIV.Byte
#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0
#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1
#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2
#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3
#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4
#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5
#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8
#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD
#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV


/*** FSEC - Flash Security Register; 0x00000101 ***/
typedef union {
  byte Byte;
  struct {
    byte SEC0        :1;                                       /* Memory security bit 0 */
    byte SEC1        :1;                                       /* Memory security bit 1 */
    byte NV2         :1;                                       /* Non Volatile flag bit 2 */
    byte NV3         :1;                                       /* Non Volatile flag bit 3 */
    byte NV4         :1;                                       /* Non Volatile flag bit 4 */
    byte NV5         :1;                                       /* Non Volatile flag bit 5 */
    byte NV6         :1;                                       /* Non Volatile flag bit 6 */
    byte KEYEN       :1;                                       /* Enable backdoor key to security */
  } Bits;
  struct {
    byte grpSEC  :2;
    byte grpNV_2 :5;
    byte         :1;
  } MergedBits;
} FSECSTR;
extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101);
#define FSEC _FSEC.Byte
#define FSEC_SEC0 _FSEC.Bits.SEC0
#define FSEC_SEC1 _FSEC.Bits.SEC1
#define FSEC_NV2 _FSEC.Bits.NV2
#define FSEC_NV3 _FSEC.Bits.NV3
#define FSEC_NV4 _FSEC.Bits.NV4
#define FSEC_NV5 _FSEC.Bits.NV5
#define FSEC_NV6 _FSEC.Bits.NV6
#define FSEC_KEYEN _FSEC.Bits.KEYEN
#define FSEC_SEC _FSEC.MergedBits.grpSEC
#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2
#define FSEC_NV FSEC_NV_2


/*** FCNFG - Flash Configuration Register; 0x00000103 ***/
typedef union {
  byte Byte;
  struct {
    byte BKSEL0      :1;                                       /* Register bank select 0 */
    byte BKSEL1      :1;                                       /* Register bank select 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte KEYACC      :1;                                       /* Enable Security Key Writing */
    byte CCIE        :1;                                       /* Command Complete Interrupt Enable */
    byte CBEIE       :1;                                       /* Command Buffers Empty Interrupt Enable */
  } Bits;
  struct {
    byte grpBKSEL :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} FCNFGSTR;
extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103);
#define FCNFG _FCNFG.Byte
#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0
#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1
#define FCNFG_KEYACC _FCNFG.Bits.KEYACC
#define FCNFG_CCIE _FCNFG.Bits.CCIE
#define FCNFG_CBEIE _FCNFG.Bits.CBEIE
#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL


/*** FPROT - Flash Protection Register; 0x00000104 ***/
typedef union {
  byte Byte;
  struct {
    byte FPLS0       :1;                                       /* Flash Protection Lower Address size 0 */
    byte FPLS1       :1;                                       /* Flash Protection Lower Address size 1 */
    byte FPLDIS      :1;                                       /* Flash Protection Lower address range disable */
    byte FPHS0       :1;                                       /* Flash Protection Higher address size 0 */
    byte FPHS1       :1;                                       /* Flash Protection Higher address size 1 */
    byte FPHDIS      :1;                                       /* Flash Protection Higher address range disable */
    byte NV6         :1;                                       /* Non Volatile Flag Bit */
    byte FPOPEN      :1;                                       /* Opens the flash block or subsections of it for program or erase */
  } Bits;
  struct {
    byte grpFPLS :2;
    byte         :1;
    byte grpFPHS :2;
    byte         :1;
    byte grpNV_6 :1;
    byte         :1;
  } MergedBits;
} FPROTSTR;
extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104);
#define FPROT _FPROT.Byte
#define FPROT_FPLS0 _FPROT.Bits.FPLS0
#define FPROT_FPLS1 _FPROT.Bits.FPLS1
#define FPROT_FPLDIS _FPROT.Bits.FPLDIS
#define FPROT_FPHS0 _FPROT.Bits.FPHS0
#define FPROT_FPHS1 _FPROT.Bits.FPHS1
#define FPROT_FPHDIS _FPROT.Bits.FPHDIS
#define FPROT_NV6 _FPROT.Bits.NV6
#define FPROT_FPOPEN _FPROT.Bits.FPOPEN
#define FPROT_FPLS _FPROT.MergedBits.grpFPLS
#define FPROT_FPHS _FPROT.MergedBits.grpFPHS


/*** FSTAT - Flash Status Register; 0x00000105 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte BLANK       :1;                                       /* Blank Verify Flag */
    byte             :1; 
    byte ACCERR      :1;                                       /* Access error */
    byte PVIOL       :1;                                       /* Protection violation */
    byte CCIF        :1;                                       /* Command Complete Interrupt Flag */
    byte CBEIF       :1;                                       /* Command Buffers Empty Interrupt Flag */
  } Bits;
} FSTATSTR;
extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105);
#define FSTAT _FSTAT.Byte
#define FSTAT_BLANK _FSTAT.Bits.BLANK
#define FSTAT_ACCERR _FSTAT.Bits.ACCERR
#define FSTAT_PVIOL _FSTAT.Bits.PVIOL
#define FSTAT_CCIF _FSTAT.Bits.CCIF
#define FSTAT_CBEIF _FSTAT.Bits.CBEIF


/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/
typedef union {
  byte Byte;
  struct {
    byte CMDB0       :1;                                       /* NVM User Mode Command Bit 0 */
    byte             :1; 
    byte CMDB2       :1;                                       /* NVM User Mode Command Bit 2 */
    byte             :1; 
    byte             :1; 
    byte CMDB5       :1;                                       /* NVM User Mode Command Bit 5 */
    byte CMDB6       :1;                                       /* NVM User Mode Command Bit 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpCMDB :1;
    byte         :1;
    byte grpCMDB_2 :1;
    byte         :1;
    byte         :1;
    byte grpCMDB_5 :2;
    byte         :1;
  } MergedBits;
} FCMDSTR;
extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106);
#define FCMD _FCMD.Byte
#define FCMD_CMDB0 _FCMD.Bits.CMDB0
#define FCMD_CMDB2 _FCMD.Bits.CMDB2
#define FCMD_CMDB5 _FCMD.Bits.CMDB5
#define FCMD_CMDB6 _FCMD.Bits.CMDB6
#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5
#define FCMD_CMDB FCMD_CMDB_5


/*** ECLKDIV - EEPROM Clock Divider Register; 0x00000110 ***/
typedef union {
  byte Byte;
  struct {
    byte EDIV0       :1;                                       /* EEPROM Clock Divider 0 */
    byte EDIV1       :1;                                       /* EEPROM Clock Divider 1 */
    byte EDIV2       :1;                                       /* EEPROM Clock Divider 2 */
    byte EDIV3       :1;                                       /* EEPROM Clock Divider 3 */
    byte EDIV4       :1;                                       /* EEPROM Clock Divider 4 */
    byte EDIV5       :1;                                       /* EEPROM Clock Divider 5 */
    byte PRDIV8      :1;                                       /* Enable Prescaler by 8 */
    byte EDIVLD      :1;                                       /* EEPROM Clock Divider Loaded */
  } Bits;
  struct {
    byte grpEDIV :6;
    byte grpPRDIV_8 :1;
    byte         :1;
  } MergedBits;
} ECLKDIVSTR;
extern volatile ECLKDIVSTR _ECLKDIV @(REG_BASE + 0x00000110);
#define ECLKDIV _ECLKDIV.Byte
#define ECLKDIV_EDIV0 _ECLKDIV.Bits.EDIV0
#define ECLKDIV_EDIV1 _ECLKDIV.Bits.EDIV1
#define ECLKDIV_EDIV2 _ECLKDIV.Bits.EDIV2
#define ECLKDIV_EDIV3 _ECLKDIV.Bits.EDIV3
#define ECLKDIV_EDIV4 _ECLKDIV.Bits.EDIV4
#define ECLKDIV_EDIV5 _ECLKDIV.Bits.EDIV5
#define ECLKDIV_PRDIV8 _ECLKDIV.Bits.PRDIV8
#define ECLKDIV_EDIVLD _ECLKDIV.Bits.EDIVLD
#define ECLKDIV_EDIV _ECLKDIV.MergedBits.grpEDIV


/*** ECNFG - EEPROM Configuration Register; 0x00000113 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte CCIE        :1;                                       /* Command Complete Interrupt Enable */
    byte CBEIE       :1;                                       /* Command Buffers Empty Interrupt Enable */
  } Bits;
} ECNFGSTR;
extern volatile ECNFGSTR _ECNFG @(REG_BASE + 0x00000113);
#define ECNFG _ECNFG.Byte
#define ECNFG_CCIE _ECNFG.Bits.CCIE
#define ECNFG_CBEIE _ECNFG.Bits.CBEIE


/*** EPROT - EEPROM Protection Register; 0x00000114 ***/
typedef union {
  byte Byte;
  struct {
    byte EP0         :1;                                       /* EEPROM Protection address size 0 */
    byte EP1         :1;                                       /* EEPROM Protection address size 1 */
    byte EP2         :1;                                       /* EEPROM Protection address size 2 */
    byte EPDIS       :1;                                       /* EEPROM Protection disable */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte EPOPEN      :1;                                       /* Opens the EEPROM block or a subsection of it for program or erase */
  } Bits;
  struct {
    byte grpEP   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} EPROTSTR;
extern volatile EPROTSTR _EPROT @(REG_BASE + 0x00000114);
#define EPROT _EPROT.Byte
#define EPROT_EP0 _EPROT.Bits.EP0
#define EPROT_EP1 _EPROT.Bits.EP1
#define EPROT_EP2 _EPROT.Bits.EP2
#define EPROT_EPDIS _EPROT.Bits.EPDIS
#define EPROT_EPOPEN _EPROT.Bits.EPOPEN
#define EPROT_EP _EPROT.MergedBits.grpEP


/*** ESTAT - EEPROM Status Register; 0x00000115 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte BLANK       :1;                                       /* Blank Verify Flag */
    byte             :1; 
    byte ACCERR      :1;                                       /* Access error */
    byte PVIOL       :1;                                       /* Protection violation */
    byte CCIF        :1;                                       /* Command Complete Interrupt Flag */
    byte CBEIF       :1;                                       /* Command Buffer Empty Interrupt Flag */
  } Bits;
} ESTATSTR;
extern volatile ESTATSTR _ESTAT @(REG_BASE + 0x00000115);
#define ESTAT _ESTAT.Byte
#define ESTAT_BLANK _ESTAT.Bits.BLANK
#define ESTAT_ACCERR _ESTAT.Bits.ACCERR
#define ESTAT_PVIOL _ESTAT.Bits.PVIOL
#define ESTAT_CCIF _ESTAT.Bits.CCIF
#define ESTAT_CBEIF _ESTAT.Bits.CBEIF


/*** ECMD - EEPROM Command Buffer and Register; 0x00000116 ***/
typedef union {
  byte Byte;
  struct {
    byte CMDB0       :1;                                       /* EEPROM User Mode Command 0 */
    byte             :1; 
    byte CMDB2       :1;                                       /* EEPROM User Mode Command 2 */
    byte             :1; 
    byte             :1; 
    byte CMDB5       :1;                                       /* EEPROM User Mode Command 5 */
    byte CMDB6       :1;                                       /* EEPROM User Mode Command 6 */
    byte             :1; 
  } Bits;
  struct {
    byte grpCMDB :1;
    byte         :1;
    byte grpCMDB_2 :1;
    byte         :1;
    byte         :1;
    byte grpCMDB_5 :2;
    byte         :1;
  } MergedBits;
} ECMDSTR;
extern volatile ECMDSTR _ECMD @(REG_BASE + 0x00000116);
#define ECMD _ECMD.Byte
#define ECMD_CMDB0 _ECMD.Bits.CMDB0
#define ECMD_CMDB2 _ECMD.Bits.CMDB2
#define ECMD_CMDB5 _ECMD.Bits.CMDB5
#define ECMD_CMDB6 _ECMD.Bits.CMDB6
#define ECMD_CMDB_5 _ECMD.MergedBits.grpCMDB_5
#define ECMD_CMDB ECMD_CMDB_5


/*** ATD1STAT0 - ATD 1 Status Register 0; 0x00000126 ***/
typedef union {
  byte Byte;
  struct {
    byte CC0         :1;                                       /* Conversion Counter 0 */
    byte CC1         :1;                                       /* Conversion Counter 1 */
    byte CC2         :1;                                       /* Conversion Counter 2 */
    byte             :1; 
    byte FIFOR       :1;                                       /* FIFO Over Run Flag */
    byte ETORF       :1;                                       /* External Trigger Overrun Flag */
    byte             :1; 
    byte SCF         :1;                                       /* Sequence Complete Flag */
  } Bits;
  struct {
    byte grpCC   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} ATD1STAT0STR;
extern volatile ATD1STAT0STR _ATD1STAT0 @(REG_BASE + 0x00000126);
#define ATD1STAT0 _ATD1STAT0.Byte
#define ATD1STAT0_CC0 _ATD1STAT0.Bits.CC0
#define ATD1STAT0_CC1 _ATD1STAT0.Bits.CC1
#define ATD1STAT0_CC2 _ATD1STAT0.Bits.CC2
#define ATD1STAT0_FIFOR _ATD1STAT0.Bits.FIFOR
#define ATD1STAT0_ETORF _ATD1STAT0.Bits.ETORF
#define ATD1STAT0_SCF _ATD1STAT0.Bits.SCF
#define ATD1STAT0_CC _ATD1STAT0.MergedBits.grpCC


/*** ATD1STAT1 - ATD 1 Status Register 1; 0x0000012B ***/
typedef union {
  byte Byte;
  struct {
    byte CCF0        :1;                                       /* Conversion Complete Flag 0 */
    byte CCF1        :1;                                       /* Conversion Complete Flag 1 */
    byte CCF2        :1;                                       /* Conversion Complete Flag 2 */
    byte CCF3        :1;                                       /* Conversion Complete Flag 3 */
    byte CCF4        :1;                                       /* Conversion Complete Flag 4 */
    byte CCF5        :1;                                       /* Conversion Complete Flag 5 */
    byte CCF6        :1;                                       /* Conversion Complete Flag 6 */
    byte CCF7        :1;                                       /* Conversion Complete Flag 7 */
  } Bits;
  struct {
    byte grpCCF  :8;
  } MergedBits;
} ATD1STAT1STR;
extern volatile ATD1STAT1STR _ATD1STAT1 @(REG_BASE + 0x0000012B);
#define ATD1STAT1 _ATD1STAT1.Byte
#define ATD1STAT1_CCF0 _ATD1STAT1.Bits.CCF0
#define ATD1STAT1_CCF1 _ATD1STAT1.Bits.CCF1
#define ATD1STAT1_CCF2 _ATD1STAT1.Bits.CCF2
#define ATD1STAT1_CCF3 _ATD1STAT1.Bits.CCF3
#define ATD1STAT1_CCF4 _ATD1STAT1.Bits.CCF4
#define ATD1STAT1_CCF5 _ATD1STAT1.Bits.CCF5
#define ATD1STAT1_CCF6 _ATD1STAT1.Bits.CCF6
#define ATD1STAT1_CCF7 _ATD1STAT1.Bits.CCF7
#define ATD1STAT1_CCF _ATD1STAT1.MergedBits.grpCCF


/*** ATD1DIEN - ATD 1 Input Enable Mask Register; 0x0000012D ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* Disable/Enable Digital Input Buffer Bit 0 */
    byte BIT1        :1;                                       /* Disable/Enable Digital Input Buffer Bit 1 */
    byte BIT2        :1;                                       /* Disable/Enable Digital Input Buffer Bit 2 */
    byte BIT3        :1;                                       /* Disable/Enable Digital Input Buffer Bit 3 */
    byte BIT4        :1;                                       /* Disable/Enable Digital Input Buffer Bit 4 */
    byte BIT5        :1;                                       /* Disable/Enable Digital Input Buffer Bit 5 */
    byte BIT6        :1;                                       /* Disable/Enable Digital Input Buffer Bit 6 */
    byte BIT7        :1;                                       /* Disable/Enable Digital Input Buffer Bit 7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} ATD1DIENSTR;
extern volatile ATD1DIENSTR _ATD1DIEN @(REG_BASE + 0x0000012D);
#define ATD1DIEN _ATD1DIEN.Byte
#define ATD1DIEN_BIT0 _ATD1DIEN.Bits.BIT0
#define ATD1DIEN_BIT1 _ATD1DIEN.Bits.BIT1
#define ATD1DIEN_BIT2 _ATD1DIEN.Bits.BIT2
#define ATD1DIEN_BIT3 _ATD1DIEN.Bits.BIT3
#define ATD1DIEN_BIT4 _ATD1DIEN.Bits.BIT4
#define ATD1DIEN_BIT5 _ATD1DIEN.Bits.BIT5
#define ATD1DIEN_BIT6 _ATD1DIEN.Bits.BIT6
#define ATD1DIEN_BIT7 _ATD1DIEN.Bits.BIT7
#define ATD1DIEN_BIT _ATD1DIEN.MergedBits.grpBIT


/*** PORTAD1 - Port AD1 Register; 0x0000012F ***/
typedef union {
  byte Byte;
  struct {
    byte BIT0        :1;                                       /* AN0 */
    byte BIT1        :1;                                       /* AN1 */
    byte BIT2        :1;                                       /* AN2 */
    byte BIT3        :1;                                       /* AN3 */
    byte BIT4        :1;                                       /* AN4 */
    byte BIT5        :1;                                       /* AN5 */
    byte BIT6        :1;                                       /* AN6 */
    byte BIT7        :1;                                       /* AN7 */
  } Bits;
  struct {
    byte grpBIT  :8;
  } MergedBits;
} PORTAD1STR;
extern volatile PORTAD1STR _PORTAD1 @(REG_BASE + 0x0000012F);
#define PORTAD1 _PORTAD1.Byte
#define PORTAD1_BIT0 _PORTAD1.Bits.BIT0
#define PORTAD1_BIT1 _PORTAD1.Bits.BIT1
#define PORTAD1_BIT2 _PORTAD1.Bits.BIT2
#define PORTAD1_BIT3 _PORTAD1.Bits.BIT3
#define PORTAD1_BIT4 _PORTAD1.Bits.BIT4
#define PORTAD1_BIT5 _PORTAD1.Bits.BIT5
#define PORTAD1_BIT6 _PORTAD1.Bits.BIT6
#define PORTAD1_BIT7 _PORTAD1.Bits.BIT7
#define PORTAD1_BIT _PORTAD1.MergedBits.grpBIT


/*** CAN0CTL0 - MSCAN 0 Control 0 Register; 0x00000140 ***/
typedef union {
  byte Byte;
  struct {
    byte INITRQ      :1;                                       /* Initialization Mode Request */
    byte SLPRQ       :1;                                       /* Sleep Mode Request */
    byte WUPE        :1;                                       /* Wake-Up Enable */
    byte TIME        :1;                                       /* Timer Enable */
    byte SYNCH       :1;                                       /* Synchronized Status */
    byte CSWAI       :1;                                       /* CAN Stops in Wait Mode */
    byte RXACT       :1;                                       /* Receiver Active Status */
    byte RXFRM       :1;                                       /* Received Frame Flag */
  } Bits;
} CAN0CTL0STR;
extern volatile CAN0CTL0STR _CAN0CTL0 @(REG_BASE + 0x00000140);
#define CAN0CTL0 _CAN0CTL0.Byte
#define CAN0CTL0_INITRQ _CAN0CTL0.Bits.INITRQ
#define CAN0CTL0_SLPRQ _CAN0CTL0.Bits.SLPRQ
#define CAN0CTL0_WUPE _CAN0CTL0.Bits.WUPE
#define CAN0CTL0_TIME _CAN0CTL0.Bits.TIME
#define CAN0CTL0_SYNCH _CAN0CTL0.Bits.SYNCH
#define CAN0CTL0_CSWAI _CAN0CTL0.Bits.CSWAI
#define CAN0CTL0_RXACT _CAN0CTL0.Bits.RXACT
#define CAN0CTL0_RXFRM _CAN0CTL0.Bits.RXFRM


/*** CAN0CTL1 - MSCAN 0 Control 1 Register; 0x00000141 ***/
typedef union {
  byte Byte;
  struct {
    byte INITAK      :1;                                       /* Initialization Mode Acknowledge */
    byte SLPAK       :1;                                       /* Sleep Mode Acknowledge */
    byte WUPM        :1;                                       /* Wake-Up Mode */
    byte             :1; 
    byte LISTEN      :1;                                       /* Listen Only Mode */
    byte LOOPB       :1;                                       /* Loop Back Self Test Mode */
    byte CLKSRC      :1;                                       /* MSCAN 0 Clock Source */
    byte CANE        :1;                                       /* MSCAN 0 Enable */
  } Bits;
} CAN0CTL1STR;
extern volatile CAN0CTL1STR _CAN0CTL1 @(REG_BASE + 0x00000141);
#define CAN0CTL1 _CAN0CTL1.Byte
#define CAN0CTL1_INITAK _CAN0CTL1.Bits.INITAK
#define CAN0CTL1_SLPAK _CAN0CTL1.Bits.SLPAK
#define CAN0CTL1_WUPM _CAN0CTL1.Bits.WUPM
#define CAN0CTL1_LISTEN _CAN0CTL1.Bits.LISTEN
#define CAN0CTL1_LOOPB _CAN0CTL1.Bits.LOOPB
#define CAN0CTL1_CLKSRC _CAN0CTL1.Bits.CLKSRC
#define CAN0CTL1_CANE _CAN0CTL1.Bits.CANE


/*** CAN0BTR0 - MSCAN 0 Bus Timing Register 0; 0x00000142 ***/
typedef union {
  byte Byte;
  struct {
    byte BRP0        :1;                                       /* Baud Rate Prescaler 0 */
    byte BRP1        :1;                                       /* Baud Rate Prescaler 1 */
    byte BRP2        :1;                                       /* Baud Rate Prescaler 2 */
    byte BRP3        :1;                                       /* Baud Rate Prescaler 3 */
    byte BRP4        :1;                                       /* Baud Rate Prescaler 4 */
    byte BRP5        :1;                                       /* Baud Rate Prescaler 5 */
    byte SJW0        :1;                                       /* Synchronization Jump Width 0 */
    byte SJW1        :1;                                       /* Synchronization Jump Width 1 */
  } Bits;
  struct {
    byte grpBRP  :6;
    byte grpSJW  :2;
  } MergedBits;
} CAN0BTR0STR;
extern volatile CAN0BTR0STR _CAN0BTR0 @(REG_BASE + 0x00000142);
#define CAN0BTR0 _CAN0BTR0.Byte
#define CAN0BTR0_BRP0 _CAN0BTR0.Bits.BRP0
#define CAN0BTR0_BRP1 _CAN0BTR0.Bits.BRP1
#define CAN0BTR0_BRP2 _CAN0BTR0.Bits.BRP2
#define CAN0BTR0_BRP3 _CAN0BTR0.Bits.BRP3
#define CAN0BTR0_BRP4 _CAN0BTR0.Bits.BRP4
#define CAN0BTR0_BRP5 _CAN0BTR0.Bits.BRP5
#define CAN0BTR0_SJW0 _CAN0BTR0.Bits.SJW0
#define CAN0BTR0_SJW1 _CAN0BTR0.Bits.SJW1
#define CAN0BTR0_BRP _CAN0BTR0.MergedBits.grpBRP
#define CAN0BTR0_SJW _CAN0BTR0.MergedBits.grpSJW


/*** CAN0BTR1 - MSCAN 0 Bus Timing Register 1; 0x00000143 ***/
typedef union {
  byte Byte;
  struct {
    byte TSEG10      :1;                                       /* Time Segment 1 */
    byte TSEG11      :1;                                       /* Time Segment 1 */
    byte TSEG12      :1;                                       /* Time Segment 1 */
    byte TSEG13      :1;                                       /* Time Segment 1 */
    byte TSEG20      :1;                                       /* Time Segment 2 */
    byte TSEG21      :1;                                       /* Time Segment 2 */
    byte TSEG22      :1;                                       /* Time Segment 2 */
    byte SAMP        :1;                                       /* Sampling */
  } Bits;
  struct {
    byte grpTSEG_10 :4;
    byte grpTSEG_20 :3;
    byte         :1;
  } MergedBits;
} CAN0BTR1STR;
extern volatile CAN0BTR1STR _CAN0BTR1 @(REG_BASE + 0x00000143);
#define CAN0BTR1 _CAN0BTR1.Byte
#define CAN0BTR1_TSEG10 _CAN0BTR1.Bits.TSEG10
#define CAN0BTR1_TSEG11 _CAN0BTR1.Bits.TSEG11
#define CAN0BTR1_TSEG12 _CAN0BTR1.Bits.TSEG12
#define CAN0BTR1_TSEG13 _CAN0BTR1.Bits.TSEG13
#define CAN0BTR1_TSEG20 _CAN0BTR1.Bits.TSEG20
#define CAN0BTR1_TSEG21 _CAN0BTR1.Bits.TSEG21
#define CAN0BTR1_TSEG22 _CAN0BTR1.Bits.TSEG22
#define CAN0BTR1_SAMP _CAN0BTR1.Bits.SAMP
#define CAN0BTR1_TSEG_10 _CAN0BTR1.MergedBits.grpTSEG_10
#define CAN0BTR1_TSEG_20 _CAN0BTR1.MergedBits.grpTSEG_20
#define CAN0BTR1_TSEG CAN0BTR1_TSEG_10


/*** CAN0RFLG - MSCAN 0 Receiver Flag Register; 0x00000144 ***/
typedef union {
  byte Byte;
  struct {
    byte RXF         :1;                                       /* Receive Buffer Full */
    byte OVRIF       :1;                                       /* Overrun Interrupt Flag */
    byte TSTAT0      :1;                                       /* Transmitter Status Bit 0 */
    byte TSTAT1      :1;                                       /* Transmitter Status Bit 1 */
    byte RSTAT0      :1;                                       /* Receiver Status Bit 0 */
    byte RSTAT1      :1;                                       /* Receiver Status Bit 1 */
    byte CSCIF       :1;                                       /* CAN Status Change Interrupt Flag */
    byte WUPIF       :1;                                       /* Wake-up Interrupt Flag */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpTSTAT :2;
    byte grpRSTAT :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN0RFLGSTR;
extern volatile CAN0RFLGSTR _CAN0RFLG @(REG_BASE + 0x00000144);
#define CAN0RFLG _CAN0RFLG.Byte
#define CAN0RFLG_RXF _CAN0RFLG.Bits.RXF
#define CAN0RFLG_OVRIF _CAN0RFLG.Bits.OVRIF
#define CAN0RFLG_TSTAT0 _CAN0RFLG.Bits.TSTAT0
#define CAN0RFLG_TSTAT1 _CAN0RFLG.Bits.TSTAT1
#define CAN0RFLG_RSTAT0 _CAN0RFLG.Bits.RSTAT0
#define CAN0RFLG_RSTAT1 _CAN0RFLG.Bits.RSTAT1
#define CAN0RFLG_CSCIF _CAN0RFLG.Bits.CSCIF
#define CAN0RFLG_WUPIF _CAN0RFLG.Bits.WUPIF
#define CAN0RFLG_TSTAT _CAN0RFLG.MergedBits.grpTSTAT
#define CAN0RFLG_RSTAT _CAN0RFLG.MergedBits.grpRSTAT


/*** CAN0RIER - MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 ***/
typedef union {
  byte Byte;
  struct {
    byte RXFIE       :1;                                       /* Receiver Full Interrupt Enable */
    byte OVRIE       :1;                                       /* Overrun Interrupt Enable */
    byte TSTATE0     :1;                                       /* Transmitter Status Change Enable 0 */
    byte TSTATE1     :1;                                       /* Transmitter Status Change Enable 1 */
    byte RSTATE0     :1;                                       /* Receiver Status Change Enable 0 */
    byte RSTATE1     :1;                                       /* Receiver Status Change Enable 1 */
    byte CSCIE       :1;                                       /* CAN Status Change Interrupt Enable */
    byte WUPIE       :1;                                       /* Wake-up Interrupt Enable */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpTSTATE :2;
    byte grpRSTATE :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN0RIERSTR;
extern volatile CAN0RIERSTR _CAN0RIER @(REG_BASE + 0x00000145);
#define CAN0RIER _CAN0RIER.Byte
#define CAN0RIER_RXFIE _CAN0RIER.Bits.RXFIE
#define CAN0RIER_OVRIE _CAN0RIER.Bits.OVRIE
#define CAN0RIER_TSTATE0 _CAN0RIER.Bits.TSTATE0
#define CAN0RIER_TSTATE1 _CAN0RIER.Bits.TSTATE1
#define CAN0RIER_RSTATE0 _CAN0RIER.Bits.RSTATE0
#define CAN0RIER_RSTATE1 _CAN0RIER.Bits.RSTATE1
#define CAN0RIER_CSCIE _CAN0RIER.Bits.CSCIE
#define CAN0RIER_WUPIE _CAN0RIER.Bits.WUPIE
#define CAN0RIER_TSTATE _CAN0RIER.MergedBits.grpTSTATE
#define CAN0RIER_RSTATE _CAN0RIER.MergedBits.grpRSTATE


/*** CAN0TFLG - MSCAN 0 Transmitter Flag Register; 0x00000146 ***/
typedef union {
  byte Byte;
  struct {
    byte TXE0        :1;                                       /* Transmitter Buffer Empty 0 */
    byte TXE1        :1;                                       /* Transmitter Buffer Empty 1 */
    byte TXE2        :1;                                       /* Transmitter Buffer Empty 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTXE  :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN0TFLGSTR;
extern volatile CAN0TFLGSTR _CAN0TFLG @(REG_BASE + 0x00000146);
#define CAN0TFLG _CAN0TFLG.Byte
#define CAN0TFLG_TXE0 _CAN0TFLG.Bits.TXE0
#define CAN0TFLG_TXE1 _CAN0TFLG.Bits.TXE1
#define CAN0TFLG_TXE2 _CAN0TFLG.Bits.TXE2
#define CAN0TFLG_TXE _CAN0TFLG.MergedBits.grpTXE


/*** CAN0TIER - MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 ***/
typedef union {
  byte Byte;
  struct {
    byte TXEIE0      :1;                                       /* Transmitter Empty Interrupt Enable 0 */
    byte TXEIE1      :1;                                       /* Transmitter Empty Interrupt Enable 1 */
    byte TXEIE2      :1;                                       /* Transmitter Empty Interrupt Enable 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTXEIE :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN0TIERSTR;
extern volatile CAN0TIERSTR _CAN0TIER @(REG_BASE + 0x00000147);
#define CAN0TIER _CAN0TIER.Byte
#define CAN0TIER_TXEIE0 _CAN0TIER.Bits.TXEIE0
#define CAN0TIER_TXEIE1 _CAN0TIER.Bits.TXEIE1
#define CAN0TIER_TXEIE2 _CAN0TIER.Bits.TXEIE2
#define CAN0TIER_TXEIE _CAN0TIER.MergedBits.grpTXEIE


/*** CAN0TARQ - MSCAN 0 Transmitter Message Abort Request; 0x00000148 ***/
typedef union {
  byte Byte;
  struct {
    byte ABTRQ0      :1;                                       /* Abort Request 0 */
    byte ABTRQ1      :1;                                       /* Abort Request 1 */
    byte ABTRQ2      :1;                                       /* Abort Request 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpABTRQ :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN0TARQSTR;
extern volatile CAN0TARQSTR _CAN0TARQ @(REG_BASE + 0x00000148);
#define CAN0TARQ _CAN0TARQ.Byte
#define CAN0TARQ_ABTRQ0 _CAN0TARQ.Bits.ABTRQ0
#define CAN0TARQ_ABTRQ1 _CAN0TARQ.Bits.ABTRQ1
#define CAN0TARQ_ABTRQ2 _CAN0TARQ.Bits.ABTRQ2
#define CAN0TARQ_ABTRQ _CAN0TARQ.MergedBits.grpABTRQ


/*** CAN0TAAK - MSCAN 0 Transmitter Message Abort Control; 0x00000149 ***/
typedef union {
  byte Byte;
  struct {
    byte ABTAK0      :1;                                       /* Abort Acknowledge 0 */
    byte ABTAK1      :1;                                       /* Abort Acknowledge 1 */
    byte ABTAK2      :1;                                       /* Abort Acknowledge 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpABTAK :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN0TAAKSTR;
extern volatile CAN0TAAKSTR _CAN0TAAK @(REG_BASE + 0x00000149);
#define CAN0TAAK _CAN0TAAK.Byte
#define CAN0TAAK_ABTAK0 _CAN0TAAK.Bits.ABTAK0
#define CAN0TAAK_ABTAK1 _CAN0TAAK.Bits.ABTAK1
#define CAN0TAAK_ABTAK2 _CAN0TAAK.Bits.ABTAK2
#define CAN0TAAK_ABTAK _CAN0TAAK.MergedBits.grpABTAK


/*** CAN0TBSEL - MSCAN 0 Transmit Buffer Selection; 0x0000014A ***/
typedef union {
  byte Byte;
  struct {
    byte TX0         :1;                                       /* Transmit Buffer Select 0 */
    byte TX1         :1;                                       /* Transmit Buffer Select 1 */
    byte TX2         :1;                                       /* Transmit Buffer Select 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTX   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN0TBSELSTR;
extern volatile CAN0TBSELSTR _CAN0TBSEL @(REG_BASE + 0x0000014A);
#define CAN0TBSEL _CAN0TBSEL.Byte
#define CAN0TBSEL_TX0 _CAN0TBSEL.Bits.TX0
#define CAN0TBSEL_TX1 _CAN0TBSEL.Bits.TX1
#define CAN0TBSEL_TX2 _CAN0TBSEL.Bits.TX2
#define CAN0TBSEL_TX _CAN0TBSEL.MergedBits.grpTX


/*** CAN0IDAC - MSCAN 0 Identifier Acceptance Control Register; 0x0000014B ***/
typedef union {
  byte Byte;
  struct {
    byte IDHIT0      :1;                                       /* Identifier Acceptance Hit Indicator 0 */
    byte IDHIT1      :1;                                       /* Identifier Acceptance Hit Indicator 1 */
    byte IDHIT2      :1;                                       /* Identifier Acceptance Hit Indicator 2 */
    byte             :1; 
    byte IDAM0       :1;                                       /* Identifier Acceptance Mode 0 */
    byte IDAM1       :1;                                       /* Identifier Acceptance Mode 1 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpIDHIT :3;
    byte         :1;
    byte grpIDAM :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN0IDACSTR;
extern volatile CAN0IDACSTR _CAN0IDAC @(REG_BASE + 0x0000014B);
#define CAN0IDAC _CAN0IDAC.Byte
#define CAN0IDAC_IDHIT0 _CAN0IDAC.Bits.IDHIT0
#define CAN0IDAC_IDHIT1 _CAN0IDAC.Bits.IDHIT1
#define CAN0IDAC_IDHIT2 _CAN0IDAC.Bits.IDHIT2
#define CAN0IDAC_IDAM0 _CAN0IDAC.Bits.IDAM0
#define CAN0IDAC_IDAM1 _CAN0IDAC.Bits.IDAM1
#define CAN0IDAC_IDHIT _CAN0IDAC.MergedBits.grpIDHIT
#define CAN0IDAC_IDAM _CAN0IDAC.MergedBits.grpIDAM


/*** CAN0RXERR - MSCAN 0 Receive Error Counter Register; 0x0000014E ***/
typedef union {
  byte Byte;
  struct {
    byte RXERR0      :1;                                       /* Bit 0 */
    byte RXERR1      :1;                                       /* Bit 1 */
    byte RXERR2      :1;                                       /* Bit 2 */
    byte RXERR3      :1;                                       /* Bit 3 */
    byte RXERR4      :1;                                       /* Bit 4 */
    byte RXERR5      :1;                                       /* Bit 5 */
    byte RXERR6      :1;                                       /* Bit 6 */
    byte RXERR7      :1;                                       /* Bit 7 */
  } Bits;
  struct {
    byte grpRXERR :8;
  } MergedBits;
} CAN0RXERRSTR;
extern volatile CAN0RXERRSTR _CAN0RXERR @(REG_BASE + 0x0000014E);
#define CAN0RXERR _CAN0RXERR.Byte
#define CAN0RXERR_RXERR0 _CAN0RXERR.Bits.RXERR0
#define CAN0RXERR_RXERR1 _CAN0RXERR.Bits.RXERR1
#define CAN0RXERR_RXERR2 _CAN0RXERR.Bits.RXERR2
#define CAN0RXERR_RXERR3 _CAN0RXERR.Bits.RXERR3
#define CAN0RXERR_RXERR4 _CAN0RXERR.Bits.RXERR4
#define CAN0RXERR_RXERR5 _CAN0RXERR.Bits.RXERR5
#define CAN0RXERR_RXERR6 _CAN0RXERR.Bits.RXERR6
#define CAN0RXERR_RXERR7 _CAN0RXERR.Bits.RXERR7
#define CAN0RXERR_RXERR _CAN0RXERR.MergedBits.grpRXERR


/*** CAN0TXERR - MSCAN 0 Transmit Error Counter Register; 0x0000014F ***/
typedef union {
  byte Byte;
  struct {
    byte TXERR0      :1;                                       /* Bit 0 */
    byte TXERR1      :1;                                       /* Bit 1 */
    byte TXERR2      :1;                                       /* Bit 2 */
    byte TXERR3      :1;                                       /* Bit 3 */
    byte TXERR4      :1;                                       /* Bit 4 */
    byte TXERR5      :1;                                       /* Bit 5 */
    byte TXERR6      :1;                                       /* Bit 6 */
    byte TXERR7      :1;                                       /* Bit 7 */
  } Bits;
  struct {
    byte grpTXERR :8;
  } MergedBits;
} CAN0TXERRSTR;
extern volatile CAN0TXERRSTR _CAN0TXERR @(REG_BASE + 0x0000014F);
#define CAN0TXERR _CAN0TXERR.Byte
#define CAN0TXERR_TXERR0 _CAN0TXERR.Bits.TXERR0
#define CAN0TXERR_TXERR1 _CAN0TXERR.Bits.TXERR1
#define CAN0TXERR_TXERR2 _CAN0TXERR.Bits.TXERR2
#define CAN0TXERR_TXERR3 _CAN0TXERR.Bits.TXERR3
#define CAN0TXERR_TXERR4 _CAN0TXERR.Bits.TXERR4
#define CAN0TXERR_TXERR5 _CAN0TXERR.Bits.TXERR5
#define CAN0TXERR_TXERR6 _CAN0TXERR.Bits.TXERR6
#define CAN0TXERR_TXERR7 _CAN0TXERR.Bits.TXERR7
#define CAN0TXERR_TXERR _CAN0TXERR.MergedBits.grpTXERR


/*** CAN0IDAR0 - MSCAN 0 Identifier Acceptance Register 0; 0x00000150 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN0IDAR0STR;
extern volatile CAN0IDAR0STR _CAN0IDAR0 @(REG_BASE + 0x00000150);
#define CAN0IDAR0 _CAN0IDAR0.Byte
#define CAN0IDAR0_AC0 _CAN0IDAR0.Bits.AC0
#define CAN0IDAR0_AC1 _CAN0IDAR0.Bits.AC1
#define CAN0IDAR0_AC2 _CAN0IDAR0.Bits.AC2
#define CAN0IDAR0_AC3 _CAN0IDAR0.Bits.AC3
#define CAN0IDAR0_AC4 _CAN0IDAR0.Bits.AC4
#define CAN0IDAR0_AC5 _CAN0IDAR0.Bits.AC5
#define CAN0IDAR0_AC6 _CAN0IDAR0.Bits.AC6
#define CAN0IDAR0_AC7 _CAN0IDAR0.Bits.AC7
#define CAN0IDAR0_AC _CAN0IDAR0.MergedBits.grpAC


/*** CAN0IDAR1 - MSCAN 0 Identifier Acceptance Register 1; 0x00000151 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN0IDAR1STR;
extern volatile CAN0IDAR1STR _CAN0IDAR1 @(REG_BASE + 0x00000151);
#define CAN0IDAR1 _CAN0IDAR1.Byte
#define CAN0IDAR1_AC0 _CAN0IDAR1.Bits.AC0
#define CAN0IDAR1_AC1 _CAN0IDAR1.Bits.AC1
#define CAN0IDAR1_AC2 _CAN0IDAR1.Bits.AC2
#define CAN0IDAR1_AC3 _CAN0IDAR1.Bits.AC3
#define CAN0IDAR1_AC4 _CAN0IDAR1.Bits.AC4
#define CAN0IDAR1_AC5 _CAN0IDAR1.Bits.AC5
#define CAN0IDAR1_AC6 _CAN0IDAR1.Bits.AC6
#define CAN0IDAR1_AC7 _CAN0IDAR1.Bits.AC7
#define CAN0IDAR1_AC _CAN0IDAR1.MergedBits.grpAC


/*** CAN0IDAR2 - MSCAN 0 Identifier Acceptance Register 2; 0x00000152 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN0IDAR2STR;
extern volatile CAN0IDAR2STR _CAN0IDAR2 @(REG_BASE + 0x00000152);
#define CAN0IDAR2 _CAN0IDAR2.Byte
#define CAN0IDAR2_AC0 _CAN0IDAR2.Bits.AC0
#define CAN0IDAR2_AC1 _CAN0IDAR2.Bits.AC1
#define CAN0IDAR2_AC2 _CAN0IDAR2.Bits.AC2
#define CAN0IDAR2_AC3 _CAN0IDAR2.Bits.AC3
#define CAN0IDAR2_AC4 _CAN0IDAR2.Bits.AC4
#define CAN0IDAR2_AC5 _CAN0IDAR2.Bits.AC5
#define CAN0IDAR2_AC6 _CAN0IDAR2.Bits.AC6
#define CAN0IDAR2_AC7 _CAN0IDAR2.Bits.AC7
#define CAN0IDAR2_AC _CAN0IDAR2.MergedBits.grpAC


/*** CAN0IDAR3 - MSCAN 0 Identifier Acceptance Register 3; 0x00000153 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN0IDAR3STR;
extern volatile CAN0IDAR3STR _CAN0IDAR3 @(REG_BASE + 0x00000153);
#define CAN0IDAR3 _CAN0IDAR3.Byte
#define CAN0IDAR3_AC0 _CAN0IDAR3.Bits.AC0
#define CAN0IDAR3_AC1 _CAN0IDAR3.Bits.AC1
#define CAN0IDAR3_AC2 _CAN0IDAR3.Bits.AC2
#define CAN0IDAR3_AC3 _CAN0IDAR3.Bits.AC3
#define CAN0IDAR3_AC4 _CAN0IDAR3.Bits.AC4
#define CAN0IDAR3_AC5 _CAN0IDAR3.Bits.AC5
#define CAN0IDAR3_AC6 _CAN0IDAR3.Bits.AC6
#define CAN0IDAR3_AC7 _CAN0IDAR3.Bits.AC7
#define CAN0IDAR3_AC _CAN0IDAR3.MergedBits.grpAC


/*** CAN0IDMR0 - MSCAN 0 Identifier Mask Register 0; 0x00000154 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN0IDMR0STR;
extern volatile CAN0IDMR0STR _CAN0IDMR0 @(REG_BASE + 0x00000154);
#define CAN0IDMR0 _CAN0IDMR0.Byte
#define CAN0IDMR0_AM0 _CAN0IDMR0.Bits.AM0
#define CAN0IDMR0_AM1 _CAN0IDMR0.Bits.AM1
#define CAN0IDMR0_AM2 _CAN0IDMR0.Bits.AM2
#define CAN0IDMR0_AM3 _CAN0IDMR0.Bits.AM3
#define CAN0IDMR0_AM4 _CAN0IDMR0.Bits.AM4
#define CAN0IDMR0_AM5 _CAN0IDMR0.Bits.AM5
#define CAN0IDMR0_AM6 _CAN0IDMR0.Bits.AM6
#define CAN0IDMR0_AM7 _CAN0IDMR0.Bits.AM7
#define CAN0IDMR0_AM _CAN0IDMR0.MergedBits.grpAM


/*** CAN0IDMR1 - MSCAN 0 Identifier Mask Register 1; 0x00000155 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN0IDMR1STR;
extern volatile CAN0IDMR1STR _CAN0IDMR1 @(REG_BASE + 0x00000155);
#define CAN0IDMR1 _CAN0IDMR1.Byte
#define CAN0IDMR1_AM0 _CAN0IDMR1.Bits.AM0
#define CAN0IDMR1_AM1 _CAN0IDMR1.Bits.AM1
#define CAN0IDMR1_AM2 _CAN0IDMR1.Bits.AM2
#define CAN0IDMR1_AM3 _CAN0IDMR1.Bits.AM3
#define CAN0IDMR1_AM4 _CAN0IDMR1.Bits.AM4
#define CAN0IDMR1_AM5 _CAN0IDMR1.Bits.AM5
#define CAN0IDMR1_AM6 _CAN0IDMR1.Bits.AM6
#define CAN0IDMR1_AM7 _CAN0IDMR1.Bits.AM7
#define CAN0IDMR1_AM _CAN0IDMR1.MergedBits.grpAM


/*** CAN0IDMR2 - MSCAN 0 Identifier Mask Register 2; 0x00000156 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN0IDMR2STR;
extern volatile CAN0IDMR2STR _CAN0IDMR2 @(REG_BASE + 0x00000156);
#define CAN0IDMR2 _CAN0IDMR2.Byte
#define CAN0IDMR2_AM0 _CAN0IDMR2.Bits.AM0
#define CAN0IDMR2_AM1 _CAN0IDMR2.Bits.AM1
#define CAN0IDMR2_AM2 _CAN0IDMR2.Bits.AM2
#define CAN0IDMR2_AM3 _CAN0IDMR2.Bits.AM3
#define CAN0IDMR2_AM4 _CAN0IDMR2.Bits.AM4
#define CAN0IDMR2_AM5 _CAN0IDMR2.Bits.AM5
#define CAN0IDMR2_AM6 _CAN0IDMR2.Bits.AM6
#define CAN0IDMR2_AM7 _CAN0IDMR2.Bits.AM7
#define CAN0IDMR2_AM _CAN0IDMR2.MergedBits.grpAM


/*** CAN0IDMR3 - MSCAN 0 Identifier Mask Register 3; 0x00000157 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN0IDMR3STR;
extern volatile CAN0IDMR3STR _CAN0IDMR3 @(REG_BASE + 0x00000157);
#define CAN0IDMR3 _CAN0IDMR3.Byte
#define CAN0IDMR3_AM0 _CAN0IDMR3.Bits.AM0
#define CAN0IDMR3_AM1 _CAN0IDMR3.Bits.AM1
#define CAN0IDMR3_AM2 _CAN0IDMR3.Bits.AM2
#define CAN0IDMR3_AM3 _CAN0IDMR3.Bits.AM3
#define CAN0IDMR3_AM4 _CAN0IDMR3.Bits.AM4
#define CAN0IDMR3_AM5 _CAN0IDMR3.Bits.AM5
#define CAN0IDMR3_AM6 _CAN0IDMR3.Bits.AM6
#define CAN0IDMR3_AM7 _CAN0IDMR3.Bits.AM7
#define CAN0IDMR3_AM _CAN0IDMR3.MergedBits.grpAM


/*** CAN0IDAR4 - MSCAN 0 Identifier Acceptance Register 4; 0x00000158 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN0IDAR4STR;
extern volatile CAN0IDAR4STR _CAN0IDAR4 @(REG_BASE + 0x00000158);
#define CAN0IDAR4 _CAN0IDAR4.Byte
#define CAN0IDAR4_AC0 _CAN0IDAR4.Bits.AC0
#define CAN0IDAR4_AC1 _CAN0IDAR4.Bits.AC1
#define CAN0IDAR4_AC2 _CAN0IDAR4.Bits.AC2
#define CAN0IDAR4_AC3 _CAN0IDAR4.Bits.AC3
#define CAN0IDAR4_AC4 _CAN0IDAR4.Bits.AC4
#define CAN0IDAR4_AC5 _CAN0IDAR4.Bits.AC5
#define CAN0IDAR4_AC6 _CAN0IDAR4.Bits.AC6
#define CAN0IDAR4_AC7 _CAN0IDAR4.Bits.AC7
#define CAN0IDAR4_AC _CAN0IDAR4.MergedBits.grpAC


/*** CAN0IDAR5 - MSCAN 0 Identifier Acceptance Register 5; 0x00000159 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN0IDAR5STR;
extern volatile CAN0IDAR5STR _CAN0IDAR5 @(REG_BASE + 0x00000159);
#define CAN0IDAR5 _CAN0IDAR5.Byte
#define CAN0IDAR5_AC0 _CAN0IDAR5.Bits.AC0
#define CAN0IDAR5_AC1 _CAN0IDAR5.Bits.AC1
#define CAN0IDAR5_AC2 _CAN0IDAR5.Bits.AC2
#define CAN0IDAR5_AC3 _CAN0IDAR5.Bits.AC3
#define CAN0IDAR5_AC4 _CAN0IDAR5.Bits.AC4
#define CAN0IDAR5_AC5 _CAN0IDAR5.Bits.AC5
#define CAN0IDAR5_AC6 _CAN0IDAR5.Bits.AC6
#define CAN0IDAR5_AC7 _CAN0IDAR5.Bits.AC7
#define CAN0IDAR5_AC _CAN0IDAR5.MergedBits.grpAC


/*** CAN0IDAR6 - MSCAN 0 Identifier Acceptance Register 6; 0x0000015A ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN0IDAR6STR;
extern volatile CAN0IDAR6STR _CAN0IDAR6 @(REG_BASE + 0x0000015A);
#define CAN0IDAR6 _CAN0IDAR6.Byte
#define CAN0IDAR6_AC0 _CAN0IDAR6.Bits.AC0
#define CAN0IDAR6_AC1 _CAN0IDAR6.Bits.AC1
#define CAN0IDAR6_AC2 _CAN0IDAR6.Bits.AC2
#define CAN0IDAR6_AC3 _CAN0IDAR6.Bits.AC3
#define CAN0IDAR6_AC4 _CAN0IDAR6.Bits.AC4
#define CAN0IDAR6_AC5 _CAN0IDAR6.Bits.AC5
#define CAN0IDAR6_AC6 _CAN0IDAR6.Bits.AC6
#define CAN0IDAR6_AC7 _CAN0IDAR6.Bits.AC7
#define CAN0IDAR6_AC _CAN0IDAR6.MergedBits.grpAC


/*** CAN0IDAR7 - MSCAN 0 Identifier Acceptance Register 7; 0x0000015B ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN0IDAR7STR;
extern volatile CAN0IDAR7STR _CAN0IDAR7 @(REG_BASE + 0x0000015B);
#define CAN0IDAR7 _CAN0IDAR7.Byte
#define CAN0IDAR7_AC0 _CAN0IDAR7.Bits.AC0
#define CAN0IDAR7_AC1 _CAN0IDAR7.Bits.AC1
#define CAN0IDAR7_AC2 _CAN0IDAR7.Bits.AC2
#define CAN0IDAR7_AC3 _CAN0IDAR7.Bits.AC3
#define CAN0IDAR7_AC4 _CAN0IDAR7.Bits.AC4
#define CAN0IDAR7_AC5 _CAN0IDAR7.Bits.AC5
#define CAN0IDAR7_AC6 _CAN0IDAR7.Bits.AC6
#define CAN0IDAR7_AC7 _CAN0IDAR7.Bits.AC7
#define CAN0IDAR7_AC _CAN0IDAR7.MergedBits.grpAC


/*** CAN0IDMR4 - MSCAN 0 Identifier Mask Register 4; 0x0000015C ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN0IDMR4STR;
extern volatile CAN0IDMR4STR _CAN0IDMR4 @(REG_BASE + 0x0000015C);
#define CAN0IDMR4 _CAN0IDMR4.Byte
#define CAN0IDMR4_AM0 _CAN0IDMR4.Bits.AM0
#define CAN0IDMR4_AM1 _CAN0IDMR4.Bits.AM1
#define CAN0IDMR4_AM2 _CAN0IDMR4.Bits.AM2
#define CAN0IDMR4_AM3 _CAN0IDMR4.Bits.AM3
#define CAN0IDMR4_AM4 _CAN0IDMR4.Bits.AM4
#define CAN0IDMR4_AM5 _CAN0IDMR4.Bits.AM5
#define CAN0IDMR4_AM6 _CAN0IDMR4.Bits.AM6
#define CAN0IDMR4_AM7 _CAN0IDMR4.Bits.AM7
#define CAN0IDMR4_AM _CAN0IDMR4.MergedBits.grpAM


/*** CAN0IDMR5 - MSCAN 0 Identifier Mask Register 5; 0x0000015D ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN0IDMR5STR;
extern volatile CAN0IDMR5STR _CAN0IDMR5 @(REG_BASE + 0x0000015D);
#define CAN0IDMR5 _CAN0IDMR5.Byte
#define CAN0IDMR5_AM0 _CAN0IDMR5.Bits.AM0
#define CAN0IDMR5_AM1 _CAN0IDMR5.Bits.AM1
#define CAN0IDMR5_AM2 _CAN0IDMR5.Bits.AM2
#define CAN0IDMR5_AM3 _CAN0IDMR5.Bits.AM3
#define CAN0IDMR5_AM4 _CAN0IDMR5.Bits.AM4
#define CAN0IDMR5_AM5 _CAN0IDMR5.Bits.AM5
#define CAN0IDMR5_AM6 _CAN0IDMR5.Bits.AM6
#define CAN0IDMR5_AM7 _CAN0IDMR5.Bits.AM7
#define CAN0IDMR5_AM _CAN0IDMR5.MergedBits.grpAM


/*** CAN0IDMR6 - MSCAN 0 Identifier Mask Register 6; 0x0000015E ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN0IDMR6STR;
extern volatile CAN0IDMR6STR _CAN0IDMR6 @(REG_BASE + 0x0000015E);
#define CAN0IDMR6 _CAN0IDMR6.Byte
#define CAN0IDMR6_AM0 _CAN0IDMR6.Bits.AM0
#define CAN0IDMR6_AM1 _CAN0IDMR6.Bits.AM1
#define CAN0IDMR6_AM2 _CAN0IDMR6.Bits.AM2
#define CAN0IDMR6_AM3 _CAN0IDMR6.Bits.AM3
#define CAN0IDMR6_AM4 _CAN0IDMR6.Bits.AM4
#define CAN0IDMR6_AM5 _CAN0IDMR6.Bits.AM5
#define CAN0IDMR6_AM6 _CAN0IDMR6.Bits.AM6
#define CAN0IDMR6_AM7 _CAN0IDMR6.Bits.AM7
#define CAN0IDMR6_AM _CAN0IDMR6.MergedBits.grpAM


/*** CAN0IDMR7 - MSCAN 0 Identifier Mask Register 7; 0x0000015F ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN0IDMR7STR;
extern volatile CAN0IDMR7STR _CAN0IDMR7 @(REG_BASE + 0x0000015F);
#define CAN0IDMR7 _CAN0IDMR7.Byte
#define CAN0IDMR7_AM0 _CAN0IDMR7.Bits.AM0
#define CAN0IDMR7_AM1 _CAN0IDMR7.Bits.AM1
#define CAN0IDMR7_AM2 _CAN0IDMR7.Bits.AM2
#define CAN0IDMR7_AM3 _CAN0IDMR7.Bits.AM3
#define CAN0IDMR7_AM4 _CAN0IDMR7.Bits.AM4
#define CAN0IDMR7_AM5 _CAN0IDMR7.Bits.AM5
#define CAN0IDMR7_AM6 _CAN0IDMR7.Bits.AM6
#define CAN0IDMR7_AM7 _CAN0IDMR7.Bits.AM7
#define CAN0IDMR7_AM _CAN0IDMR7.MergedBits.grpAM


/*** CAN0RXIDR0 - MSCAN 0 Receive Identifier Register 0; 0x00000160 ***/
typedef union {
  byte Byte;
  struct {
    byte ID21        :1;                                       /* Extended format identifier Bit 21 */
    byte ID22        :1;                                       /* Extended format identifier Bit 22 */
    byte ID23        :1;                                       /* Extended format identifier Bit 23 */
    byte ID24        :1;                                       /* Extended format identifier Bit 24 */
    byte ID25        :1;                                       /* Extended format identifier Bit 25 */
    byte ID26        :1;                                       /* Extended format identifier Bit 26 */
    byte ID27        :1;                                       /* Extended format identifier Bit 27 */
    byte ID28        :1;                                       /* Extended format identifier Bit 28 */
  } Bits;
  struct {
    byte grpID_21 :8;
  } MergedBits;
} CAN0RXIDR0STR;
extern volatile CAN0RXIDR0STR _CAN0RXIDR0 @(REG_BASE + 0x00000160);
#define CAN0RXIDR0 _CAN0RXIDR0.Byte
#define CAN0RXIDR0_ID21 _CAN0RXIDR0.Bits.ID21
#define CAN0RXIDR0_ID22 _CAN0RXIDR0.Bits.ID22
#define CAN0RXIDR0_ID23 _CAN0RXIDR0.Bits.ID23
#define CAN0RXIDR0_ID24 _CAN0RXIDR0.Bits.ID24
#define CAN0RXIDR0_ID25 _CAN0RXIDR0.Bits.ID25
#define CAN0RXIDR0_ID26 _CAN0RXIDR0.Bits.ID26
#define CAN0RXIDR0_ID27 _CAN0RXIDR0.Bits.ID27
#define CAN0RXIDR0_ID28 _CAN0RXIDR0.Bits.ID28
#define CAN0RXIDR0_ID_21 _CAN0RXIDR0.MergedBits.grpID_21
#define CAN0RXIDR0_ID CAN0RXIDR0_ID_21


/*** CAN0RXIDR1 - MSCAN 0 Receive Identifier Register 1; 0x00000161 ***/
typedef union {
  byte Byte;
  struct {
    byte ID15        :1;                                       /* Extended format identifier Bit 15 */
    byte ID16        :1;                                       /* Extended format identifier Bit 16 */
    byte ID17        :1;                                       /* Extended format identifier Bit 17 */
    byte IDE         :1;                                       /* ID Extended */
    byte SRR         :1;                                       /* Substitute Remote Request */
    byte ID18        :1;                                       /* Extended format identifier Bit 18 */
    byte ID19        :1;                                       /* Extended format identifier Bit 19 */
    byte ID20        :1;                                       /* Extended format identifier Bit 20 */
  } Bits;
  struct {
    byte grpID_15 :3;
    byte         :1;
    byte         :1;
    byte grpID_18 :3;
  } MergedBits;
} CAN0RXIDR1STR;
extern volatile CAN0RXIDR1STR _CAN0RXIDR1 @(REG_BASE + 0x00000161);
#define CAN0RXIDR1 _CAN0RXIDR1.Byte
#define CAN0RXIDR1_ID15 _CAN0RXIDR1.Bits.ID15
#define CAN0RXIDR1_ID16 _CAN0RXIDR1.Bits.ID16
#define CAN0RXIDR1_ID17 _CAN0RXIDR1.Bits.ID17
#define CAN0RXIDR1_IDE _CAN0RXIDR1.Bits.IDE
#define CAN0RXIDR1_SRR _CAN0RXIDR1.Bits.SRR
#define CAN0RXIDR1_ID18 _CAN0RXIDR1.Bits.ID18
#define CAN0RXIDR1_ID19 _CAN0RXIDR1.Bits.ID19
#define CAN0RXIDR1_ID20 _CAN0RXIDR1.Bits.ID20
#define CAN0RXIDR1_ID_15 _CAN0RXIDR1.MergedBits.grpID_15
#define CAN0RXIDR1_ID_18 _CAN0RXIDR1.MergedBits.grpID_18
#define CAN0RXIDR1_ID CAN0RXIDR1_ID_15


/*** CAN0RXIDR2 - MSCAN 0 Receive Identifier Register 2; 0x00000162 ***/
typedef union {
  byte Byte;
  struct {
    byte ID7         :1;                                       /* Extended format identifier Bit 7 */
    byte ID8         :1;                                       /* Extended format identifier Bit 8 */
    byte ID9         :1;                                       /* Extended format identifier Bit 9 */
    byte ID10        :1;                                       /* Extended format identifier Bit 10 */
    byte ID11        :1;                                       /* Extended format identifier Bit 11 */
    byte ID12        :1;                                       /* Extended format identifier Bit 12 */
    byte ID13        :1;                                       /* Extended format identifier Bit 13 */
    byte ID14        :1;                                       /* Extended format identifier Bit 14 */
  } Bits;
  struct {
    byte grpID_7 :8;
  } MergedBits;
} CAN0RXIDR2STR;
extern volatile CAN0RXIDR2STR _CAN0RXIDR2 @(REG_BASE + 0x00000162);
#define CAN0RXIDR2 _CAN0RXIDR2.Byte
#define CAN0RXIDR2_ID7 _CAN0RXIDR2.Bits.ID7
#define CAN0RXIDR2_ID8 _CAN0RXIDR2.Bits.ID8
#define CAN0RXIDR2_ID9 _CAN0RXIDR2.Bits.ID9
#define CAN0RXIDR2_ID10 _CAN0RXIDR2.Bits.ID10
#define CAN0RXIDR2_ID11 _CAN0RXIDR2.Bits.ID11
#define CAN0RXIDR2_ID12 _CAN0RXIDR2.Bits.ID12
#define CAN0RXIDR2_ID13 _CAN0RXIDR2.Bits.ID13
#define CAN0RXIDR2_ID14 _CAN0RXIDR2.Bits.ID14
#define CAN0RXIDR2_ID_7 _CAN0RXIDR2.MergedBits.grpID_7
#define CAN0RXIDR2_ID CAN0RXIDR2_ID_7


/*** CAN0RXIDR3 - MSCAN 0 Receive Identifier Register 3; 0x00000163 ***/
typedef union {
  byte Byte;
  struct {
    byte RTR         :1;                                       /* Remote Transmission Request */
    byte ID0         :1;                                       /* Extended format identifier Bit 0 */
    byte ID1         :1;                                       /* Extended format identifier Bit 1 */
    byte ID2         :1;                                       /* Extended format identifier Bit 2 */
    byte ID3         :1;                                       /* Extended format identifier Bit 3 */
    byte ID4         :1;                                       /* Extended format identifier Bit 4 */
    byte ID5         :1;                                       /* Extended format identifier Bit 5 */
    byte ID6         :1;                                       /* Extended format identifier Bit 6 */
  } Bits;
  struct {
    byte         :1;
    byte grpID   :7;
  } MergedBits;
} CAN0RXIDR3STR;
extern volatile CAN0RXIDR3STR _CAN0RXIDR3 @(REG_BASE + 0x00000163);
#define CAN0RXIDR3 _CAN0RXIDR3.Byte
#define CAN0RXIDR3_RTR _CAN0RXIDR3.Bits.RTR
#define CAN0RXIDR3_ID0 _CAN0RXIDR3.Bits.ID0
#define CAN0RXIDR3_ID1 _CAN0RXIDR3.Bits.ID1
#define CAN0RXIDR3_ID2 _CAN0RXIDR3.Bits.ID2
#define CAN0RXIDR3_ID3 _CAN0RXIDR3.Bits.ID3
#define CAN0RXIDR3_ID4 _CAN0RXIDR3.Bits.ID4
#define CAN0RXIDR3_ID5 _CAN0RXIDR3.Bits.ID5
#define CAN0RXIDR3_ID6 _CAN0RXIDR3.Bits.ID6
#define CAN0RXIDR3_ID _CAN0RXIDR3.MergedBits.grpID


/*** CAN0RXDSR0 - MSCAN 0 Receive Data Segment Register 0; 0x00000164 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0RXDSR0STR;
extern volatile CAN0RXDSR0STR _CAN0RXDSR0 @(REG_BASE + 0x00000164);
#define CAN0RXDSR0 _CAN0RXDSR0.Byte
#define CAN0RXDSR0_DB0 _CAN0RXDSR0.Bits.DB0
#define CAN0RXDSR0_DB1 _CAN0RXDSR0.Bits.DB1
#define CAN0RXDSR0_DB2 _CAN0RXDSR0.Bits.DB2
#define CAN0RXDSR0_DB3 _CAN0RXDSR0.Bits.DB3
#define CAN0RXDSR0_DB4 _CAN0RXDSR0.Bits.DB4
#define CAN0RXDSR0_DB5 _CAN0RXDSR0.Bits.DB5
#define CAN0RXDSR0_DB6 _CAN0RXDSR0.Bits.DB6
#define CAN0RXDSR0_DB7 _CAN0RXDSR0.Bits.DB7
#define CAN0RXDSR0_DB _CAN0RXDSR0.MergedBits.grpDB


/*** CAN0RXDSR1 - MSCAN 0 Receive Data Segment Register 1; 0x00000165 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0RXDSR1STR;
extern volatile CAN0RXDSR1STR _CAN0RXDSR1 @(REG_BASE + 0x00000165);
#define CAN0RXDSR1 _CAN0RXDSR1.Byte
#define CAN0RXDSR1_DB0 _CAN0RXDSR1.Bits.DB0
#define CAN0RXDSR1_DB1 _CAN0RXDSR1.Bits.DB1
#define CAN0RXDSR1_DB2 _CAN0RXDSR1.Bits.DB2
#define CAN0RXDSR1_DB3 _CAN0RXDSR1.Bits.DB3
#define CAN0RXDSR1_DB4 _CAN0RXDSR1.Bits.DB4
#define CAN0RXDSR1_DB5 _CAN0RXDSR1.Bits.DB5
#define CAN0RXDSR1_DB6 _CAN0RXDSR1.Bits.DB6
#define CAN0RXDSR1_DB7 _CAN0RXDSR1.Bits.DB7
#define CAN0RXDSR1_DB _CAN0RXDSR1.MergedBits.grpDB


/*** CAN0RXDSR2 - MSCAN 0 Receive Data Segment Register 2; 0x00000166 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0RXDSR2STR;
extern volatile CAN0RXDSR2STR _CAN0RXDSR2 @(REG_BASE + 0x00000166);
#define CAN0RXDSR2 _CAN0RXDSR2.Byte
#define CAN0RXDSR2_DB0 _CAN0RXDSR2.Bits.DB0
#define CAN0RXDSR2_DB1 _CAN0RXDSR2.Bits.DB1
#define CAN0RXDSR2_DB2 _CAN0RXDSR2.Bits.DB2
#define CAN0RXDSR2_DB3 _CAN0RXDSR2.Bits.DB3
#define CAN0RXDSR2_DB4 _CAN0RXDSR2.Bits.DB4
#define CAN0RXDSR2_DB5 _CAN0RXDSR2.Bits.DB5
#define CAN0RXDSR2_DB6 _CAN0RXDSR2.Bits.DB6
#define CAN0RXDSR2_DB7 _CAN0RXDSR2.Bits.DB7
#define CAN0RXDSR2_DB _CAN0RXDSR2.MergedBits.grpDB


/*** CAN0RXDSR3 - MSCAN 0 Receive Data Segment Register 3; 0x00000167 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0RXDSR3STR;
extern volatile CAN0RXDSR3STR _CAN0RXDSR3 @(REG_BASE + 0x00000167);
#define CAN0RXDSR3 _CAN0RXDSR3.Byte
#define CAN0RXDSR3_DB0 _CAN0RXDSR3.Bits.DB0
#define CAN0RXDSR3_DB1 _CAN0RXDSR3.Bits.DB1
#define CAN0RXDSR3_DB2 _CAN0RXDSR3.Bits.DB2
#define CAN0RXDSR3_DB3 _CAN0RXDSR3.Bits.DB3
#define CAN0RXDSR3_DB4 _CAN0RXDSR3.Bits.DB4
#define CAN0RXDSR3_DB5 _CAN0RXDSR3.Bits.DB5
#define CAN0RXDSR3_DB6 _CAN0RXDSR3.Bits.DB6
#define CAN0RXDSR3_DB7 _CAN0RXDSR3.Bits.DB7
#define CAN0RXDSR3_DB _CAN0RXDSR3.MergedBits.grpDB


/*** CAN0RXDSR4 - MSCAN 0 Receive Data Segment Register 4; 0x00000168 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0RXDSR4STR;
extern volatile CAN0RXDSR4STR _CAN0RXDSR4 @(REG_BASE + 0x00000168);
#define CAN0RXDSR4 _CAN0RXDSR4.Byte
#define CAN0RXDSR4_DB0 _CAN0RXDSR4.Bits.DB0
#define CAN0RXDSR4_DB1 _CAN0RXDSR4.Bits.DB1
#define CAN0RXDSR4_DB2 _CAN0RXDSR4.Bits.DB2
#define CAN0RXDSR4_DB3 _CAN0RXDSR4.Bits.DB3
#define CAN0RXDSR4_DB4 _CAN0RXDSR4.Bits.DB4
#define CAN0RXDSR4_DB5 _CAN0RXDSR4.Bits.DB5
#define CAN0RXDSR4_DB6 _CAN0RXDSR4.Bits.DB6
#define CAN0RXDSR4_DB7 _CAN0RXDSR4.Bits.DB7
#define CAN0RXDSR4_DB _CAN0RXDSR4.MergedBits.grpDB


/*** CAN0RXDSR5 - MSCAN 0 Receive Data Segment Register 5; 0x00000169 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0RXDSR5STR;
extern volatile CAN0RXDSR5STR _CAN0RXDSR5 @(REG_BASE + 0x00000169);
#define CAN0RXDSR5 _CAN0RXDSR5.Byte
#define CAN0RXDSR5_DB0 _CAN0RXDSR5.Bits.DB0
#define CAN0RXDSR5_DB1 _CAN0RXDSR5.Bits.DB1
#define CAN0RXDSR5_DB2 _CAN0RXDSR5.Bits.DB2
#define CAN0RXDSR5_DB3 _CAN0RXDSR5.Bits.DB3
#define CAN0RXDSR5_DB4 _CAN0RXDSR5.Bits.DB4
#define CAN0RXDSR5_DB5 _CAN0RXDSR5.Bits.DB5
#define CAN0RXDSR5_DB6 _CAN0RXDSR5.Bits.DB6
#define CAN0RXDSR5_DB7 _CAN0RXDSR5.Bits.DB7
#define CAN0RXDSR5_DB _CAN0RXDSR5.MergedBits.grpDB


/*** CAN0RXDSR6 - MSCAN 0 Receive Data Segment Register 6; 0x0000016A ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0RXDSR6STR;
extern volatile CAN0RXDSR6STR _CAN0RXDSR6 @(REG_BASE + 0x0000016A);
#define CAN0RXDSR6 _CAN0RXDSR6.Byte
#define CAN0RXDSR6_DB0 _CAN0RXDSR6.Bits.DB0
#define CAN0RXDSR6_DB1 _CAN0RXDSR6.Bits.DB1
#define CAN0RXDSR6_DB2 _CAN0RXDSR6.Bits.DB2
#define CAN0RXDSR6_DB3 _CAN0RXDSR6.Bits.DB3
#define CAN0RXDSR6_DB4 _CAN0RXDSR6.Bits.DB4
#define CAN0RXDSR6_DB5 _CAN0RXDSR6.Bits.DB5
#define CAN0RXDSR6_DB6 _CAN0RXDSR6.Bits.DB6
#define CAN0RXDSR6_DB7 _CAN0RXDSR6.Bits.DB7
#define CAN0RXDSR6_DB _CAN0RXDSR6.MergedBits.grpDB


/*** CAN0RXDSR7 - MSCAN 0 Receive Data Segment Register 7; 0x0000016B ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0RXDSR7STR;
extern volatile CAN0RXDSR7STR _CAN0RXDSR7 @(REG_BASE + 0x0000016B);
#define CAN0RXDSR7 _CAN0RXDSR7.Byte
#define CAN0RXDSR7_DB0 _CAN0RXDSR7.Bits.DB0
#define CAN0RXDSR7_DB1 _CAN0RXDSR7.Bits.DB1
#define CAN0RXDSR7_DB2 _CAN0RXDSR7.Bits.DB2
#define CAN0RXDSR7_DB3 _CAN0RXDSR7.Bits.DB3
#define CAN0RXDSR7_DB4 _CAN0RXDSR7.Bits.DB4
#define CAN0RXDSR7_DB5 _CAN0RXDSR7.Bits.DB5
#define CAN0RXDSR7_DB6 _CAN0RXDSR7.Bits.DB6
#define CAN0RXDSR7_DB7 _CAN0RXDSR7.Bits.DB7
#define CAN0RXDSR7_DB _CAN0RXDSR7.MergedBits.grpDB


/*** CAN0RXDLR - MSCAN 0 Receive Data Length Register; 0x0000016C ***/
typedef union {
  byte Byte;
  struct {
    byte DLC0        :1;                                       /* Data Length Code Bit 0 */
    byte DLC1        :1;                                       /* Data Length Code Bit 1 */
    byte DLC2        :1;                                       /* Data Length Code Bit 2 */
    byte DLC3        :1;                                       /* Data Length Code Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDLC  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN0RXDLRSTR;
extern volatile CAN0RXDLRSTR _CAN0RXDLR @(REG_BASE + 0x0000016C);
#define CAN0RXDLR _CAN0RXDLR.Byte
#define CAN0RXDLR_DLC0 _CAN0RXDLR.Bits.DLC0
#define CAN0RXDLR_DLC1 _CAN0RXDLR.Bits.DLC1
#define CAN0RXDLR_DLC2 _CAN0RXDLR.Bits.DLC2
#define CAN0RXDLR_DLC3 _CAN0RXDLR.Bits.DLC3
#define CAN0RXDLR_DLC _CAN0RXDLR.MergedBits.grpDLC


/*** CAN0TXIDR0 - MSCAN 0 Transmit Identifier Register 0; 0x00000170 ***/
typedef union {
  byte Byte;
  struct {
    byte ID21        :1;                                       /* Extended format identifier Bit 21 */
    byte ID22        :1;                                       /* Extended format identifier Bit 22 */
    byte ID23        :1;                                       /* Extended format identifier Bit 23 */
    byte ID24        :1;                                       /* Extended format identifier Bit 24 */
    byte ID25        :1;                                       /* Extended format identifier Bit 25 */
    byte ID26        :1;                                       /* Extended format identifier Bit 26 */
    byte ID27        :1;                                       /* Extended format identifier Bit 27 */
    byte ID28        :1;                                       /* Extended format identifier Bit 28 */
  } Bits;
  struct {
    byte grpID_21 :8;
  } MergedBits;
} CAN0TXIDR0STR;
extern volatile CAN0TXIDR0STR _CAN0TXIDR0 @(REG_BASE + 0x00000170);
#define CAN0TXIDR0 _CAN0TXIDR0.Byte
#define CAN0TXIDR0_ID21 _CAN0TXIDR0.Bits.ID21
#define CAN0TXIDR0_ID22 _CAN0TXIDR0.Bits.ID22
#define CAN0TXIDR0_ID23 _CAN0TXIDR0.Bits.ID23
#define CAN0TXIDR0_ID24 _CAN0TXIDR0.Bits.ID24
#define CAN0TXIDR0_ID25 _CAN0TXIDR0.Bits.ID25
#define CAN0TXIDR0_ID26 _CAN0TXIDR0.Bits.ID26
#define CAN0TXIDR0_ID27 _CAN0TXIDR0.Bits.ID27
#define CAN0TXIDR0_ID28 _CAN0TXIDR0.Bits.ID28
#define CAN0TXIDR0_ID_21 _CAN0TXIDR0.MergedBits.grpID_21
#define CAN0TXIDR0_ID CAN0TXIDR0_ID_21


/*** CAN0TXIDR1 - MSCAN 0 Transmit Identifier Register 1; 0x00000171 ***/
typedef union {
  byte Byte;
  struct {
    byte ID15        :1;                                       /* Extended format identifier Bit 15 */
    byte ID16        :1;                                       /* Extended format identifier Bit 16 */
    byte ID17        :1;                                       /* Extended format identifier Bit 17 */
    byte IDE         :1;                                       /* ID Extended */
    byte SRR         :1;                                       /* Substitute Remote Request */
    byte ID18        :1;                                       /* Extended format identifier Bit 18 */
    byte ID19        :1;                                       /* Extended format identifier Bit 19 */
    byte ID20        :1;                                       /* Extended format identifier Bit 20 */
  } Bits;
  struct {
    byte grpID_15 :3;
    byte         :1;
    byte         :1;
    byte grpID_18 :3;
  } MergedBits;
} CAN0TXIDR1STR;
extern volatile CAN0TXIDR1STR _CAN0TXIDR1 @(REG_BASE + 0x00000171);
#define CAN0TXIDR1 _CAN0TXIDR1.Byte
#define CAN0TXIDR1_ID15 _CAN0TXIDR1.Bits.ID15
#define CAN0TXIDR1_ID16 _CAN0TXIDR1.Bits.ID16
#define CAN0TXIDR1_ID17 _CAN0TXIDR1.Bits.ID17
#define CAN0TXIDR1_IDE _CAN0TXIDR1.Bits.IDE
#define CAN0TXIDR1_SRR _CAN0TXIDR1.Bits.SRR
#define CAN0TXIDR1_ID18 _CAN0TXIDR1.Bits.ID18
#define CAN0TXIDR1_ID19 _CAN0TXIDR1.Bits.ID19
#define CAN0TXIDR1_ID20 _CAN0TXIDR1.Bits.ID20
#define CAN0TXIDR1_ID_15 _CAN0TXIDR1.MergedBits.grpID_15
#define CAN0TXIDR1_ID_18 _CAN0TXIDR1.MergedBits.grpID_18
#define CAN0TXIDR1_ID CAN0TXIDR1_ID_15


/*** CAN0TXIDR2 - MSCAN 0 Transmit Identifier Register 2; 0x00000172 ***/
typedef union {
  byte Byte;
  struct {
    byte ID7         :1;                                       /* Extended format identifier Bit 7 */
    byte ID8         :1;                                       /* Extended format identifier Bit 8 */
    byte ID9         :1;                                       /* Extended format identifier Bit 9 */
    byte ID10        :1;                                       /* Extended format identifier Bit 10 */
    byte ID11        :1;                                       /* Extended format identifier Bit 11 */
    byte ID12        :1;                                       /* Extended format identifier Bit 12 */
    byte ID13        :1;                                       /* Extended format identifier Bit 13 */
    byte ID14        :1;                                       /* Extended format identifier Bit 14 */
  } Bits;
  struct {
    byte grpID_7 :8;
  } MergedBits;
} CAN0TXIDR2STR;
extern volatile CAN0TXIDR2STR _CAN0TXIDR2 @(REG_BASE + 0x00000172);
#define CAN0TXIDR2 _CAN0TXIDR2.Byte
#define CAN0TXIDR2_ID7 _CAN0TXIDR2.Bits.ID7
#define CAN0TXIDR2_ID8 _CAN0TXIDR2.Bits.ID8
#define CAN0TXIDR2_ID9 _CAN0TXIDR2.Bits.ID9
#define CAN0TXIDR2_ID10 _CAN0TXIDR2.Bits.ID10
#define CAN0TXIDR2_ID11 _CAN0TXIDR2.Bits.ID11
#define CAN0TXIDR2_ID12 _CAN0TXIDR2.Bits.ID12
#define CAN0TXIDR2_ID13 _CAN0TXIDR2.Bits.ID13
#define CAN0TXIDR2_ID14 _CAN0TXIDR2.Bits.ID14
#define CAN0TXIDR2_ID_7 _CAN0TXIDR2.MergedBits.grpID_7
#define CAN0TXIDR2_ID CAN0TXIDR2_ID_7


/*** CAN0TXIDR3 - MSCAN 0 Transmit Identifier Register 3; 0x00000173 ***/
typedef union {
  byte Byte;
  struct {
    byte RTR         :1;                                       /* Remote Transmission Request */
    byte ID0         :1;                                       /* Extended format identifier Bit 0 */
    byte ID1         :1;                                       /* Extended format identifier Bit 1 */
    byte ID2         :1;                                       /* Extended format identifier Bit 2 */
    byte ID3         :1;                                       /* Extended format identifier Bit 3 */
    byte ID4         :1;                                       /* Extended format identifier Bit 4 */
    byte ID5         :1;                                       /* Extended format identifier Bit 5 */
    byte ID6         :1;                                       /* Extended format identifier Bit 6 */
  } Bits;
  struct {
    byte         :1;
    byte grpID   :7;
  } MergedBits;
} CAN0TXIDR3STR;
extern volatile CAN0TXIDR3STR _CAN0TXIDR3 @(REG_BASE + 0x00000173);
#define CAN0TXIDR3 _CAN0TXIDR3.Byte
#define CAN0TXIDR3_RTR _CAN0TXIDR3.Bits.RTR
#define CAN0TXIDR3_ID0 _CAN0TXIDR3.Bits.ID0
#define CAN0TXIDR3_ID1 _CAN0TXIDR3.Bits.ID1
#define CAN0TXIDR3_ID2 _CAN0TXIDR3.Bits.ID2
#define CAN0TXIDR3_ID3 _CAN0TXIDR3.Bits.ID3
#define CAN0TXIDR3_ID4 _CAN0TXIDR3.Bits.ID4
#define CAN0TXIDR3_ID5 _CAN0TXIDR3.Bits.ID5
#define CAN0TXIDR3_ID6 _CAN0TXIDR3.Bits.ID6
#define CAN0TXIDR3_ID _CAN0TXIDR3.MergedBits.grpID


/*** CAN0TXDSR0 - MSCAN 0 Transmit Data Segment Register 0; 0x00000174 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0TXDSR0STR;
extern volatile CAN0TXDSR0STR _CAN0TXDSR0 @(REG_BASE + 0x00000174);
#define CAN0TXDSR0 _CAN0TXDSR0.Byte
#define CAN0TXDSR0_DB0 _CAN0TXDSR0.Bits.DB0
#define CAN0TXDSR0_DB1 _CAN0TXDSR0.Bits.DB1
#define CAN0TXDSR0_DB2 _CAN0TXDSR0.Bits.DB2
#define CAN0TXDSR0_DB3 _CAN0TXDSR0.Bits.DB3
#define CAN0TXDSR0_DB4 _CAN0TXDSR0.Bits.DB4
#define CAN0TXDSR0_DB5 _CAN0TXDSR0.Bits.DB5
#define CAN0TXDSR0_DB6 _CAN0TXDSR0.Bits.DB6
#define CAN0TXDSR0_DB7 _CAN0TXDSR0.Bits.DB7
#define CAN0TXDSR0_DB _CAN0TXDSR0.MergedBits.grpDB


/*** CAN0TXDSR1 - MSCAN 0 Transmit Data Segment Register 1; 0x00000175 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0TXDSR1STR;
extern volatile CAN0TXDSR1STR _CAN0TXDSR1 @(REG_BASE + 0x00000175);
#define CAN0TXDSR1 _CAN0TXDSR1.Byte
#define CAN0TXDSR1_DB0 _CAN0TXDSR1.Bits.DB0
#define CAN0TXDSR1_DB1 _CAN0TXDSR1.Bits.DB1
#define CAN0TXDSR1_DB2 _CAN0TXDSR1.Bits.DB2
#define CAN0TXDSR1_DB3 _CAN0TXDSR1.Bits.DB3
#define CAN0TXDSR1_DB4 _CAN0TXDSR1.Bits.DB4
#define CAN0TXDSR1_DB5 _CAN0TXDSR1.Bits.DB5
#define CAN0TXDSR1_DB6 _CAN0TXDSR1.Bits.DB6
#define CAN0TXDSR1_DB7 _CAN0TXDSR1.Bits.DB7
#define CAN0TXDSR1_DB _CAN0TXDSR1.MergedBits.grpDB


/*** CAN0TXDSR2 - MSCAN 0 Transmit Data Segment Register 2; 0x00000176 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0TXDSR2STR;
extern volatile CAN0TXDSR2STR _CAN0TXDSR2 @(REG_BASE + 0x00000176);
#define CAN0TXDSR2 _CAN0TXDSR2.Byte
#define CAN0TXDSR2_DB0 _CAN0TXDSR2.Bits.DB0
#define CAN0TXDSR2_DB1 _CAN0TXDSR2.Bits.DB1
#define CAN0TXDSR2_DB2 _CAN0TXDSR2.Bits.DB2
#define CAN0TXDSR2_DB3 _CAN0TXDSR2.Bits.DB3
#define CAN0TXDSR2_DB4 _CAN0TXDSR2.Bits.DB4
#define CAN0TXDSR2_DB5 _CAN0TXDSR2.Bits.DB5
#define CAN0TXDSR2_DB6 _CAN0TXDSR2.Bits.DB6
#define CAN0TXDSR2_DB7 _CAN0TXDSR2.Bits.DB7
#define CAN0TXDSR2_DB _CAN0TXDSR2.MergedBits.grpDB


/*** CAN0TXDSR3 - MSCAN 0 Transmit Data Segment Register 3; 0x00000177 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0TXDSR3STR;
extern volatile CAN0TXDSR3STR _CAN0TXDSR3 @(REG_BASE + 0x00000177);
#define CAN0TXDSR3 _CAN0TXDSR3.Byte
#define CAN0TXDSR3_DB0 _CAN0TXDSR3.Bits.DB0
#define CAN0TXDSR3_DB1 _CAN0TXDSR3.Bits.DB1
#define CAN0TXDSR3_DB2 _CAN0TXDSR3.Bits.DB2
#define CAN0TXDSR3_DB3 _CAN0TXDSR3.Bits.DB3
#define CAN0TXDSR3_DB4 _CAN0TXDSR3.Bits.DB4
#define CAN0TXDSR3_DB5 _CAN0TXDSR3.Bits.DB5
#define CAN0TXDSR3_DB6 _CAN0TXDSR3.Bits.DB6
#define CAN0TXDSR3_DB7 _CAN0TXDSR3.Bits.DB7
#define CAN0TXDSR3_DB _CAN0TXDSR3.MergedBits.grpDB


/*** CAN0TXDSR4 - MSCAN 0 Transmit Data Segment Register 4; 0x00000178 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0TXDSR4STR;
extern volatile CAN0TXDSR4STR _CAN0TXDSR4 @(REG_BASE + 0x00000178);
#define CAN0TXDSR4 _CAN0TXDSR4.Byte
#define CAN0TXDSR4_DB0 _CAN0TXDSR4.Bits.DB0
#define CAN0TXDSR4_DB1 _CAN0TXDSR4.Bits.DB1
#define CAN0TXDSR4_DB2 _CAN0TXDSR4.Bits.DB2
#define CAN0TXDSR4_DB3 _CAN0TXDSR4.Bits.DB3
#define CAN0TXDSR4_DB4 _CAN0TXDSR4.Bits.DB4
#define CAN0TXDSR4_DB5 _CAN0TXDSR4.Bits.DB5
#define CAN0TXDSR4_DB6 _CAN0TXDSR4.Bits.DB6
#define CAN0TXDSR4_DB7 _CAN0TXDSR4.Bits.DB7
#define CAN0TXDSR4_DB _CAN0TXDSR4.MergedBits.grpDB


/*** CAN0TXDSR5 - MSCAN 0 Transmit Data Segment Register 5; 0x00000179 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0TXDSR5STR;
extern volatile CAN0TXDSR5STR _CAN0TXDSR5 @(REG_BASE + 0x00000179);
#define CAN0TXDSR5 _CAN0TXDSR5.Byte
#define CAN0TXDSR5_DB0 _CAN0TXDSR5.Bits.DB0
#define CAN0TXDSR5_DB1 _CAN0TXDSR5.Bits.DB1
#define CAN0TXDSR5_DB2 _CAN0TXDSR5.Bits.DB2
#define CAN0TXDSR5_DB3 _CAN0TXDSR5.Bits.DB3
#define CAN0TXDSR5_DB4 _CAN0TXDSR5.Bits.DB4
#define CAN0TXDSR5_DB5 _CAN0TXDSR5.Bits.DB5
#define CAN0TXDSR5_DB6 _CAN0TXDSR5.Bits.DB6
#define CAN0TXDSR5_DB7 _CAN0TXDSR5.Bits.DB7
#define CAN0TXDSR5_DB _CAN0TXDSR5.MergedBits.grpDB


/*** CAN0TXDSR6 - MSCAN 0 Transmit Data Segment Register 6; 0x0000017A ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0TXDSR6STR;
extern volatile CAN0TXDSR6STR _CAN0TXDSR6 @(REG_BASE + 0x0000017A);
#define CAN0TXDSR6 _CAN0TXDSR6.Byte
#define CAN0TXDSR6_DB0 _CAN0TXDSR6.Bits.DB0
#define CAN0TXDSR6_DB1 _CAN0TXDSR6.Bits.DB1
#define CAN0TXDSR6_DB2 _CAN0TXDSR6.Bits.DB2
#define CAN0TXDSR6_DB3 _CAN0TXDSR6.Bits.DB3
#define CAN0TXDSR6_DB4 _CAN0TXDSR6.Bits.DB4
#define CAN0TXDSR6_DB5 _CAN0TXDSR6.Bits.DB5
#define CAN0TXDSR6_DB6 _CAN0TXDSR6.Bits.DB6
#define CAN0TXDSR6_DB7 _CAN0TXDSR6.Bits.DB7
#define CAN0TXDSR6_DB _CAN0TXDSR6.MergedBits.grpDB


/*** CAN0TXDSR7 - MSCAN 0 Transmit Data Segment Register 7; 0x0000017B ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN0TXDSR7STR;
extern volatile CAN0TXDSR7STR _CAN0TXDSR7 @(REG_BASE + 0x0000017B);
#define CAN0TXDSR7 _CAN0TXDSR7.Byte
#define CAN0TXDSR7_DB0 _CAN0TXDSR7.Bits.DB0
#define CAN0TXDSR7_DB1 _CAN0TXDSR7.Bits.DB1
#define CAN0TXDSR7_DB2 _CAN0TXDSR7.Bits.DB2
#define CAN0TXDSR7_DB3 _CAN0TXDSR7.Bits.DB3
#define CAN0TXDSR7_DB4 _CAN0TXDSR7.Bits.DB4
#define CAN0TXDSR7_DB5 _CAN0TXDSR7.Bits.DB5
#define CAN0TXDSR7_DB6 _CAN0TXDSR7.Bits.DB6
#define CAN0TXDSR7_DB7 _CAN0TXDSR7.Bits.DB7
#define CAN0TXDSR7_DB _CAN0TXDSR7.MergedBits.grpDB


/*** CAN0TXDLR - MSCAN 0 Transmit Data Length Register; 0x0000017C ***/
typedef union {
  byte Byte;
  struct {
    byte DLC0        :1;                                       /* Data Length Code Bit 0 */
    byte DLC1        :1;                                       /* Data Length Code Bit 1 */
    byte DLC2        :1;                                       /* Data Length Code Bit 2 */
    byte DLC3        :1;                                       /* Data Length Code Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDLC  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN0TXDLRSTR;
extern volatile CAN0TXDLRSTR _CAN0TXDLR @(REG_BASE + 0x0000017C);
#define CAN0TXDLR _CAN0TXDLR.Byte
#define CAN0TXDLR_DLC0 _CAN0TXDLR.Bits.DLC0
#define CAN0TXDLR_DLC1 _CAN0TXDLR.Bits.DLC1
#define CAN0TXDLR_DLC2 _CAN0TXDLR.Bits.DLC2
#define CAN0TXDLR_DLC3 _CAN0TXDLR.Bits.DLC3
#define CAN0TXDLR_DLC _CAN0TXDLR.MergedBits.grpDLC


/*** CAN0TXTBPR - MSCAN 0 Transmit Buffer Priority; 0x0000017F ***/
typedef union {
  byte Byte;
  struct {
    byte PRIO0       :1;                                       /* Transmit Buffer Priority Bit 0 */
    byte PRIO1       :1;                                       /* Transmit Buffer Priority Bit 1 */
    byte PRIO2       :1;                                       /* Transmit Buffer Priority Bit 2 */
    byte PRIO3       :1;                                       /* Transmit Buffer Priority Bit 3 */
    byte PRIO4       :1;                                       /* Transmit Buffer Priority Bit 4 */
    byte PRIO5       :1;                                       /* Transmit Buffer Priority Bit 5 */
    byte PRIO6       :1;                                       /* Transmit Buffer Priority Bit 6 */
    byte PRIO7       :1;                                       /* Transmit Buffer Priority Bit 7 */
  } Bits;
  struct {
    byte grpPRIO :8;
  } MergedBits;
} CAN0TXTBPRSTR;
extern volatile CAN0TXTBPRSTR _CAN0TXTBPR @(REG_BASE + 0x0000017F);
#define CAN0TXTBPR _CAN0TXTBPR.Byte
#define CAN0TXTBPR_PRIO0 _CAN0TXTBPR.Bits.PRIO0
#define CAN0TXTBPR_PRIO1 _CAN0TXTBPR.Bits.PRIO1
#define CAN0TXTBPR_PRIO2 _CAN0TXTBPR.Bits.PRIO2
#define CAN0TXTBPR_PRIO3 _CAN0TXTBPR.Bits.PRIO3
#define CAN0TXTBPR_PRIO4 _CAN0TXTBPR.Bits.PRIO4
#define CAN0TXTBPR_PRIO5 _CAN0TXTBPR.Bits.PRIO5
#define CAN0TXTBPR_PRIO6 _CAN0TXTBPR.Bits.PRIO6
#define CAN0TXTBPR_PRIO7 _CAN0TXTBPR.Bits.PRIO7
#define CAN0TXTBPR_PRIO _CAN0TXTBPR.MergedBits.grpPRIO


/*** CAN1CTL0 - MSCAN 1 Control 0 Register; 0x00000180 ***/
typedef union {
  byte Byte;
  struct {
    byte INITRQ      :1;                                       /* Initialization Mode Request */
    byte SLPRQ       :1;                                       /* Sleep Mode Request */
    byte WUPE        :1;                                       /* Wake-Up Enable */
    byte TIME        :1;                                       /* Timer Enable */
    byte SYNCH       :1;                                       /* Synchronized Status */
    byte CSWAI       :1;                                       /* CAN Stops in Wait Mode */
    byte RXACT       :1;                                       /* Receiver Active Status */
    byte RXFRM       :1;                                       /* Received Frame Flag */
  } Bits;
} CAN1CTL0STR;
extern volatile CAN1CTL0STR _CAN1CTL0 @(REG_BASE + 0x00000180);
#define CAN1CTL0 _CAN1CTL0.Byte
#define CAN1CTL0_INITRQ _CAN1CTL0.Bits.INITRQ
#define CAN1CTL0_SLPRQ _CAN1CTL0.Bits.SLPRQ
#define CAN1CTL0_WUPE _CAN1CTL0.Bits.WUPE
#define CAN1CTL0_TIME _CAN1CTL0.Bits.TIME
#define CAN1CTL0_SYNCH _CAN1CTL0.Bits.SYNCH
#define CAN1CTL0_CSWAI _CAN1CTL0.Bits.CSWAI
#define CAN1CTL0_RXACT _CAN1CTL0.Bits.RXACT
#define CAN1CTL0_RXFRM _CAN1CTL0.Bits.RXFRM


/*** CAN1CTL1 - MSCAN 1 Control 1 Register; 0x00000181 ***/
typedef union {
  byte Byte;
  struct {
    byte INITAK      :1;                                       /* Initialization Mode Acknowledge */
    byte SLPAK       :1;                                       /* Sleep Mode Acknowledge */
    byte WUPM        :1;                                       /* Wake-Up Mode */
    byte             :1; 
    byte LISTEN      :1;                                       /* Listen Only Mode */
    byte LOOPB       :1;                                       /* Loop Back Self Test Mode */
    byte CLKSRC      :1;                                       /* MSCAN 1 Clock Source */
    byte CANE        :1;                                       /* MSCAN 1 Enable */
  } Bits;
} CAN1CTL1STR;
extern volatile CAN1CTL1STR _CAN1CTL1 @(REG_BASE + 0x00000181);
#define CAN1CTL1 _CAN1CTL1.Byte
#define CAN1CTL1_INITAK _CAN1CTL1.Bits.INITAK
#define CAN1CTL1_SLPAK _CAN1CTL1.Bits.SLPAK
#define CAN1CTL1_WUPM _CAN1CTL1.Bits.WUPM
#define CAN1CTL1_LISTEN _CAN1CTL1.Bits.LISTEN
#define CAN1CTL1_LOOPB _CAN1CTL1.Bits.LOOPB
#define CAN1CTL1_CLKSRC _CAN1CTL1.Bits.CLKSRC
#define CAN1CTL1_CANE _CAN1CTL1.Bits.CANE


/*** CAN1BTR0 - MSCAN 1 Bus Timing Register 0; 0x00000182 ***/
typedef union {
  byte Byte;
  struct {
    byte BRP0        :1;                                       /* Baud Rate Prescaler 0 */
    byte BRP1        :1;                                       /* Baud Rate Prescaler 1 */
    byte BRP2        :1;                                       /* Baud Rate Prescaler 2 */
    byte BRP3        :1;                                       /* Baud Rate Prescaler 3 */
    byte BRP4        :1;                                       /* Baud Rate Prescaler 4 */
    byte BRP5        :1;                                       /* Baud Rate Prescaler 5 */
    byte SJW0        :1;                                       /* Synchronization Jump Width 0 */
    byte SJW1        :1;                                       /* Synchronization Jump Width 1 */
  } Bits;
  struct {
    byte grpBRP  :6;
    byte grpSJW  :2;
  } MergedBits;
} CAN1BTR0STR;
extern volatile CAN1BTR0STR _CAN1BTR0 @(REG_BASE + 0x00000182);
#define CAN1BTR0 _CAN1BTR0.Byte
#define CAN1BTR0_BRP0 _CAN1BTR0.Bits.BRP0
#define CAN1BTR0_BRP1 _CAN1BTR0.Bits.BRP1
#define CAN1BTR0_BRP2 _CAN1BTR0.Bits.BRP2
#define CAN1BTR0_BRP3 _CAN1BTR0.Bits.BRP3
#define CAN1BTR0_BRP4 _CAN1BTR0.Bits.BRP4
#define CAN1BTR0_BRP5 _CAN1BTR0.Bits.BRP5
#define CAN1BTR0_SJW0 _CAN1BTR0.Bits.SJW0
#define CAN1BTR0_SJW1 _CAN1BTR0.Bits.SJW1
#define CAN1BTR0_BRP _CAN1BTR0.MergedBits.grpBRP
#define CAN1BTR0_SJW _CAN1BTR0.MergedBits.grpSJW


/*** CAN1BTR1 - MSCAN 1 Bus Timing Register 1; 0x00000183 ***/
typedef union {
  byte Byte;
  struct {
    byte TSEG10      :1;                                       /* Time Segment 1 */
    byte TSEG11      :1;                                       /* Time Segment 1 */
    byte TSEG12      :1;                                       /* Time Segment 1 */
    byte TSEG13      :1;                                       /* Time Segment 1 */
    byte TSEG20      :1;                                       /* Time Segment 2 */
    byte TSEG21      :1;                                       /* Time Segment 2 */
    byte TSEG22      :1;                                       /* Time Segment 2 */
    byte SAMP        :1;                                       /* Sampling */
  } Bits;
  struct {
    byte grpTSEG_10 :4;
    byte grpTSEG_20 :3;
    byte         :1;
  } MergedBits;
} CAN1BTR1STR;
extern volatile CAN1BTR1STR _CAN1BTR1 @(REG_BASE + 0x00000183);
#define CAN1BTR1 _CAN1BTR1.Byte
#define CAN1BTR1_TSEG10 _CAN1BTR1.Bits.TSEG10
#define CAN1BTR1_TSEG11 _CAN1BTR1.Bits.TSEG11
#define CAN1BTR1_TSEG12 _CAN1BTR1.Bits.TSEG12
#define CAN1BTR1_TSEG13 _CAN1BTR1.Bits.TSEG13
#define CAN1BTR1_TSEG20 _CAN1BTR1.Bits.TSEG20
#define CAN1BTR1_TSEG21 _CAN1BTR1.Bits.TSEG21
#define CAN1BTR1_TSEG22 _CAN1BTR1.Bits.TSEG22
#define CAN1BTR1_SAMP _CAN1BTR1.Bits.SAMP
#define CAN1BTR1_TSEG_10 _CAN1BTR1.MergedBits.grpTSEG_10
#define CAN1BTR1_TSEG_20 _CAN1BTR1.MergedBits.grpTSEG_20
#define CAN1BTR1_TSEG CAN1BTR1_TSEG_10


/*** CAN1RFLG - MSCAN 1 Receiver Flag Register; 0x00000184 ***/
typedef union {
  byte Byte;
  struct {
    byte RXF         :1;                                       /* Receive Buffer Full */
    byte OVRIF       :1;                                       /* Overrun Interrupt Flag */
    byte TSTAT0      :1;                                       /* Transmitter Status Bit 0 */
    byte TSTAT1      :1;                                       /* Transmitter Status Bit 1 */
    byte RSTAT0      :1;                                       /* Receiver Status Bit 0 */
    byte RSTAT1      :1;                                       /* Receiver Status Bit 1 */
    byte CSCIF       :1;                                       /* CAN Status Change Interrupt Flag */
    byte WUPIF       :1;                                       /* Wake-up Interrupt Flag */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpTSTAT :2;
    byte grpRSTAT :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN1RFLGSTR;
extern volatile CAN1RFLGSTR _CAN1RFLG @(REG_BASE + 0x00000184);
#define CAN1RFLG _CAN1RFLG.Byte
#define CAN1RFLG_RXF _CAN1RFLG.Bits.RXF
#define CAN1RFLG_OVRIF _CAN1RFLG.Bits.OVRIF
#define CAN1RFLG_TSTAT0 _CAN1RFLG.Bits.TSTAT0
#define CAN1RFLG_TSTAT1 _CAN1RFLG.Bits.TSTAT1
#define CAN1RFLG_RSTAT0 _CAN1RFLG.Bits.RSTAT0
#define CAN1RFLG_RSTAT1 _CAN1RFLG.Bits.RSTAT1
#define CAN1RFLG_CSCIF _CAN1RFLG.Bits.CSCIF
#define CAN1RFLG_WUPIF _CAN1RFLG.Bits.WUPIF
#define CAN1RFLG_TSTAT _CAN1RFLG.MergedBits.grpTSTAT
#define CAN1RFLG_RSTAT _CAN1RFLG.MergedBits.grpRSTAT


/*** CAN1RIER - MSCAN 1 Receiver Interrupt Enable Register; 0x00000185 ***/
typedef union {
  byte Byte;
  struct {
    byte RXFIE       :1;                                       /* Receiver Full Interrupt Enable */
    byte OVRIE       :1;                                       /* Overrun Interrupt Enable */
    byte TSTATE0     :1;                                       /* Transmitter Status Change Enable 0 */
    byte TSTATE1     :1;                                       /* Transmitter Status Change Enable 1 */
    byte RSTATE0     :1;                                       /* Receiver Status Change Enable 0 */
    byte RSTATE1     :1;                                       /* Receiver Status Change Enable 1 */
    byte CSCIE       :1;                                       /* CAN Status Change Interrupt Enable */
    byte WUPIE       :1;                                       /* Wake-up Interrupt Enable */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpTSTATE :2;
    byte grpRSTATE :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN1RIERSTR;
extern volatile CAN1RIERSTR _CAN1RIER @(REG_BASE + 0x00000185);
#define CAN1RIER _CAN1RIER.Byte
#define CAN1RIER_RXFIE _CAN1RIER.Bits.RXFIE
#define CAN1RIER_OVRIE _CAN1RIER.Bits.OVRIE
#define CAN1RIER_TSTATE0 _CAN1RIER.Bits.TSTATE0
#define CAN1RIER_TSTATE1 _CAN1RIER.Bits.TSTATE1
#define CAN1RIER_RSTATE0 _CAN1RIER.Bits.RSTATE0
#define CAN1RIER_RSTATE1 _CAN1RIER.Bits.RSTATE1
#define CAN1RIER_CSCIE _CAN1RIER.Bits.CSCIE
#define CAN1RIER_WUPIE _CAN1RIER.Bits.WUPIE
#define CAN1RIER_TSTATE _CAN1RIER.MergedBits.grpTSTATE
#define CAN1RIER_RSTATE _CAN1RIER.MergedBits.grpRSTATE


/*** CAN1TFLG - MSCAN 1 Transmitter Flag Register; 0x00000186 ***/
typedef union {
  byte Byte;
  struct {
    byte TXE0        :1;                                       /* Transmitter Buffer Empty 0 */
    byte TXE1        :1;                                       /* Transmitter Buffer Empty 1 */
    byte TXE2        :1;                                       /* Transmitter Buffer Empty 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTXE  :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN1TFLGSTR;
extern volatile CAN1TFLGSTR _CAN1TFLG @(REG_BASE + 0x00000186);
#define CAN1TFLG _CAN1TFLG.Byte
#define CAN1TFLG_TXE0 _CAN1TFLG.Bits.TXE0
#define CAN1TFLG_TXE1 _CAN1TFLG.Bits.TXE1
#define CAN1TFLG_TXE2 _CAN1TFLG.Bits.TXE2
#define CAN1TFLG_TXE _CAN1TFLG.MergedBits.grpTXE


/*** CAN1TIER - MSCAN 1 Transmitter Interrupt Enable Register; 0x00000187 ***/
typedef union {
  byte Byte;
  struct {
    byte TXEIE0      :1;                                       /* Transmitter Empty Interrupt Enable 0 */
    byte TXEIE1      :1;                                       /* Transmitter Empty Interrupt Enable 1 */
    byte TXEIE2      :1;                                       /* Transmitter Empty Interrupt Enable 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTXEIE :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN1TIERSTR;
extern volatile CAN1TIERSTR _CAN1TIER @(REG_BASE + 0x00000187);
#define CAN1TIER _CAN1TIER.Byte
#define CAN1TIER_TXEIE0 _CAN1TIER.Bits.TXEIE0
#define CAN1TIER_TXEIE1 _CAN1TIER.Bits.TXEIE1
#define CAN1TIER_TXEIE2 _CAN1TIER.Bits.TXEIE2
#define CAN1TIER_TXEIE _CAN1TIER.MergedBits.grpTXEIE


/*** CAN1TARQ - MSCAN 1 Transmitter Message Abort Request; 0x00000188 ***/
typedef union {
  byte Byte;
  struct {
    byte ABTRQ0      :1;                                       /* Abort Request 0 */
    byte ABTRQ1      :1;                                       /* Abort Request 1 */
    byte ABTRQ2      :1;                                       /* Abort Request 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpABTRQ :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN1TARQSTR;
extern volatile CAN1TARQSTR _CAN1TARQ @(REG_BASE + 0x00000188);
#define CAN1TARQ _CAN1TARQ.Byte
#define CAN1TARQ_ABTRQ0 _CAN1TARQ.Bits.ABTRQ0
#define CAN1TARQ_ABTRQ1 _CAN1TARQ.Bits.ABTRQ1
#define CAN1TARQ_ABTRQ2 _CAN1TARQ.Bits.ABTRQ2
#define CAN1TARQ_ABTRQ _CAN1TARQ.MergedBits.grpABTRQ


/*** CAN1TAAK - MSCAN 1 Transmitter Message Abort Control; 0x00000189 ***/
typedef union {
  byte Byte;
  struct {
    byte ABTAK0      :1;                                       /* Abort Acknowledge 0 */
    byte ABTAK1      :1;                                       /* Abort Acknowledge 1 */
    byte ABTAK2      :1;                                       /* Abort Acknowledge 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpABTAK :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN1TAAKSTR;
extern volatile CAN1TAAKSTR _CAN1TAAK @(REG_BASE + 0x00000189);
#define CAN1TAAK _CAN1TAAK.Byte
#define CAN1TAAK_ABTAK0 _CAN1TAAK.Bits.ABTAK0
#define CAN1TAAK_ABTAK1 _CAN1TAAK.Bits.ABTAK1
#define CAN1TAAK_ABTAK2 _CAN1TAAK.Bits.ABTAK2
#define CAN1TAAK_ABTAK _CAN1TAAK.MergedBits.grpABTAK


/*** CAN1TBSEL - MSCAN 1 Transmit Buffer Selection; 0x0000018A ***/
typedef union {
  byte Byte;
  struct {
    byte TX0         :1;                                       /* Transmit Buffer Select 0 */
    byte TX1         :1;                                       /* Transmit Buffer Select 1 */
    byte TX2         :1;                                       /* Transmit Buffer Select 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTX   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN1TBSELSTR;
extern volatile CAN1TBSELSTR _CAN1TBSEL @(REG_BASE + 0x0000018A);
#define CAN1TBSEL _CAN1TBSEL.Byte
#define CAN1TBSEL_TX0 _CAN1TBSEL.Bits.TX0
#define CAN1TBSEL_TX1 _CAN1TBSEL.Bits.TX1
#define CAN1TBSEL_TX2 _CAN1TBSEL.Bits.TX2
#define CAN1TBSEL_TX _CAN1TBSEL.MergedBits.grpTX


/*** CAN1IDAC - MSCAN 1 Identifier Acceptance Control Register; 0x0000018B ***/
typedef union {
  byte Byte;
  struct {
    byte IDHIT0      :1;                                       /* Identifier Acceptance Hit Indicator 0 */
    byte IDHIT1      :1;                                       /* Identifier Acceptance Hit Indicator 1 */
    byte IDHIT2      :1;                                       /* Identifier Acceptance Hit Indicator 2 */
    byte             :1; 
    byte IDAM0       :1;                                       /* Identifier Acceptance Mode 0 */
    byte IDAM1       :1;                                       /* Identifier Acceptance Mode 1 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpIDHIT :3;
    byte         :1;
    byte grpIDAM :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN1IDACSTR;
extern volatile CAN1IDACSTR _CAN1IDAC @(REG_BASE + 0x0000018B);
#define CAN1IDAC _CAN1IDAC.Byte
#define CAN1IDAC_IDHIT0 _CAN1IDAC.Bits.IDHIT0
#define CAN1IDAC_IDHIT1 _CAN1IDAC.Bits.IDHIT1
#define CAN1IDAC_IDHIT2 _CAN1IDAC.Bits.IDHIT2
#define CAN1IDAC_IDAM0 _CAN1IDAC.Bits.IDAM0
#define CAN1IDAC_IDAM1 _CAN1IDAC.Bits.IDAM1
#define CAN1IDAC_IDHIT _CAN1IDAC.MergedBits.grpIDHIT
#define CAN1IDAC_IDAM _CAN1IDAC.MergedBits.grpIDAM


/*** CAN1RXERR - MSCAN 1 Receive Error Counter Register; 0x0000018E ***/
typedef union {
  byte Byte;
  struct {
    byte RXERR0      :1;                                       /* Bit 0 */
    byte RXERR1      :1;                                       /* Bit 1 */
    byte RXERR2      :1;                                       /* Bit 2 */
    byte RXERR3      :1;                                       /* Bit 3 */
    byte RXERR4      :1;                                       /* Bit 4 */
    byte RXERR5      :1;                                       /* Bit 5 */
    byte RXERR6      :1;                                       /* Bit 6 */
    byte RXERR7      :1;                                       /* Bit 7 */
  } Bits;
  struct {
    byte grpRXERR :8;
  } MergedBits;
} CAN1RXERRSTR;
extern volatile CAN1RXERRSTR _CAN1RXERR @(REG_BASE + 0x0000018E);
#define CAN1RXERR _CAN1RXERR.Byte
#define CAN1RXERR_RXERR0 _CAN1RXERR.Bits.RXERR0
#define CAN1RXERR_RXERR1 _CAN1RXERR.Bits.RXERR1
#define CAN1RXERR_RXERR2 _CAN1RXERR.Bits.RXERR2
#define CAN1RXERR_RXERR3 _CAN1RXERR.Bits.RXERR3
#define CAN1RXERR_RXERR4 _CAN1RXERR.Bits.RXERR4
#define CAN1RXERR_RXERR5 _CAN1RXERR.Bits.RXERR5
#define CAN1RXERR_RXERR6 _CAN1RXERR.Bits.RXERR6
#define CAN1RXERR_RXERR7 _CAN1RXERR.Bits.RXERR7
#define CAN1RXERR_RXERR _CAN1RXERR.MergedBits.grpRXERR


/*** CAN1TXERR - MSCAN 1 Transmit Error Counter Register; 0x0000018F ***/
typedef union {
  byte Byte;
  struct {
    byte TXERR0      :1;                                       /* Bit 0 */
    byte TXERR1      :1;                                       /* Bit 1 */
    byte TXERR2      :1;                                       /* Bit 2 */
    byte TXERR3      :1;                                       /* Bit 3 */
    byte TXERR4      :1;                                       /* Bit 4 */
    byte TXERR5      :1;                                       /* Bit 5 */
    byte TXERR6      :1;                                       /* Bit 6 */
    byte TXERR7      :1;                                       /* Bit 7 */
  } Bits;
  struct {
    byte grpTXERR :8;
  } MergedBits;
} CAN1TXERRSTR;
extern volatile CAN1TXERRSTR _CAN1TXERR @(REG_BASE + 0x0000018F);
#define CAN1TXERR _CAN1TXERR.Byte
#define CAN1TXERR_TXERR0 _CAN1TXERR.Bits.TXERR0
#define CAN1TXERR_TXERR1 _CAN1TXERR.Bits.TXERR1
#define CAN1TXERR_TXERR2 _CAN1TXERR.Bits.TXERR2
#define CAN1TXERR_TXERR3 _CAN1TXERR.Bits.TXERR3
#define CAN1TXERR_TXERR4 _CAN1TXERR.Bits.TXERR4
#define CAN1TXERR_TXERR5 _CAN1TXERR.Bits.TXERR5
#define CAN1TXERR_TXERR6 _CAN1TXERR.Bits.TXERR6
#define CAN1TXERR_TXERR7 _CAN1TXERR.Bits.TXERR7
#define CAN1TXERR_TXERR _CAN1TXERR.MergedBits.grpTXERR


/*** CAN1IDAR0 - MSCAN 1 Identifier Acceptance Register 0; 0x00000190 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN1IDAR0STR;
extern volatile CAN1IDAR0STR _CAN1IDAR0 @(REG_BASE + 0x00000190);
#define CAN1IDAR0 _CAN1IDAR0.Byte
#define CAN1IDAR0_AC0 _CAN1IDAR0.Bits.AC0
#define CAN1IDAR0_AC1 _CAN1IDAR0.Bits.AC1
#define CAN1IDAR0_AC2 _CAN1IDAR0.Bits.AC2
#define CAN1IDAR0_AC3 _CAN1IDAR0.Bits.AC3
#define CAN1IDAR0_AC4 _CAN1IDAR0.Bits.AC4
#define CAN1IDAR0_AC5 _CAN1IDAR0.Bits.AC5
#define CAN1IDAR0_AC6 _CAN1IDAR0.Bits.AC6
#define CAN1IDAR0_AC7 _CAN1IDAR0.Bits.AC7
#define CAN1IDAR0_AC _CAN1IDAR0.MergedBits.grpAC


/*** CAN1IDAR1 - MSCAN 1 Identifier Acceptance Register 1; 0x00000191 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN1IDAR1STR;
extern volatile CAN1IDAR1STR _CAN1IDAR1 @(REG_BASE + 0x00000191);
#define CAN1IDAR1 _CAN1IDAR1.Byte
#define CAN1IDAR1_AC0 _CAN1IDAR1.Bits.AC0
#define CAN1IDAR1_AC1 _CAN1IDAR1.Bits.AC1
#define CAN1IDAR1_AC2 _CAN1IDAR1.Bits.AC2
#define CAN1IDAR1_AC3 _CAN1IDAR1.Bits.AC3
#define CAN1IDAR1_AC4 _CAN1IDAR1.Bits.AC4
#define CAN1IDAR1_AC5 _CAN1IDAR1.Bits.AC5
#define CAN1IDAR1_AC6 _CAN1IDAR1.Bits.AC6
#define CAN1IDAR1_AC7 _CAN1IDAR1.Bits.AC7
#define CAN1IDAR1_AC _CAN1IDAR1.MergedBits.grpAC


/*** CAN1IDAR2 - MSCAN 1 Identifier Acceptance Register 2; 0x00000192 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN1IDAR2STR;
extern volatile CAN1IDAR2STR _CAN1IDAR2 @(REG_BASE + 0x00000192);
#define CAN1IDAR2 _CAN1IDAR2.Byte
#define CAN1IDAR2_AC0 _CAN1IDAR2.Bits.AC0
#define CAN1IDAR2_AC1 _CAN1IDAR2.Bits.AC1
#define CAN1IDAR2_AC2 _CAN1IDAR2.Bits.AC2
#define CAN1IDAR2_AC3 _CAN1IDAR2.Bits.AC3
#define CAN1IDAR2_AC4 _CAN1IDAR2.Bits.AC4
#define CAN1IDAR2_AC5 _CAN1IDAR2.Bits.AC5
#define CAN1IDAR2_AC6 _CAN1IDAR2.Bits.AC6
#define CAN1IDAR2_AC7 _CAN1IDAR2.Bits.AC7
#define CAN1IDAR2_AC _CAN1IDAR2.MergedBits.grpAC


/*** CAN1IDAR3 - MSCAN 1 Identifier Acceptance Register 3; 0x00000193 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN1IDAR3STR;
extern volatile CAN1IDAR3STR _CAN1IDAR3 @(REG_BASE + 0x00000193);
#define CAN1IDAR3 _CAN1IDAR3.Byte
#define CAN1IDAR3_AC0 _CAN1IDAR3.Bits.AC0
#define CAN1IDAR3_AC1 _CAN1IDAR3.Bits.AC1
#define CAN1IDAR3_AC2 _CAN1IDAR3.Bits.AC2
#define CAN1IDAR3_AC3 _CAN1IDAR3.Bits.AC3
#define CAN1IDAR3_AC4 _CAN1IDAR3.Bits.AC4
#define CAN1IDAR3_AC5 _CAN1IDAR3.Bits.AC5
#define CAN1IDAR3_AC6 _CAN1IDAR3.Bits.AC6
#define CAN1IDAR3_AC7 _CAN1IDAR3.Bits.AC7
#define CAN1IDAR3_AC _CAN1IDAR3.MergedBits.grpAC


/*** CAN1IDMR0 - MSCAN 1 Identifier Mask Register 0; 0x00000194 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN1IDMR0STR;
extern volatile CAN1IDMR0STR _CAN1IDMR0 @(REG_BASE + 0x00000194);
#define CAN1IDMR0 _CAN1IDMR0.Byte
#define CAN1IDMR0_AM0 _CAN1IDMR0.Bits.AM0
#define CAN1IDMR0_AM1 _CAN1IDMR0.Bits.AM1
#define CAN1IDMR0_AM2 _CAN1IDMR0.Bits.AM2
#define CAN1IDMR0_AM3 _CAN1IDMR0.Bits.AM3
#define CAN1IDMR0_AM4 _CAN1IDMR0.Bits.AM4
#define CAN1IDMR0_AM5 _CAN1IDMR0.Bits.AM5
#define CAN1IDMR0_AM6 _CAN1IDMR0.Bits.AM6
#define CAN1IDMR0_AM7 _CAN1IDMR0.Bits.AM7
#define CAN1IDMR0_AM _CAN1IDMR0.MergedBits.grpAM


/*** CAN1IDMR1 - MSCAN 1 Identifier Mask Register 1; 0x00000195 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN1IDMR1STR;
extern volatile CAN1IDMR1STR _CAN1IDMR1 @(REG_BASE + 0x00000195);
#define CAN1IDMR1 _CAN1IDMR1.Byte
#define CAN1IDMR1_AM0 _CAN1IDMR1.Bits.AM0
#define CAN1IDMR1_AM1 _CAN1IDMR1.Bits.AM1
#define CAN1IDMR1_AM2 _CAN1IDMR1.Bits.AM2
#define CAN1IDMR1_AM3 _CAN1IDMR1.Bits.AM3
#define CAN1IDMR1_AM4 _CAN1IDMR1.Bits.AM4
#define CAN1IDMR1_AM5 _CAN1IDMR1.Bits.AM5
#define CAN1IDMR1_AM6 _CAN1IDMR1.Bits.AM6
#define CAN1IDMR1_AM7 _CAN1IDMR1.Bits.AM7
#define CAN1IDMR1_AM _CAN1IDMR1.MergedBits.grpAM


/*** CAN1IDMR2 - MSCAN 1 Identifier Mask Register 2; 0x00000196 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN1IDMR2STR;
extern volatile CAN1IDMR2STR _CAN1IDMR2 @(REG_BASE + 0x00000196);
#define CAN1IDMR2 _CAN1IDMR2.Byte
#define CAN1IDMR2_AM0 _CAN1IDMR2.Bits.AM0
#define CAN1IDMR2_AM1 _CAN1IDMR2.Bits.AM1
#define CAN1IDMR2_AM2 _CAN1IDMR2.Bits.AM2
#define CAN1IDMR2_AM3 _CAN1IDMR2.Bits.AM3
#define CAN1IDMR2_AM4 _CAN1IDMR2.Bits.AM4
#define CAN1IDMR2_AM5 _CAN1IDMR2.Bits.AM5
#define CAN1IDMR2_AM6 _CAN1IDMR2.Bits.AM6
#define CAN1IDMR2_AM7 _CAN1IDMR2.Bits.AM7
#define CAN1IDMR2_AM _CAN1IDMR2.MergedBits.grpAM


/*** CAN1IDMR3 - MSCAN 1 Identifier Mask Register 3; 0x00000197 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN1IDMR3STR;
extern volatile CAN1IDMR3STR _CAN1IDMR3 @(REG_BASE + 0x00000197);
#define CAN1IDMR3 _CAN1IDMR3.Byte
#define CAN1IDMR3_AM0 _CAN1IDMR3.Bits.AM0
#define CAN1IDMR3_AM1 _CAN1IDMR3.Bits.AM1
#define CAN1IDMR3_AM2 _CAN1IDMR3.Bits.AM2
#define CAN1IDMR3_AM3 _CAN1IDMR3.Bits.AM3
#define CAN1IDMR3_AM4 _CAN1IDMR3.Bits.AM4
#define CAN1IDMR3_AM5 _CAN1IDMR3.Bits.AM5
#define CAN1IDMR3_AM6 _CAN1IDMR3.Bits.AM6
#define CAN1IDMR3_AM7 _CAN1IDMR3.Bits.AM7
#define CAN1IDMR3_AM _CAN1IDMR3.MergedBits.grpAM


/*** CAN1IDAR4 - MSCAN 1 Identifier Acceptance Register 4; 0x00000198 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN1IDAR4STR;
extern volatile CAN1IDAR4STR _CAN1IDAR4 @(REG_BASE + 0x00000198);
#define CAN1IDAR4 _CAN1IDAR4.Byte
#define CAN1IDAR4_AC0 _CAN1IDAR4.Bits.AC0
#define CAN1IDAR4_AC1 _CAN1IDAR4.Bits.AC1
#define CAN1IDAR4_AC2 _CAN1IDAR4.Bits.AC2
#define CAN1IDAR4_AC3 _CAN1IDAR4.Bits.AC3
#define CAN1IDAR4_AC4 _CAN1IDAR4.Bits.AC4
#define CAN1IDAR4_AC5 _CAN1IDAR4.Bits.AC5
#define CAN1IDAR4_AC6 _CAN1IDAR4.Bits.AC6
#define CAN1IDAR4_AC7 _CAN1IDAR4.Bits.AC7
#define CAN1IDAR4_AC _CAN1IDAR4.MergedBits.grpAC


/*** CAN1IDAR5 - MSCAN 1 Identifier Acceptance Register 5; 0x00000199 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN1IDAR5STR;
extern volatile CAN1IDAR5STR _CAN1IDAR5 @(REG_BASE + 0x00000199);
#define CAN1IDAR5 _CAN1IDAR5.Byte
#define CAN1IDAR5_AC0 _CAN1IDAR5.Bits.AC0
#define CAN1IDAR5_AC1 _CAN1IDAR5.Bits.AC1
#define CAN1IDAR5_AC2 _CAN1IDAR5.Bits.AC2
#define CAN1IDAR5_AC3 _CAN1IDAR5.Bits.AC3
#define CAN1IDAR5_AC4 _CAN1IDAR5.Bits.AC4
#define CAN1IDAR5_AC5 _CAN1IDAR5.Bits.AC5
#define CAN1IDAR5_AC6 _CAN1IDAR5.Bits.AC6
#define CAN1IDAR5_AC7 _CAN1IDAR5.Bits.AC7
#define CAN1IDAR5_AC _CAN1IDAR5.MergedBits.grpAC


/*** CAN1IDAR6 - MSCAN 1 Identifier Acceptance Register 6; 0x0000019A ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN1IDAR6STR;
extern volatile CAN1IDAR6STR _CAN1IDAR6 @(REG_BASE + 0x0000019A);
#define CAN1IDAR6 _CAN1IDAR6.Byte
#define CAN1IDAR6_AC0 _CAN1IDAR6.Bits.AC0
#define CAN1IDAR6_AC1 _CAN1IDAR6.Bits.AC1
#define CAN1IDAR6_AC2 _CAN1IDAR6.Bits.AC2
#define CAN1IDAR6_AC3 _CAN1IDAR6.Bits.AC3
#define CAN1IDAR6_AC4 _CAN1IDAR6.Bits.AC4
#define CAN1IDAR6_AC5 _CAN1IDAR6.Bits.AC5
#define CAN1IDAR6_AC6 _CAN1IDAR6.Bits.AC6
#define CAN1IDAR6_AC7 _CAN1IDAR6.Bits.AC7
#define CAN1IDAR6_AC _CAN1IDAR6.MergedBits.grpAC


/*** CAN1IDAR7 - MSCAN 1 Identifier Acceptance Register 7; 0x0000019B ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN1IDAR7STR;
extern volatile CAN1IDAR7STR _CAN1IDAR7 @(REG_BASE + 0x0000019B);
#define CAN1IDAR7 _CAN1IDAR7.Byte
#define CAN1IDAR7_AC0 _CAN1IDAR7.Bits.AC0
#define CAN1IDAR7_AC1 _CAN1IDAR7.Bits.AC1
#define CAN1IDAR7_AC2 _CAN1IDAR7.Bits.AC2
#define CAN1IDAR7_AC3 _CAN1IDAR7.Bits.AC3
#define CAN1IDAR7_AC4 _CAN1IDAR7.Bits.AC4
#define CAN1IDAR7_AC5 _CAN1IDAR7.Bits.AC5
#define CAN1IDAR7_AC6 _CAN1IDAR7.Bits.AC6
#define CAN1IDAR7_AC7 _CAN1IDAR7.Bits.AC7
#define CAN1IDAR7_AC _CAN1IDAR7.MergedBits.grpAC


/*** CAN1IDMR4 - MSCAN 1 Identifier Mask Register 4; 0x0000019C ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN1IDMR4STR;
extern volatile CAN1IDMR4STR _CAN1IDMR4 @(REG_BASE + 0x0000019C);
#define CAN1IDMR4 _CAN1IDMR4.Byte
#define CAN1IDMR4_AM0 _CAN1IDMR4.Bits.AM0
#define CAN1IDMR4_AM1 _CAN1IDMR4.Bits.AM1
#define CAN1IDMR4_AM2 _CAN1IDMR4.Bits.AM2
#define CAN1IDMR4_AM3 _CAN1IDMR4.Bits.AM3
#define CAN1IDMR4_AM4 _CAN1IDMR4.Bits.AM4
#define CAN1IDMR4_AM5 _CAN1IDMR4.Bits.AM5
#define CAN1IDMR4_AM6 _CAN1IDMR4.Bits.AM6
#define CAN1IDMR4_AM7 _CAN1IDMR4.Bits.AM7
#define CAN1IDMR4_AM _CAN1IDMR4.MergedBits.grpAM


/*** CAN1IDMR5 - MSCAN 1 Identifier Mask Register 5; 0x0000019D ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN1IDMR5STR;
extern volatile CAN1IDMR5STR _CAN1IDMR5 @(REG_BASE + 0x0000019D);
#define CAN1IDMR5 _CAN1IDMR5.Byte
#define CAN1IDMR5_AM0 _CAN1IDMR5.Bits.AM0
#define CAN1IDMR5_AM1 _CAN1IDMR5.Bits.AM1
#define CAN1IDMR5_AM2 _CAN1IDMR5.Bits.AM2
#define CAN1IDMR5_AM3 _CAN1IDMR5.Bits.AM3
#define CAN1IDMR5_AM4 _CAN1IDMR5.Bits.AM4
#define CAN1IDMR5_AM5 _CAN1IDMR5.Bits.AM5
#define CAN1IDMR5_AM6 _CAN1IDMR5.Bits.AM6
#define CAN1IDMR5_AM7 _CAN1IDMR5.Bits.AM7
#define CAN1IDMR5_AM _CAN1IDMR5.MergedBits.grpAM


/*** CAN1IDMR6 - MSCAN 1 Identifier Mask Register 6; 0x0000019E ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN1IDMR6STR;
extern volatile CAN1IDMR6STR _CAN1IDMR6 @(REG_BASE + 0x0000019E);
#define CAN1IDMR6 _CAN1IDMR6.Byte
#define CAN1IDMR6_AM0 _CAN1IDMR6.Bits.AM0
#define CAN1IDMR6_AM1 _CAN1IDMR6.Bits.AM1
#define CAN1IDMR6_AM2 _CAN1IDMR6.Bits.AM2
#define CAN1IDMR6_AM3 _CAN1IDMR6.Bits.AM3
#define CAN1IDMR6_AM4 _CAN1IDMR6.Bits.AM4
#define CAN1IDMR6_AM5 _CAN1IDMR6.Bits.AM5
#define CAN1IDMR6_AM6 _CAN1IDMR6.Bits.AM6
#define CAN1IDMR6_AM7 _CAN1IDMR6.Bits.AM7
#define CAN1IDMR6_AM _CAN1IDMR6.MergedBits.grpAM


/*** CAN1IDMR7 - MSCAN 1 Identifier Mask Register 7; 0x0000019F ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN1IDMR7STR;
extern volatile CAN1IDMR7STR _CAN1IDMR7 @(REG_BASE + 0x0000019F);
#define CAN1IDMR7 _CAN1IDMR7.Byte
#define CAN1IDMR7_AM0 _CAN1IDMR7.Bits.AM0
#define CAN1IDMR7_AM1 _CAN1IDMR7.Bits.AM1
#define CAN1IDMR7_AM2 _CAN1IDMR7.Bits.AM2
#define CAN1IDMR7_AM3 _CAN1IDMR7.Bits.AM3
#define CAN1IDMR7_AM4 _CAN1IDMR7.Bits.AM4
#define CAN1IDMR7_AM5 _CAN1IDMR7.Bits.AM5
#define CAN1IDMR7_AM6 _CAN1IDMR7.Bits.AM6
#define CAN1IDMR7_AM7 _CAN1IDMR7.Bits.AM7
#define CAN1IDMR7_AM _CAN1IDMR7.MergedBits.grpAM


/*** CAN1RXIDR0 - MSCAN 1 Receive Identifier Register 0; 0x000001A0 ***/
typedef union {
  byte Byte;
  struct {
    byte ID21        :1;                                       /* Extended format identifier Bit 21 */
    byte ID22        :1;                                       /* Extended format identifier Bit 22 */
    byte ID23        :1;                                       /* Extended format identifier Bit 23 */
    byte ID24        :1;                                       /* Extended format identifier Bit 24 */
    byte ID25        :1;                                       /* Extended format identifier Bit 25 */
    byte ID26        :1;                                       /* Extended format identifier Bit 26 */
    byte ID27        :1;                                       /* Extended format identifier Bit 27 */
    byte ID28        :1;                                       /* Extended format identifier Bit 28 */
  } Bits;
  struct {
    byte grpID_21 :8;
  } MergedBits;
} CAN1RXIDR0STR;
extern volatile CAN1RXIDR0STR _CAN1RXIDR0 @(REG_BASE + 0x000001A0);
#define CAN1RXIDR0 _CAN1RXIDR0.Byte
#define CAN1RXIDR0_ID21 _CAN1RXIDR0.Bits.ID21
#define CAN1RXIDR0_ID22 _CAN1RXIDR0.Bits.ID22
#define CAN1RXIDR0_ID23 _CAN1RXIDR0.Bits.ID23
#define CAN1RXIDR0_ID24 _CAN1RXIDR0.Bits.ID24
#define CAN1RXIDR0_ID25 _CAN1RXIDR0.Bits.ID25
#define CAN1RXIDR0_ID26 _CAN1RXIDR0.Bits.ID26
#define CAN1RXIDR0_ID27 _CAN1RXIDR0.Bits.ID27
#define CAN1RXIDR0_ID28 _CAN1RXIDR0.Bits.ID28
#define CAN1RXIDR0_ID_21 _CAN1RXIDR0.MergedBits.grpID_21
#define CAN1RXIDR0_ID CAN1RXIDR0_ID_21


/*** CAN1RXIDR1 - MSCAN 1 Receive Identifier Register 1; 0x000001A1 ***/
typedef union {
  byte Byte;
  struct {
    byte ID15        :1;                                       /* Extended format identifier Bit 15 */
    byte ID16        :1;                                       /* Extended format identifier Bit 16 */
    byte ID17        :1;                                       /* Extended format identifier Bit 17 */
    byte IDE         :1;                                       /* ID Extended */
    byte SRR         :1;                                       /* Substitute Remote Request */
    byte ID18        :1;                                       /* Extended format identifier Bit 18 */
    byte ID19        :1;                                       /* Extended format identifier Bit 19 */
    byte ID20        :1;                                       /* Extended format identifier Bit 20 */
  } Bits;
  struct {
    byte grpID_15 :3;
    byte         :1;
    byte         :1;
    byte grpID_18 :3;
  } MergedBits;
} CAN1RXIDR1STR;
extern volatile CAN1RXIDR1STR _CAN1RXIDR1 @(REG_BASE + 0x000001A1);
#define CAN1RXIDR1 _CAN1RXIDR1.Byte
#define CAN1RXIDR1_ID15 _CAN1RXIDR1.Bits.ID15
#define CAN1RXIDR1_ID16 _CAN1RXIDR1.Bits.ID16
#define CAN1RXIDR1_ID17 _CAN1RXIDR1.Bits.ID17
#define CAN1RXIDR1_IDE _CAN1RXIDR1.Bits.IDE
#define CAN1RXIDR1_SRR _CAN1RXIDR1.Bits.SRR
#define CAN1RXIDR1_ID18 _CAN1RXIDR1.Bits.ID18
#define CAN1RXIDR1_ID19 _CAN1RXIDR1.Bits.ID19
#define CAN1RXIDR1_ID20 _CAN1RXIDR1.Bits.ID20
#define CAN1RXIDR1_ID_15 _CAN1RXIDR1.MergedBits.grpID_15
#define CAN1RXIDR1_ID_18 _CAN1RXIDR1.MergedBits.grpID_18
#define CAN1RXIDR1_ID CAN1RXIDR1_ID_15


/*** CAN1RXIDR2 - MSCAN 1 Receive Identifier Register 2; 0x000001A2 ***/
typedef union {
  byte Byte;
  struct {
    byte ID7         :1;                                       /* Extended format identifier Bit 7 */
    byte ID8         :1;                                       /* Extended format identifier Bit 8 */
    byte ID9         :1;                                       /* Extended format identifier Bit 9 */
    byte ID10        :1;                                       /* Extended format identifier Bit 10 */
    byte ID11        :1;                                       /* Extended format identifier Bit 11 */
    byte ID12        :1;                                       /* Extended format identifier Bit 12 */
    byte ID13        :1;                                       /* Extended format identifier Bit 13 */
    byte ID14        :1;                                       /* Extended format identifier Bit 14 */
  } Bits;
  struct {
    byte grpID_7 :8;
  } MergedBits;
} CAN1RXIDR2STR;
extern volatile CAN1RXIDR2STR _CAN1RXIDR2 @(REG_BASE + 0x000001A2);
#define CAN1RXIDR2 _CAN1RXIDR2.Byte
#define CAN1RXIDR2_ID7 _CAN1RXIDR2.Bits.ID7
#define CAN1RXIDR2_ID8 _CAN1RXIDR2.Bits.ID8
#define CAN1RXIDR2_ID9 _CAN1RXIDR2.Bits.ID9
#define CAN1RXIDR2_ID10 _CAN1RXIDR2.Bits.ID10
#define CAN1RXIDR2_ID11 _CAN1RXIDR2.Bits.ID11
#define CAN1RXIDR2_ID12 _CAN1RXIDR2.Bits.ID12
#define CAN1RXIDR2_ID13 _CAN1RXIDR2.Bits.ID13
#define CAN1RXIDR2_ID14 _CAN1RXIDR2.Bits.ID14
#define CAN1RXIDR2_ID_7 _CAN1RXIDR2.MergedBits.grpID_7
#define CAN1RXIDR2_ID CAN1RXIDR2_ID_7


/*** CAN1RXIDR3 - MSCAN 1 Receive Identifier Register 3; 0x000001A3 ***/
typedef union {
  byte Byte;
  struct {
    byte RTR         :1;                                       /* Remote Transmission Request */
    byte ID0         :1;                                       /* Extended format identifier Bit 0 */
    byte ID1         :1;                                       /* Extended format identifier Bit 1 */
    byte ID2         :1;                                       /* Extended format identifier Bit 2 */
    byte ID3         :1;                                       /* Extended format identifier Bit 3 */
    byte ID4         :1;                                       /* Extended format identifier Bit 4 */
    byte ID5         :1;                                       /* Extended format identifier Bit 5 */
    byte ID6         :1;                                       /* Extended format identifier Bit 6 */
  } Bits;
  struct {
    byte         :1;
    byte grpID   :7;
  } MergedBits;
} CAN1RXIDR3STR;
extern volatile CAN1RXIDR3STR _CAN1RXIDR3 @(REG_BASE + 0x000001A3);
#define CAN1RXIDR3 _CAN1RXIDR3.Byte
#define CAN1RXIDR3_RTR _CAN1RXIDR3.Bits.RTR
#define CAN1RXIDR3_ID0 _CAN1RXIDR3.Bits.ID0
#define CAN1RXIDR3_ID1 _CAN1RXIDR3.Bits.ID1
#define CAN1RXIDR3_ID2 _CAN1RXIDR3.Bits.ID2
#define CAN1RXIDR3_ID3 _CAN1RXIDR3.Bits.ID3
#define CAN1RXIDR3_ID4 _CAN1RXIDR3.Bits.ID4
#define CAN1RXIDR3_ID5 _CAN1RXIDR3.Bits.ID5
#define CAN1RXIDR3_ID6 _CAN1RXIDR3.Bits.ID6
#define CAN1RXIDR3_ID _CAN1RXIDR3.MergedBits.grpID


/*** CAN1RXDSR0 - MSCAN 1 Receive Data Segment Register 0; 0x000001A4 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1RXDSR0STR;
extern volatile CAN1RXDSR0STR _CAN1RXDSR0 @(REG_BASE + 0x000001A4);
#define CAN1RXDSR0 _CAN1RXDSR0.Byte
#define CAN1RXDSR0_DB0 _CAN1RXDSR0.Bits.DB0
#define CAN1RXDSR0_DB1 _CAN1RXDSR0.Bits.DB1
#define CAN1RXDSR0_DB2 _CAN1RXDSR0.Bits.DB2
#define CAN1RXDSR0_DB3 _CAN1RXDSR0.Bits.DB3
#define CAN1RXDSR0_DB4 _CAN1RXDSR0.Bits.DB4
#define CAN1RXDSR0_DB5 _CAN1RXDSR0.Bits.DB5
#define CAN1RXDSR0_DB6 _CAN1RXDSR0.Bits.DB6
#define CAN1RXDSR0_DB7 _CAN1RXDSR0.Bits.DB7
#define CAN1RXDSR0_DB _CAN1RXDSR0.MergedBits.grpDB


/*** CAN1RXDSR1 - MSCAN 1 Receive Data Segment Register 1; 0x000001A5 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1RXDSR1STR;
extern volatile CAN1RXDSR1STR _CAN1RXDSR1 @(REG_BASE + 0x000001A5);
#define CAN1RXDSR1 _CAN1RXDSR1.Byte
#define CAN1RXDSR1_DB0 _CAN1RXDSR1.Bits.DB0
#define CAN1RXDSR1_DB1 _CAN1RXDSR1.Bits.DB1
#define CAN1RXDSR1_DB2 _CAN1RXDSR1.Bits.DB2
#define CAN1RXDSR1_DB3 _CAN1RXDSR1.Bits.DB3
#define CAN1RXDSR1_DB4 _CAN1RXDSR1.Bits.DB4
#define CAN1RXDSR1_DB5 _CAN1RXDSR1.Bits.DB5
#define CAN1RXDSR1_DB6 _CAN1RXDSR1.Bits.DB6
#define CAN1RXDSR1_DB7 _CAN1RXDSR1.Bits.DB7
#define CAN1RXDSR1_DB _CAN1RXDSR1.MergedBits.grpDB


/*** CAN1RXDSR2 - MSCAN 1 Receive Data Segment Register 2; 0x000001A6 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1RXDSR2STR;
extern volatile CAN1RXDSR2STR _CAN1RXDSR2 @(REG_BASE + 0x000001A6);
#define CAN1RXDSR2 _CAN1RXDSR2.Byte
#define CAN1RXDSR2_DB0 _CAN1RXDSR2.Bits.DB0
#define CAN1RXDSR2_DB1 _CAN1RXDSR2.Bits.DB1
#define CAN1RXDSR2_DB2 _CAN1RXDSR2.Bits.DB2
#define CAN1RXDSR2_DB3 _CAN1RXDSR2.Bits.DB3
#define CAN1RXDSR2_DB4 _CAN1RXDSR2.Bits.DB4
#define CAN1RXDSR2_DB5 _CAN1RXDSR2.Bits.DB5
#define CAN1RXDSR2_DB6 _CAN1RXDSR2.Bits.DB6
#define CAN1RXDSR2_DB7 _CAN1RXDSR2.Bits.DB7
#define CAN1RXDSR2_DB _CAN1RXDSR2.MergedBits.grpDB


/*** CAN1RXDSR3 - MSCAN 1 Receive Data Segment Register 3; 0x000001A7 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1RXDSR3STR;
extern volatile CAN1RXDSR3STR _CAN1RXDSR3 @(REG_BASE + 0x000001A7);
#define CAN1RXDSR3 _CAN1RXDSR3.Byte
#define CAN1RXDSR3_DB0 _CAN1RXDSR3.Bits.DB0
#define CAN1RXDSR3_DB1 _CAN1RXDSR3.Bits.DB1
#define CAN1RXDSR3_DB2 _CAN1RXDSR3.Bits.DB2
#define CAN1RXDSR3_DB3 _CAN1RXDSR3.Bits.DB3
#define CAN1RXDSR3_DB4 _CAN1RXDSR3.Bits.DB4
#define CAN1RXDSR3_DB5 _CAN1RXDSR3.Bits.DB5
#define CAN1RXDSR3_DB6 _CAN1RXDSR3.Bits.DB6
#define CAN1RXDSR3_DB7 _CAN1RXDSR3.Bits.DB7
#define CAN1RXDSR3_DB _CAN1RXDSR3.MergedBits.grpDB


/*** CAN1RXDSR4 - MSCAN 1 Receive Data Segment Register 4; 0x000001A8 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1RXDSR4STR;
extern volatile CAN1RXDSR4STR _CAN1RXDSR4 @(REG_BASE + 0x000001A8);
#define CAN1RXDSR4 _CAN1RXDSR4.Byte
#define CAN1RXDSR4_DB0 _CAN1RXDSR4.Bits.DB0
#define CAN1RXDSR4_DB1 _CAN1RXDSR4.Bits.DB1
#define CAN1RXDSR4_DB2 _CAN1RXDSR4.Bits.DB2
#define CAN1RXDSR4_DB3 _CAN1RXDSR4.Bits.DB3
#define CAN1RXDSR4_DB4 _CAN1RXDSR4.Bits.DB4
#define CAN1RXDSR4_DB5 _CAN1RXDSR4.Bits.DB5
#define CAN1RXDSR4_DB6 _CAN1RXDSR4.Bits.DB6
#define CAN1RXDSR4_DB7 _CAN1RXDSR4.Bits.DB7
#define CAN1RXDSR4_DB _CAN1RXDSR4.MergedBits.grpDB


/*** CAN1RXDSR5 - MSCAN 1 Receive Data Segment Register 5; 0x000001A9 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1RXDSR5STR;
extern volatile CAN1RXDSR5STR _CAN1RXDSR5 @(REG_BASE + 0x000001A9);
#define CAN1RXDSR5 _CAN1RXDSR5.Byte
#define CAN1RXDSR5_DB0 _CAN1RXDSR5.Bits.DB0
#define CAN1RXDSR5_DB1 _CAN1RXDSR5.Bits.DB1
#define CAN1RXDSR5_DB2 _CAN1RXDSR5.Bits.DB2
#define CAN1RXDSR5_DB3 _CAN1RXDSR5.Bits.DB3
#define CAN1RXDSR5_DB4 _CAN1RXDSR5.Bits.DB4
#define CAN1RXDSR5_DB5 _CAN1RXDSR5.Bits.DB5
#define CAN1RXDSR5_DB6 _CAN1RXDSR5.Bits.DB6
#define CAN1RXDSR5_DB7 _CAN1RXDSR5.Bits.DB7
#define CAN1RXDSR5_DB _CAN1RXDSR5.MergedBits.grpDB


/*** CAN1RXDSR6 - MSCAN 1 Receive Data Segment Register 6; 0x000001AA ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1RXDSR6STR;
extern volatile CAN1RXDSR6STR _CAN1RXDSR6 @(REG_BASE + 0x000001AA);
#define CAN1RXDSR6 _CAN1RXDSR6.Byte
#define CAN1RXDSR6_DB0 _CAN1RXDSR6.Bits.DB0
#define CAN1RXDSR6_DB1 _CAN1RXDSR6.Bits.DB1
#define CAN1RXDSR6_DB2 _CAN1RXDSR6.Bits.DB2
#define CAN1RXDSR6_DB3 _CAN1RXDSR6.Bits.DB3
#define CAN1RXDSR6_DB4 _CAN1RXDSR6.Bits.DB4
#define CAN1RXDSR6_DB5 _CAN1RXDSR6.Bits.DB5
#define CAN1RXDSR6_DB6 _CAN1RXDSR6.Bits.DB6
#define CAN1RXDSR6_DB7 _CAN1RXDSR6.Bits.DB7
#define CAN1RXDSR6_DB _CAN1RXDSR6.MergedBits.grpDB


/*** CAN1RXDSR7 - MSCAN 1 Receive Data Segment Register 7; 0x000001AB ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1RXDSR7STR;
extern volatile CAN1RXDSR7STR _CAN1RXDSR7 @(REG_BASE + 0x000001AB);
#define CAN1RXDSR7 _CAN1RXDSR7.Byte
#define CAN1RXDSR7_DB0 _CAN1RXDSR7.Bits.DB0
#define CAN1RXDSR7_DB1 _CAN1RXDSR7.Bits.DB1
#define CAN1RXDSR7_DB2 _CAN1RXDSR7.Bits.DB2
#define CAN1RXDSR7_DB3 _CAN1RXDSR7.Bits.DB3
#define CAN1RXDSR7_DB4 _CAN1RXDSR7.Bits.DB4
#define CAN1RXDSR7_DB5 _CAN1RXDSR7.Bits.DB5
#define CAN1RXDSR7_DB6 _CAN1RXDSR7.Bits.DB6
#define CAN1RXDSR7_DB7 _CAN1RXDSR7.Bits.DB7
#define CAN1RXDSR7_DB _CAN1RXDSR7.MergedBits.grpDB


/*** CAN1RXDLR - MSCAN 1 Receive Data Length Register; 0x000001AC ***/
typedef union {
  byte Byte;
  struct {
    byte DLC0        :1;                                       /* Data Length Code Bit 0 */
    byte DLC1        :1;                                       /* Data Length Code Bit 1 */
    byte DLC2        :1;                                       /* Data Length Code Bit 2 */
    byte DLC3        :1;                                       /* Data Length Code Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDLC  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN1RXDLRSTR;
extern volatile CAN1RXDLRSTR _CAN1RXDLR @(REG_BASE + 0x000001AC);
#define CAN1RXDLR _CAN1RXDLR.Byte
#define CAN1RXDLR_DLC0 _CAN1RXDLR.Bits.DLC0
#define CAN1RXDLR_DLC1 _CAN1RXDLR.Bits.DLC1
#define CAN1RXDLR_DLC2 _CAN1RXDLR.Bits.DLC2
#define CAN1RXDLR_DLC3 _CAN1RXDLR.Bits.DLC3
#define CAN1RXDLR_DLC _CAN1RXDLR.MergedBits.grpDLC


/*** CAN1TXIDR0 - MSCAN 1 Transmit Identifier Register 0; 0x000001B0 ***/
typedef union {
  byte Byte;
  struct {
    byte ID21        :1;                                       /* Extended format identifier Bit 21 */
    byte ID22        :1;                                       /* Extended format identifier Bit 22 */
    byte ID23        :1;                                       /* Extended format identifier Bit 23 */
    byte ID24        :1;                                       /* Extended format identifier Bit 24 */
    byte ID25        :1;                                       /* Extended format identifier Bit 25 */
    byte ID26        :1;                                       /* Extended format identifier Bit 26 */
    byte ID27        :1;                                       /* Extended format identifier Bit 27 */
    byte ID28        :1;                                       /* Extended format identifier Bit 28 */
  } Bits;
  struct {
    byte grpID_21 :8;
  } MergedBits;
} CAN1TXIDR0STR;
extern volatile CAN1TXIDR0STR _CAN1TXIDR0 @(REG_BASE + 0x000001B0);
#define CAN1TXIDR0 _CAN1TXIDR0.Byte
#define CAN1TXIDR0_ID21 _CAN1TXIDR0.Bits.ID21
#define CAN1TXIDR0_ID22 _CAN1TXIDR0.Bits.ID22
#define CAN1TXIDR0_ID23 _CAN1TXIDR0.Bits.ID23
#define CAN1TXIDR0_ID24 _CAN1TXIDR0.Bits.ID24
#define CAN1TXIDR0_ID25 _CAN1TXIDR0.Bits.ID25
#define CAN1TXIDR0_ID26 _CAN1TXIDR0.Bits.ID26
#define CAN1TXIDR0_ID27 _CAN1TXIDR0.Bits.ID27
#define CAN1TXIDR0_ID28 _CAN1TXIDR0.Bits.ID28
#define CAN1TXIDR0_ID_21 _CAN1TXIDR0.MergedBits.grpID_21
#define CAN1TXIDR0_ID CAN1TXIDR0_ID_21


/*** CAN1TXIDR1 - MSCAN 1 Transmit Identifier Register 1; 0x000001B1 ***/
typedef union {
  byte Byte;
  struct {
    byte ID15        :1;                                       /* Extended format identifier Bit 15 */
    byte ID16        :1;                                       /* Extended format identifier Bit 16 */
    byte ID17        :1;                                       /* Extended format identifier Bit 17 */
    byte IDE         :1;                                       /* ID Extended */
    byte SRR         :1;                                       /* Substitute Remote Request */
    byte ID18        :1;                                       /* Extended format identifier Bit 18 */
    byte ID19        :1;                                       /* Extended format identifier Bit 19 */
    byte ID20        :1;                                       /* Extended format identifier Bit 20 */
  } Bits;
  struct {
    byte grpID_15 :3;
    byte         :1;
    byte         :1;
    byte grpID_18 :3;
  } MergedBits;
} CAN1TXIDR1STR;
extern volatile CAN1TXIDR1STR _CAN1TXIDR1 @(REG_BASE + 0x000001B1);
#define CAN1TXIDR1 _CAN1TXIDR1.Byte
#define CAN1TXIDR1_ID15 _CAN1TXIDR1.Bits.ID15
#define CAN1TXIDR1_ID16 _CAN1TXIDR1.Bits.ID16
#define CAN1TXIDR1_ID17 _CAN1TXIDR1.Bits.ID17
#define CAN1TXIDR1_IDE _CAN1TXIDR1.Bits.IDE
#define CAN1TXIDR1_SRR _CAN1TXIDR1.Bits.SRR
#define CAN1TXIDR1_ID18 _CAN1TXIDR1.Bits.ID18
#define CAN1TXIDR1_ID19 _CAN1TXIDR1.Bits.ID19
#define CAN1TXIDR1_ID20 _CAN1TXIDR1.Bits.ID20
#define CAN1TXIDR1_ID_15 _CAN1TXIDR1.MergedBits.grpID_15
#define CAN1TXIDR1_ID_18 _CAN1TXIDR1.MergedBits.grpID_18
#define CAN1TXIDR1_ID CAN1TXIDR1_ID_15


/*** CAN1TXIDR2 - MSCAN 1 Transmit Identifier Register 2; 0x000001B2 ***/
typedef union {
  byte Byte;
  struct {
    byte ID7         :1;                                       /* Extended format identifier Bit 7 */
    byte ID8         :1;                                       /* Extended format identifier Bit 8 */
    byte ID9         :1;                                       /* Extended format identifier Bit 9 */
    byte ID10        :1;                                       /* Extended format identifier Bit 10 */
    byte ID11        :1;                                       /* Extended format identifier Bit 11 */
    byte ID12        :1;                                       /* Extended format identifier Bit 12 */
    byte ID13        :1;                                       /* Extended format identifier Bit 13 */
    byte ID14        :1;                                       /* Extended format identifier Bit 14 */
  } Bits;
  struct {
    byte grpID_7 :8;
  } MergedBits;
} CAN1TXIDR2STR;
extern volatile CAN1TXIDR2STR _CAN1TXIDR2 @(REG_BASE + 0x000001B2);
#define CAN1TXIDR2 _CAN1TXIDR2.Byte
#define CAN1TXIDR2_ID7 _CAN1TXIDR2.Bits.ID7
#define CAN1TXIDR2_ID8 _CAN1TXIDR2.Bits.ID8
#define CAN1TXIDR2_ID9 _CAN1TXIDR2.Bits.ID9
#define CAN1TXIDR2_ID10 _CAN1TXIDR2.Bits.ID10
#define CAN1TXIDR2_ID11 _CAN1TXIDR2.Bits.ID11
#define CAN1TXIDR2_ID12 _CAN1TXIDR2.Bits.ID12
#define CAN1TXIDR2_ID13 _CAN1TXIDR2.Bits.ID13
#define CAN1TXIDR2_ID14 _CAN1TXIDR2.Bits.ID14
#define CAN1TXIDR2_ID_7 _CAN1TXIDR2.MergedBits.grpID_7
#define CAN1TXIDR2_ID CAN1TXIDR2_ID_7


/*** CAN1TXIDR3 - MSCAN 1 Transmit Identifier Register 3; 0x000001B3 ***/
typedef union {
  byte Byte;
  struct {
    byte RTR         :1;                                       /* Remote Transmission Request */
    byte ID0         :1;                                       /* Extended format identifier Bit 0 */
    byte ID1         :1;                                       /* Extended format identifier Bit 1 */
    byte ID2         :1;                                       /* Extended format identifier Bit 2 */
    byte ID3         :1;                                       /* Extended format identifier Bit 3 */
    byte ID4         :1;                                       /* Extended format identifier Bit 4 */
    byte ID5         :1;                                       /* Extended format identifier Bit 5 */
    byte ID6         :1;                                       /* Extended format identifier Bit 6 */
  } Bits;
  struct {
    byte         :1;
    byte grpID   :7;
  } MergedBits;
} CAN1TXIDR3STR;
extern volatile CAN1TXIDR3STR _CAN1TXIDR3 @(REG_BASE + 0x000001B3);
#define CAN1TXIDR3 _CAN1TXIDR3.Byte
#define CAN1TXIDR3_RTR _CAN1TXIDR3.Bits.RTR
#define CAN1TXIDR3_ID0 _CAN1TXIDR3.Bits.ID0
#define CAN1TXIDR3_ID1 _CAN1TXIDR3.Bits.ID1
#define CAN1TXIDR3_ID2 _CAN1TXIDR3.Bits.ID2
#define CAN1TXIDR3_ID3 _CAN1TXIDR3.Bits.ID3
#define CAN1TXIDR3_ID4 _CAN1TXIDR3.Bits.ID4
#define CAN1TXIDR3_ID5 _CAN1TXIDR3.Bits.ID5
#define CAN1TXIDR3_ID6 _CAN1TXIDR3.Bits.ID6
#define CAN1TXIDR3_ID _CAN1TXIDR3.MergedBits.grpID


/*** CAN1TXDSR0 - MSCAN 1 Transmit Data Segment Register 0; 0x000001B4 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1TXDSR0STR;
extern volatile CAN1TXDSR0STR _CAN1TXDSR0 @(REG_BASE + 0x000001B4);
#define CAN1TXDSR0 _CAN1TXDSR0.Byte
#define CAN1TXDSR0_DB0 _CAN1TXDSR0.Bits.DB0
#define CAN1TXDSR0_DB1 _CAN1TXDSR0.Bits.DB1
#define CAN1TXDSR0_DB2 _CAN1TXDSR0.Bits.DB2
#define CAN1TXDSR0_DB3 _CAN1TXDSR0.Bits.DB3
#define CAN1TXDSR0_DB4 _CAN1TXDSR0.Bits.DB4
#define CAN1TXDSR0_DB5 _CAN1TXDSR0.Bits.DB5
#define CAN1TXDSR0_DB6 _CAN1TXDSR0.Bits.DB6
#define CAN1TXDSR0_DB7 _CAN1TXDSR0.Bits.DB7
#define CAN1TXDSR0_DB _CAN1TXDSR0.MergedBits.grpDB


/*** CAN1TXDSR1 - MSCAN 1 Transmit Data Segment Register 1; 0x000001B5 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1TXDSR1STR;
extern volatile CAN1TXDSR1STR _CAN1TXDSR1 @(REG_BASE + 0x000001B5);
#define CAN1TXDSR1 _CAN1TXDSR1.Byte
#define CAN1TXDSR1_DB0 _CAN1TXDSR1.Bits.DB0
#define CAN1TXDSR1_DB1 _CAN1TXDSR1.Bits.DB1
#define CAN1TXDSR1_DB2 _CAN1TXDSR1.Bits.DB2
#define CAN1TXDSR1_DB3 _CAN1TXDSR1.Bits.DB3
#define CAN1TXDSR1_DB4 _CAN1TXDSR1.Bits.DB4
#define CAN1TXDSR1_DB5 _CAN1TXDSR1.Bits.DB5
#define CAN1TXDSR1_DB6 _CAN1TXDSR1.Bits.DB6
#define CAN1TXDSR1_DB7 _CAN1TXDSR1.Bits.DB7
#define CAN1TXDSR1_DB _CAN1TXDSR1.MergedBits.grpDB


/*** CAN1TXDSR2 - MSCAN 1 Transmit Data Segment Register 2; 0x000001B6 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1TXDSR2STR;
extern volatile CAN1TXDSR2STR _CAN1TXDSR2 @(REG_BASE + 0x000001B6);
#define CAN1TXDSR2 _CAN1TXDSR2.Byte
#define CAN1TXDSR2_DB0 _CAN1TXDSR2.Bits.DB0
#define CAN1TXDSR2_DB1 _CAN1TXDSR2.Bits.DB1
#define CAN1TXDSR2_DB2 _CAN1TXDSR2.Bits.DB2
#define CAN1TXDSR2_DB3 _CAN1TXDSR2.Bits.DB3
#define CAN1TXDSR2_DB4 _CAN1TXDSR2.Bits.DB4
#define CAN1TXDSR2_DB5 _CAN1TXDSR2.Bits.DB5
#define CAN1TXDSR2_DB6 _CAN1TXDSR2.Bits.DB6
#define CAN1TXDSR2_DB7 _CAN1TXDSR2.Bits.DB7
#define CAN1TXDSR2_DB _CAN1TXDSR2.MergedBits.grpDB


/*** CAN1TXDSR3 - MSCAN 1 Transmit Data Segment Register 3; 0x000001B7 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1TXDSR3STR;
extern volatile CAN1TXDSR3STR _CAN1TXDSR3 @(REG_BASE + 0x000001B7);
#define CAN1TXDSR3 _CAN1TXDSR3.Byte
#define CAN1TXDSR3_DB0 _CAN1TXDSR3.Bits.DB0
#define CAN1TXDSR3_DB1 _CAN1TXDSR3.Bits.DB1
#define CAN1TXDSR3_DB2 _CAN1TXDSR3.Bits.DB2
#define CAN1TXDSR3_DB3 _CAN1TXDSR3.Bits.DB3
#define CAN1TXDSR3_DB4 _CAN1TXDSR3.Bits.DB4
#define CAN1TXDSR3_DB5 _CAN1TXDSR3.Bits.DB5
#define CAN1TXDSR3_DB6 _CAN1TXDSR3.Bits.DB6
#define CAN1TXDSR3_DB7 _CAN1TXDSR3.Bits.DB7
#define CAN1TXDSR3_DB _CAN1TXDSR3.MergedBits.grpDB


/*** CAN1TXDSR4 - MSCAN 1 Transmit Data Segment Register 4; 0x000001B8 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1TXDSR4STR;
extern volatile CAN1TXDSR4STR _CAN1TXDSR4 @(REG_BASE + 0x000001B8);
#define CAN1TXDSR4 _CAN1TXDSR4.Byte
#define CAN1TXDSR4_DB0 _CAN1TXDSR4.Bits.DB0
#define CAN1TXDSR4_DB1 _CAN1TXDSR4.Bits.DB1
#define CAN1TXDSR4_DB2 _CAN1TXDSR4.Bits.DB2
#define CAN1TXDSR4_DB3 _CAN1TXDSR4.Bits.DB3
#define CAN1TXDSR4_DB4 _CAN1TXDSR4.Bits.DB4
#define CAN1TXDSR4_DB5 _CAN1TXDSR4.Bits.DB5
#define CAN1TXDSR4_DB6 _CAN1TXDSR4.Bits.DB6
#define CAN1TXDSR4_DB7 _CAN1TXDSR4.Bits.DB7
#define CAN1TXDSR4_DB _CAN1TXDSR4.MergedBits.grpDB


/*** CAN1TXDSR5 - MSCAN 1 Transmit Data Segment Register 5; 0x000001B9 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1TXDSR5STR;
extern volatile CAN1TXDSR5STR _CAN1TXDSR5 @(REG_BASE + 0x000001B9);
#define CAN1TXDSR5 _CAN1TXDSR5.Byte
#define CAN1TXDSR5_DB0 _CAN1TXDSR5.Bits.DB0
#define CAN1TXDSR5_DB1 _CAN1TXDSR5.Bits.DB1
#define CAN1TXDSR5_DB2 _CAN1TXDSR5.Bits.DB2
#define CAN1TXDSR5_DB3 _CAN1TXDSR5.Bits.DB3
#define CAN1TXDSR5_DB4 _CAN1TXDSR5.Bits.DB4
#define CAN1TXDSR5_DB5 _CAN1TXDSR5.Bits.DB5
#define CAN1TXDSR5_DB6 _CAN1TXDSR5.Bits.DB6
#define CAN1TXDSR5_DB7 _CAN1TXDSR5.Bits.DB7
#define CAN1TXDSR5_DB _CAN1TXDSR5.MergedBits.grpDB


/*** CAN1TXDSR6 - MSCAN 1 Transmit Data Segment Register 6; 0x000001BA ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1TXDSR6STR;
extern volatile CAN1TXDSR6STR _CAN1TXDSR6 @(REG_BASE + 0x000001BA);
#define CAN1TXDSR6 _CAN1TXDSR6.Byte
#define CAN1TXDSR6_DB0 _CAN1TXDSR6.Bits.DB0
#define CAN1TXDSR6_DB1 _CAN1TXDSR6.Bits.DB1
#define CAN1TXDSR6_DB2 _CAN1TXDSR6.Bits.DB2
#define CAN1TXDSR6_DB3 _CAN1TXDSR6.Bits.DB3
#define CAN1TXDSR6_DB4 _CAN1TXDSR6.Bits.DB4
#define CAN1TXDSR6_DB5 _CAN1TXDSR6.Bits.DB5
#define CAN1TXDSR6_DB6 _CAN1TXDSR6.Bits.DB6
#define CAN1TXDSR6_DB7 _CAN1TXDSR6.Bits.DB7
#define CAN1TXDSR6_DB _CAN1TXDSR6.MergedBits.grpDB


/*** CAN1TXDSR7 - MSCAN 1 Transmit Data Segment Register 7; 0x000001BB ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN1TXDSR7STR;
extern volatile CAN1TXDSR7STR _CAN1TXDSR7 @(REG_BASE + 0x000001BB);
#define CAN1TXDSR7 _CAN1TXDSR7.Byte
#define CAN1TXDSR7_DB0 _CAN1TXDSR7.Bits.DB0
#define CAN1TXDSR7_DB1 _CAN1TXDSR7.Bits.DB1
#define CAN1TXDSR7_DB2 _CAN1TXDSR7.Bits.DB2
#define CAN1TXDSR7_DB3 _CAN1TXDSR7.Bits.DB3
#define CAN1TXDSR7_DB4 _CAN1TXDSR7.Bits.DB4
#define CAN1TXDSR7_DB5 _CAN1TXDSR7.Bits.DB5
#define CAN1TXDSR7_DB6 _CAN1TXDSR7.Bits.DB6
#define CAN1TXDSR7_DB7 _CAN1TXDSR7.Bits.DB7
#define CAN1TXDSR7_DB _CAN1TXDSR7.MergedBits.grpDB


/*** CAN1TXDLR - MSCAN 1 Transmit Data Length Register; 0x000001BC ***/
typedef union {
  byte Byte;
  struct {
    byte DLC0        :1;                                       /* Data Length Code Bit 0 */
    byte DLC1        :1;                                       /* Data Length Code Bit 1 */
    byte DLC2        :1;                                       /* Data Length Code Bit 2 */
    byte DLC3        :1;                                       /* Data Length Code Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDLC  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN1TXDLRSTR;
extern volatile CAN1TXDLRSTR _CAN1TXDLR @(REG_BASE + 0x000001BC);
#define CAN1TXDLR _CAN1TXDLR.Byte
#define CAN1TXDLR_DLC0 _CAN1TXDLR.Bits.DLC0
#define CAN1TXDLR_DLC1 _CAN1TXDLR.Bits.DLC1
#define CAN1TXDLR_DLC2 _CAN1TXDLR.Bits.DLC2
#define CAN1TXDLR_DLC3 _CAN1TXDLR.Bits.DLC3
#define CAN1TXDLR_DLC _CAN1TXDLR.MergedBits.grpDLC


/*** CAN1TXTBPR - MSCAN 1 Transmit Buffer Priority; 0x000001BF ***/
typedef union {
  byte Byte;
  struct {
    byte PRIO0       :1;                                       /* Transmit Buffer Priority Bit 0 */
    byte PRIO1       :1;                                       /* Transmit Buffer Priority Bit 1 */
    byte PRIO2       :1;                                       /* Transmit Buffer Priority Bit 2 */
    byte PRIO3       :1;                                       /* Transmit Buffer Priority Bit 3 */
    byte PRIO4       :1;                                       /* Transmit Buffer Priority Bit 4 */
    byte PRIO5       :1;                                       /* Transmit Buffer Priority Bit 5 */
    byte PRIO6       :1;                                       /* Transmit Buffer Priority Bit 6 */
    byte PRIO7       :1;                                       /* Transmit Buffer Priority Bit 7 */
  } Bits;
  struct {
    byte grpPRIO :8;
  } MergedBits;
} CAN1TXTBPRSTR;
extern volatile CAN1TXTBPRSTR _CAN1TXTBPR @(REG_BASE + 0x000001BF);
#define CAN1TXTBPR _CAN1TXTBPR.Byte
#define CAN1TXTBPR_PRIO0 _CAN1TXTBPR.Bits.PRIO0
#define CAN1TXTBPR_PRIO1 _CAN1TXTBPR.Bits.PRIO1
#define CAN1TXTBPR_PRIO2 _CAN1TXTBPR.Bits.PRIO2
#define CAN1TXTBPR_PRIO3 _CAN1TXTBPR.Bits.PRIO3
#define CAN1TXTBPR_PRIO4 _CAN1TXTBPR.Bits.PRIO4
#define CAN1TXTBPR_PRIO5 _CAN1TXTBPR.Bits.PRIO5
#define CAN1TXTBPR_PRIO6 _CAN1TXTBPR.Bits.PRIO6
#define CAN1TXTBPR_PRIO7 _CAN1TXTBPR.Bits.PRIO7
#define CAN1TXTBPR_PRIO _CAN1TXTBPR.MergedBits.grpPRIO


/*** CAN2CTL0 - MSCAN 2 Control 0 Register; 0x000001C0 ***/
typedef union {
  byte Byte;
  struct {
    byte INITRQ      :1;                                       /* Initialization Mode Request */
    byte SLPRQ       :1;                                       /* Sleep Mode Request */
    byte WUPE        :1;                                       /* Wake-Up Enable */
    byte TIME        :1;                                       /* Timer Enable */
    byte SYNCH       :1;                                       /* Synchronized Status */
    byte CSWAI       :1;                                       /* CAN Stops in Wait Mode */
    byte RXACT       :1;                                       /* Receiver Active Status */
    byte RXFRM       :1;                                       /* Received Frame Flag */
  } Bits;
} CAN2CTL0STR;
extern volatile CAN2CTL0STR _CAN2CTL0 @(REG_BASE + 0x000001C0);
#define CAN2CTL0 _CAN2CTL0.Byte
#define CAN2CTL0_INITRQ _CAN2CTL0.Bits.INITRQ
#define CAN2CTL0_SLPRQ _CAN2CTL0.Bits.SLPRQ
#define CAN2CTL0_WUPE _CAN2CTL0.Bits.WUPE
#define CAN2CTL0_TIME _CAN2CTL0.Bits.TIME
#define CAN2CTL0_SYNCH _CAN2CTL0.Bits.SYNCH
#define CAN2CTL0_CSWAI _CAN2CTL0.Bits.CSWAI
#define CAN2CTL0_RXACT _CAN2CTL0.Bits.RXACT
#define CAN2CTL0_RXFRM _CAN2CTL0.Bits.RXFRM


/*** CAN2CTL1 - MSCAN 2 Control 1 Register; 0x000001C1 ***/
typedef union {
  byte Byte;
  struct {
    byte INITAK      :1;                                       /* Initialization Mode Acknowledge */
    byte SLPAK       :1;                                       /* Sleep Mode Acknowledge */
    byte WUPM        :1;                                       /* Wake-Up Mode */
    byte             :1; 
    byte LISTEN      :1;                                       /* Listen Only Mode */
    byte LOOPB       :1;                                       /* Loop Back Self Test Mode */
    byte CLKSRC      :1;                                       /* MSCAN 2 Clock Source */
    byte CANE        :1;                                       /* MSCAN 2 Enable */
  } Bits;
} CAN2CTL1STR;
extern volatile CAN2CTL1STR _CAN2CTL1 @(REG_BASE + 0x000001C1);
#define CAN2CTL1 _CAN2CTL1.Byte
#define CAN2CTL1_INITAK _CAN2CTL1.Bits.INITAK
#define CAN2CTL1_SLPAK _CAN2CTL1.Bits.SLPAK
#define CAN2CTL1_WUPM _CAN2CTL1.Bits.WUPM
#define CAN2CTL1_LISTEN _CAN2CTL1.Bits.LISTEN
#define CAN2CTL1_LOOPB _CAN2CTL1.Bits.LOOPB
#define CAN2CTL1_CLKSRC _CAN2CTL1.Bits.CLKSRC
#define CAN2CTL1_CANE _CAN2CTL1.Bits.CANE


/*** CAN2BTR0 - MSCAN 2 Bus Timing Register 0; 0x000001C2 ***/
typedef union {
  byte Byte;
  struct {
    byte BRP0        :1;                                       /* Baud Rate Prescaler 0 */
    byte BRP1        :1;                                       /* Baud Rate Prescaler 1 */
    byte BRP2        :1;                                       /* Baud Rate Prescaler 2 */
    byte BRP3        :1;                                       /* Baud Rate Prescaler 3 */
    byte BRP4        :1;                                       /* Baud Rate Prescaler 4 */
    byte BRP5        :1;                                       /* Baud Rate Prescaler 5 */
    byte SJW0        :1;                                       /* Synchronization Jump Width 0 */
    byte SJW1        :1;                                       /* Synchronization Jump Width 1 */
  } Bits;
  struct {
    byte grpBRP  :6;
    byte grpSJW  :2;
  } MergedBits;
} CAN2BTR0STR;
extern volatile CAN2BTR0STR _CAN2BTR0 @(REG_BASE + 0x000001C2);
#define CAN2BTR0 _CAN2BTR0.Byte
#define CAN2BTR0_BRP0 _CAN2BTR0.Bits.BRP0
#define CAN2BTR0_BRP1 _CAN2BTR0.Bits.BRP1
#define CAN2BTR0_BRP2 _CAN2BTR0.Bits.BRP2
#define CAN2BTR0_BRP3 _CAN2BTR0.Bits.BRP3
#define CAN2BTR0_BRP4 _CAN2BTR0.Bits.BRP4
#define CAN2BTR0_BRP5 _CAN2BTR0.Bits.BRP5
#define CAN2BTR0_SJW0 _CAN2BTR0.Bits.SJW0
#define CAN2BTR0_SJW1 _CAN2BTR0.Bits.SJW1
#define CAN2BTR0_BRP _CAN2BTR0.MergedBits.grpBRP
#define CAN2BTR0_SJW _CAN2BTR0.MergedBits.grpSJW


/*** CAN2BTR1 - MSCAN 2 Bus Timing Register 1; 0x000001C3 ***/
typedef union {
  byte Byte;
  struct {
    byte TSEG10      :1;                                       /* Time Segment 1 */
    byte TSEG11      :1;                                       /* Time Segment 1 */
    byte TSEG12      :1;                                       /* Time Segment 1 */
    byte TSEG13      :1;                                       /* Time Segment 1 */
    byte TSEG20      :1;                                       /* Time Segment 2 */
    byte TSEG21      :1;                                       /* Time Segment 2 */
    byte TSEG22      :1;                                       /* Time Segment 2 */
    byte SAMP        :1;                                       /* Sampling */
  } Bits;
  struct {
    byte grpTSEG_10 :4;
    byte grpTSEG_20 :3;
    byte         :1;
  } MergedBits;
} CAN2BTR1STR;
extern volatile CAN2BTR1STR _CAN2BTR1 @(REG_BASE + 0x000001C3);
#define CAN2BTR1 _CAN2BTR1.Byte
#define CAN2BTR1_TSEG10 _CAN2BTR1.Bits.TSEG10
#define CAN2BTR1_TSEG11 _CAN2BTR1.Bits.TSEG11
#define CAN2BTR1_TSEG12 _CAN2BTR1.Bits.TSEG12
#define CAN2BTR1_TSEG13 _CAN2BTR1.Bits.TSEG13
#define CAN2BTR1_TSEG20 _CAN2BTR1.Bits.TSEG20
#define CAN2BTR1_TSEG21 _CAN2BTR1.Bits.TSEG21
#define CAN2BTR1_TSEG22 _CAN2BTR1.Bits.TSEG22
#define CAN2BTR1_SAMP _CAN2BTR1.Bits.SAMP
#define CAN2BTR1_TSEG_10 _CAN2BTR1.MergedBits.grpTSEG_10
#define CAN2BTR1_TSEG_20 _CAN2BTR1.MergedBits.grpTSEG_20
#define CAN2BTR1_TSEG CAN2BTR1_TSEG_10


/*** CAN2RFLG - MSCAN 2 Receiver Flag Register; 0x000001C4 ***/
typedef union {
  byte Byte;
  struct {
    byte RXF         :1;                                       /* Receive Buffer Full */
    byte OVRIF       :1;                                       /* Overrun Interrupt Flag */
    byte TSTAT0      :1;                                       /* Transmitter Status Bit 0 */
    byte TSTAT1      :1;                                       /* Transmitter Status Bit 1 */
    byte RSTAT0      :1;                                       /* Receiver Status Bit 0 */
    byte RSTAT1      :1;                                       /* Receiver Status Bit 1 */
    byte CSCIF       :1;                                       /* CAN Status Change Interrupt Flag */
    byte WUPIF       :1;                                       /* Wake-up Interrupt Flag */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpTSTAT :2;
    byte grpRSTAT :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN2RFLGSTR;
extern volatile CAN2RFLGSTR _CAN2RFLG @(REG_BASE + 0x000001C4);
#define CAN2RFLG _CAN2RFLG.Byte
#define CAN2RFLG_RXF _CAN2RFLG.Bits.RXF
#define CAN2RFLG_OVRIF _CAN2RFLG.Bits.OVRIF
#define CAN2RFLG_TSTAT0 _CAN2RFLG.Bits.TSTAT0
#define CAN2RFLG_TSTAT1 _CAN2RFLG.Bits.TSTAT1
#define CAN2RFLG_RSTAT0 _CAN2RFLG.Bits.RSTAT0
#define CAN2RFLG_RSTAT1 _CAN2RFLG.Bits.RSTAT1
#define CAN2RFLG_CSCIF _CAN2RFLG.Bits.CSCIF
#define CAN2RFLG_WUPIF _CAN2RFLG.Bits.WUPIF
#define CAN2RFLG_TSTAT _CAN2RFLG.MergedBits.grpTSTAT
#define CAN2RFLG_RSTAT _CAN2RFLG.MergedBits.grpRSTAT


/*** CAN2RIER - MSCAN 2 Receiver Interrupt Enable Register; 0x000001C5 ***/
typedef union {
  byte Byte;
  struct {
    byte RXFIE       :1;                                       /* Receiver Full Interrupt Enable */
    byte OVRIE       :1;                                       /* Overrun Interrupt Enable */
    byte TSTATE0     :1;                                       /* Transmitter Status Change Enable 0 */
    byte TSTATE1     :1;                                       /* Transmitter Status Change Enable 1 */
    byte RSTATE0     :1;                                       /* Receiver Status Change Enable 0 */
    byte RSTATE1     :1;                                       /* Receiver Status Change Enable 1 */
    byte CSCIE       :1;                                       /* CAN Status Change Interrupt Enable */
    byte WUPIE       :1;                                       /* Wake-up Interrupt Enable */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpTSTATE :2;
    byte grpRSTATE :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN2RIERSTR;
extern volatile CAN2RIERSTR _CAN2RIER @(REG_BASE + 0x000001C5);
#define CAN2RIER _CAN2RIER.Byte
#define CAN2RIER_RXFIE _CAN2RIER.Bits.RXFIE
#define CAN2RIER_OVRIE _CAN2RIER.Bits.OVRIE
#define CAN2RIER_TSTATE0 _CAN2RIER.Bits.TSTATE0
#define CAN2RIER_TSTATE1 _CAN2RIER.Bits.TSTATE1
#define CAN2RIER_RSTATE0 _CAN2RIER.Bits.RSTATE0
#define CAN2RIER_RSTATE1 _CAN2RIER.Bits.RSTATE1
#define CAN2RIER_CSCIE _CAN2RIER.Bits.CSCIE
#define CAN2RIER_WUPIE _CAN2RIER.Bits.WUPIE
#define CAN2RIER_TSTATE _CAN2RIER.MergedBits.grpTSTATE
#define CAN2RIER_RSTATE _CAN2RIER.MergedBits.grpRSTATE


/*** CAN2TFLG - MSCAN 2 Transmitter Flag Register; 0x000001C6 ***/
typedef union {
  byte Byte;
  struct {
    byte TXE0        :1;                                       /* Transmitter Buffer Empty 0 */
    byte TXE1        :1;                                       /* Transmitter Buffer Empty 1 */
    byte TXE2        :1;                                       /* Transmitter Buffer Empty 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTXE  :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN2TFLGSTR;
extern volatile CAN2TFLGSTR _CAN2TFLG @(REG_BASE + 0x000001C6);
#define CAN2TFLG _CAN2TFLG.Byte
#define CAN2TFLG_TXE0 _CAN2TFLG.Bits.TXE0
#define CAN2TFLG_TXE1 _CAN2TFLG.Bits.TXE1
#define CAN2TFLG_TXE2 _CAN2TFLG.Bits.TXE2
#define CAN2TFLG_TXE _CAN2TFLG.MergedBits.grpTXE


/*** CAN2TIER - MSCAN 2 Transmitter Interrupt Enable Register; 0x000001C7 ***/
typedef union {
  byte Byte;
  struct {
    byte TXEIE0      :1;                                       /* Transmitter Empty Interrupt Enable 0 */
    byte TXEIE1      :1;                                       /* Transmitter Empty Interrupt Enable 1 */
    byte TXEIE2      :1;                                       /* Transmitter Empty Interrupt Enable 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTXEIE :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN2TIERSTR;
extern volatile CAN2TIERSTR _CAN2TIER @(REG_BASE + 0x000001C7);
#define CAN2TIER _CAN2TIER.Byte
#define CAN2TIER_TXEIE0 _CAN2TIER.Bits.TXEIE0
#define CAN2TIER_TXEIE1 _CAN2TIER.Bits.TXEIE1
#define CAN2TIER_TXEIE2 _CAN2TIER.Bits.TXEIE2
#define CAN2TIER_TXEIE _CAN2TIER.MergedBits.grpTXEIE


/*** CAN2TARQ - MSCAN 2 Transmitter Message Abort Request; 0x000001C8 ***/
typedef union {
  byte Byte;
  struct {
    byte ABTRQ0      :1;                                       /* Abort Request 0 */
    byte ABTRQ1      :1;                                       /* Abort Request 1 */
    byte ABTRQ2      :1;                                       /* Abort Request 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpABTRQ :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN2TARQSTR;
extern volatile CAN2TARQSTR _CAN2TARQ @(REG_BASE + 0x000001C8);
#define CAN2TARQ _CAN2TARQ.Byte
#define CAN2TARQ_ABTRQ0 _CAN2TARQ.Bits.ABTRQ0
#define CAN2TARQ_ABTRQ1 _CAN2TARQ.Bits.ABTRQ1
#define CAN2TARQ_ABTRQ2 _CAN2TARQ.Bits.ABTRQ2
#define CAN2TARQ_ABTRQ _CAN2TARQ.MergedBits.grpABTRQ


/*** CAN2TAAK - MSCAN 2 Transmitter Message Abort Control; 0x000001C9 ***/
typedef union {
  byte Byte;
  struct {
    byte ABTAK0      :1;                                       /* Abort Acknowledge 0 */
    byte ABTAK1      :1;                                       /* Abort Acknowledge 1 */
    byte ABTAK2      :1;                                       /* Abort Acknowledge 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpABTAK :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN2TAAKSTR;
extern volatile CAN2TAAKSTR _CAN2TAAK @(REG_BASE + 0x000001C9);
#define CAN2TAAK _CAN2TAAK.Byte
#define CAN2TAAK_ABTAK0 _CAN2TAAK.Bits.ABTAK0
#define CAN2TAAK_ABTAK1 _CAN2TAAK.Bits.ABTAK1
#define CAN2TAAK_ABTAK2 _CAN2TAAK.Bits.ABTAK2
#define CAN2TAAK_ABTAK _CAN2TAAK.MergedBits.grpABTAK


/*** CAN2TBSEL - MSCAN 2 Transmit Buffer Selection; 0x000001CA ***/
typedef union {
  byte Byte;
  struct {
    byte TX0         :1;                                       /* Transmit Buffer Select 0 */
    byte TX1         :1;                                       /* Transmit Buffer Select 1 */
    byte TX2         :1;                                       /* Transmit Buffer Select 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTX   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN2TBSELSTR;
extern volatile CAN2TBSELSTR _CAN2TBSEL @(REG_BASE + 0x000001CA);
#define CAN2TBSEL _CAN2TBSEL.Byte
#define CAN2TBSEL_TX0 _CAN2TBSEL.Bits.TX0
#define CAN2TBSEL_TX1 _CAN2TBSEL.Bits.TX1
#define CAN2TBSEL_TX2 _CAN2TBSEL.Bits.TX2
#define CAN2TBSEL_TX _CAN2TBSEL.MergedBits.grpTX


/*** CAN2IDAC - MSCAN 2 Identifier Acceptance Control Register; 0x000001CB ***/
typedef union {
  byte Byte;
  struct {
    byte IDHIT0      :1;                                       /* Identifier Acceptance Hit Indicator 0 */
    byte IDHIT1      :1;                                       /* Identifier Acceptance Hit Indicator 1 */
    byte IDHIT2      :1;                                       /* Identifier Acceptance Hit Indicator 2 */
    byte             :1; 
    byte IDAM0       :1;                                       /* Identifier Acceptance Mode 0 */
    byte IDAM1       :1;                                       /* Identifier Acceptance Mode 1 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpIDHIT :3;
    byte         :1;
    byte grpIDAM :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN2IDACSTR;
extern volatile CAN2IDACSTR _CAN2IDAC @(REG_BASE + 0x000001CB);
#define CAN2IDAC _CAN2IDAC.Byte
#define CAN2IDAC_IDHIT0 _CAN2IDAC.Bits.IDHIT0
#define CAN2IDAC_IDHIT1 _CAN2IDAC.Bits.IDHIT1
#define CAN2IDAC_IDHIT2 _CAN2IDAC.Bits.IDHIT2
#define CAN2IDAC_IDAM0 _CAN2IDAC.Bits.IDAM0
#define CAN2IDAC_IDAM1 _CAN2IDAC.Bits.IDAM1
#define CAN2IDAC_IDHIT _CAN2IDAC.MergedBits.grpIDHIT
#define CAN2IDAC_IDAM _CAN2IDAC.MergedBits.grpIDAM


/*** CAN2RXERR - MSCAN 2 Receive Error Counter Register; 0x000001CE ***/
typedef union {
  byte Byte;
  struct {
    byte RXERR0      :1;                                       /* Bit 0 */
    byte RXERR1      :1;                                       /* Bit 1 */
    byte RXERR2      :1;                                       /* Bit 2 */
    byte RXERR3      :1;                                       /* Bit 3 */
    byte RXERR4      :1;                                       /* Bit 4 */
    byte RXERR5      :1;                                       /* Bit 5 */
    byte RXERR6      :1;                                       /* Bit 6 */
    byte RXERR7      :1;                                       /* Bit 7 */
  } Bits;
  struct {
    byte grpRXERR :8;
  } MergedBits;
} CAN2RXERRSTR;
extern volatile CAN2RXERRSTR _CAN2RXERR @(REG_BASE + 0x000001CE);
#define CAN2RXERR _CAN2RXERR.Byte
#define CAN2RXERR_RXERR0 _CAN2RXERR.Bits.RXERR0
#define CAN2RXERR_RXERR1 _CAN2RXERR.Bits.RXERR1
#define CAN2RXERR_RXERR2 _CAN2RXERR.Bits.RXERR2
#define CAN2RXERR_RXERR3 _CAN2RXERR.Bits.RXERR3
#define CAN2RXERR_RXERR4 _CAN2RXERR.Bits.RXERR4
#define CAN2RXERR_RXERR5 _CAN2RXERR.Bits.RXERR5
#define CAN2RXERR_RXERR6 _CAN2RXERR.Bits.RXERR6
#define CAN2RXERR_RXERR7 _CAN2RXERR.Bits.RXERR7
#define CAN2RXERR_RXERR _CAN2RXERR.MergedBits.grpRXERR


/*** CAN2TXERR - MSCAN 2 Transmit Error Counter Register; 0x000001CF ***/
typedef union {
  byte Byte;
  struct {
    byte TXERR0      :1;                                       /* Bit 0 */
    byte TXERR1      :1;                                       /* Bit 1 */
    byte TXERR2      :1;                                       /* Bit 2 */
    byte TXERR3      :1;                                       /* Bit 3 */
    byte TXERR4      :1;                                       /* Bit 4 */
    byte TXERR5      :1;                                       /* Bit 5 */
    byte TXERR6      :1;                                       /* Bit 6 */
    byte TXERR7      :1;                                       /* Bit 7 */
  } Bits;
  struct {
    byte grpTXERR :8;
  } MergedBits;
} CAN2TXERRSTR;
extern volatile CAN2TXERRSTR _CAN2TXERR @(REG_BASE + 0x000001CF);
#define CAN2TXERR _CAN2TXERR.Byte
#define CAN2TXERR_TXERR0 _CAN2TXERR.Bits.TXERR0
#define CAN2TXERR_TXERR1 _CAN2TXERR.Bits.TXERR1
#define CAN2TXERR_TXERR2 _CAN2TXERR.Bits.TXERR2
#define CAN2TXERR_TXERR3 _CAN2TXERR.Bits.TXERR3
#define CAN2TXERR_TXERR4 _CAN2TXERR.Bits.TXERR4
#define CAN2TXERR_TXERR5 _CAN2TXERR.Bits.TXERR5
#define CAN2TXERR_TXERR6 _CAN2TXERR.Bits.TXERR6
#define CAN2TXERR_TXERR7 _CAN2TXERR.Bits.TXERR7
#define CAN2TXERR_TXERR _CAN2TXERR.MergedBits.grpTXERR


/*** CAN2IDAR0 - MSCAN 2 Identifier Acceptance Register 0; 0x000001D0 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN2IDAR0STR;
extern volatile CAN2IDAR0STR _CAN2IDAR0 @(REG_BASE + 0x000001D0);
#define CAN2IDAR0 _CAN2IDAR0.Byte
#define CAN2IDAR0_AC0 _CAN2IDAR0.Bits.AC0
#define CAN2IDAR0_AC1 _CAN2IDAR0.Bits.AC1
#define CAN2IDAR0_AC2 _CAN2IDAR0.Bits.AC2
#define CAN2IDAR0_AC3 _CAN2IDAR0.Bits.AC3
#define CAN2IDAR0_AC4 _CAN2IDAR0.Bits.AC4
#define CAN2IDAR0_AC5 _CAN2IDAR0.Bits.AC5
#define CAN2IDAR0_AC6 _CAN2IDAR0.Bits.AC6
#define CAN2IDAR0_AC7 _CAN2IDAR0.Bits.AC7
#define CAN2IDAR0_AC _CAN2IDAR0.MergedBits.grpAC


/*** CAN2IDAR1 - MSCAN 2 Identifier Acceptance Register 1; 0x000001D1 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN2IDAR1STR;
extern volatile CAN2IDAR1STR _CAN2IDAR1 @(REG_BASE + 0x000001D1);
#define CAN2IDAR1 _CAN2IDAR1.Byte
#define CAN2IDAR1_AC0 _CAN2IDAR1.Bits.AC0
#define CAN2IDAR1_AC1 _CAN2IDAR1.Bits.AC1
#define CAN2IDAR1_AC2 _CAN2IDAR1.Bits.AC2
#define CAN2IDAR1_AC3 _CAN2IDAR1.Bits.AC3
#define CAN2IDAR1_AC4 _CAN2IDAR1.Bits.AC4
#define CAN2IDAR1_AC5 _CAN2IDAR1.Bits.AC5
#define CAN2IDAR1_AC6 _CAN2IDAR1.Bits.AC6
#define CAN2IDAR1_AC7 _CAN2IDAR1.Bits.AC7
#define CAN2IDAR1_AC _CAN2IDAR1.MergedBits.grpAC


/*** CAN2IDAR2 - MSCAN 2 Identifier Acceptance Register 2; 0x000001D2 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN2IDAR2STR;
extern volatile CAN2IDAR2STR _CAN2IDAR2 @(REG_BASE + 0x000001D2);
#define CAN2IDAR2 _CAN2IDAR2.Byte
#define CAN2IDAR2_AC0 _CAN2IDAR2.Bits.AC0
#define CAN2IDAR2_AC1 _CAN2IDAR2.Bits.AC1
#define CAN2IDAR2_AC2 _CAN2IDAR2.Bits.AC2
#define CAN2IDAR2_AC3 _CAN2IDAR2.Bits.AC3
#define CAN2IDAR2_AC4 _CAN2IDAR2.Bits.AC4
#define CAN2IDAR2_AC5 _CAN2IDAR2.Bits.AC5
#define CAN2IDAR2_AC6 _CAN2IDAR2.Bits.AC6
#define CAN2IDAR2_AC7 _CAN2IDAR2.Bits.AC7
#define CAN2IDAR2_AC _CAN2IDAR2.MergedBits.grpAC


/*** CAN2IDAR3 - MSCAN 2 Identifier Acceptance Register 3; 0x000001D3 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN2IDAR3STR;
extern volatile CAN2IDAR3STR _CAN2IDAR3 @(REG_BASE + 0x000001D3);
#define CAN2IDAR3 _CAN2IDAR3.Byte
#define CAN2IDAR3_AC0 _CAN2IDAR3.Bits.AC0
#define CAN2IDAR3_AC1 _CAN2IDAR3.Bits.AC1
#define CAN2IDAR3_AC2 _CAN2IDAR3.Bits.AC2
#define CAN2IDAR3_AC3 _CAN2IDAR3.Bits.AC3
#define CAN2IDAR3_AC4 _CAN2IDAR3.Bits.AC4
#define CAN2IDAR3_AC5 _CAN2IDAR3.Bits.AC5
#define CAN2IDAR3_AC6 _CAN2IDAR3.Bits.AC6
#define CAN2IDAR3_AC7 _CAN2IDAR3.Bits.AC7
#define CAN2IDAR3_AC _CAN2IDAR3.MergedBits.grpAC


/*** CAN2IDMR0 - MSCAN 2 Identifier Mask Register 0; 0x000001D4 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN2IDMR0STR;
extern volatile CAN2IDMR0STR _CAN2IDMR0 @(REG_BASE + 0x000001D4);
#define CAN2IDMR0 _CAN2IDMR0.Byte
#define CAN2IDMR0_AM0 _CAN2IDMR0.Bits.AM0
#define CAN2IDMR0_AM1 _CAN2IDMR0.Bits.AM1
#define CAN2IDMR0_AM2 _CAN2IDMR0.Bits.AM2
#define CAN2IDMR0_AM3 _CAN2IDMR0.Bits.AM3
#define CAN2IDMR0_AM4 _CAN2IDMR0.Bits.AM4
#define CAN2IDMR0_AM5 _CAN2IDMR0.Bits.AM5
#define CAN2IDMR0_AM6 _CAN2IDMR0.Bits.AM6
#define CAN2IDMR0_AM7 _CAN2IDMR0.Bits.AM7
#define CAN2IDMR0_AM _CAN2IDMR0.MergedBits.grpAM


/*** CAN2IDMR1 - MSCAN 2 Identifier Mask Register 1; 0x000001D5 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN2IDMR1STR;
extern volatile CAN2IDMR1STR _CAN2IDMR1 @(REG_BASE + 0x000001D5);
#define CAN2IDMR1 _CAN2IDMR1.Byte
#define CAN2IDMR1_AM0 _CAN2IDMR1.Bits.AM0
#define CAN2IDMR1_AM1 _CAN2IDMR1.Bits.AM1
#define CAN2IDMR1_AM2 _CAN2IDMR1.Bits.AM2
#define CAN2IDMR1_AM3 _CAN2IDMR1.Bits.AM3
#define CAN2IDMR1_AM4 _CAN2IDMR1.Bits.AM4
#define CAN2IDMR1_AM5 _CAN2IDMR1.Bits.AM5
#define CAN2IDMR1_AM6 _CAN2IDMR1.Bits.AM6
#define CAN2IDMR1_AM7 _CAN2IDMR1.Bits.AM7
#define CAN2IDMR1_AM _CAN2IDMR1.MergedBits.grpAM


/*** CAN2IDMR2 - MSCAN 2 Identifier Mask Register 2; 0x000001D6 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN2IDMR2STR;
extern volatile CAN2IDMR2STR _CAN2IDMR2 @(REG_BASE + 0x000001D6);
#define CAN2IDMR2 _CAN2IDMR2.Byte
#define CAN2IDMR2_AM0 _CAN2IDMR2.Bits.AM0
#define CAN2IDMR2_AM1 _CAN2IDMR2.Bits.AM1
#define CAN2IDMR2_AM2 _CAN2IDMR2.Bits.AM2
#define CAN2IDMR2_AM3 _CAN2IDMR2.Bits.AM3
#define CAN2IDMR2_AM4 _CAN2IDMR2.Bits.AM4
#define CAN2IDMR2_AM5 _CAN2IDMR2.Bits.AM5
#define CAN2IDMR2_AM6 _CAN2IDMR2.Bits.AM6
#define CAN2IDMR2_AM7 _CAN2IDMR2.Bits.AM7
#define CAN2IDMR2_AM _CAN2IDMR2.MergedBits.grpAM


/*** CAN2IDMR3 - MSCAN 2 Identifier Mask Register 3; 0x000001D7 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN2IDMR3STR;
extern volatile CAN2IDMR3STR _CAN2IDMR3 @(REG_BASE + 0x000001D7);
#define CAN2IDMR3 _CAN2IDMR3.Byte
#define CAN2IDMR3_AM0 _CAN2IDMR3.Bits.AM0
#define CAN2IDMR3_AM1 _CAN2IDMR3.Bits.AM1
#define CAN2IDMR3_AM2 _CAN2IDMR3.Bits.AM2
#define CAN2IDMR3_AM3 _CAN2IDMR3.Bits.AM3
#define CAN2IDMR3_AM4 _CAN2IDMR3.Bits.AM4
#define CAN2IDMR3_AM5 _CAN2IDMR3.Bits.AM5
#define CAN2IDMR3_AM6 _CAN2IDMR3.Bits.AM6
#define CAN2IDMR3_AM7 _CAN2IDMR3.Bits.AM7
#define CAN2IDMR3_AM _CAN2IDMR3.MergedBits.grpAM


/*** CAN2IDAR4 - MSCAN 2 Identifier Acceptance Register 4; 0x000001D8 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN2IDAR4STR;
extern volatile CAN2IDAR4STR _CAN2IDAR4 @(REG_BASE + 0x000001D8);
#define CAN2IDAR4 _CAN2IDAR4.Byte
#define CAN2IDAR4_AC0 _CAN2IDAR4.Bits.AC0
#define CAN2IDAR4_AC1 _CAN2IDAR4.Bits.AC1
#define CAN2IDAR4_AC2 _CAN2IDAR4.Bits.AC2
#define CAN2IDAR4_AC3 _CAN2IDAR4.Bits.AC3
#define CAN2IDAR4_AC4 _CAN2IDAR4.Bits.AC4
#define CAN2IDAR4_AC5 _CAN2IDAR4.Bits.AC5
#define CAN2IDAR4_AC6 _CAN2IDAR4.Bits.AC6
#define CAN2IDAR4_AC7 _CAN2IDAR4.Bits.AC7
#define CAN2IDAR4_AC _CAN2IDAR4.MergedBits.grpAC


/*** CAN2IDAR5 - MSCAN 2 Identifier Acceptance Register 5; 0x000001D9 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN2IDAR5STR;
extern volatile CAN2IDAR5STR _CAN2IDAR5 @(REG_BASE + 0x000001D9);
#define CAN2IDAR5 _CAN2IDAR5.Byte
#define CAN2IDAR5_AC0 _CAN2IDAR5.Bits.AC0
#define CAN2IDAR5_AC1 _CAN2IDAR5.Bits.AC1
#define CAN2IDAR5_AC2 _CAN2IDAR5.Bits.AC2
#define CAN2IDAR5_AC3 _CAN2IDAR5.Bits.AC3
#define CAN2IDAR5_AC4 _CAN2IDAR5.Bits.AC4
#define CAN2IDAR5_AC5 _CAN2IDAR5.Bits.AC5
#define CAN2IDAR5_AC6 _CAN2IDAR5.Bits.AC6
#define CAN2IDAR5_AC7 _CAN2IDAR5.Bits.AC7
#define CAN2IDAR5_AC _CAN2IDAR5.MergedBits.grpAC


/*** CAN2IDAR6 - MSCAN 2 Identifier Acceptance Register 6; 0x000001DA ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN2IDAR6STR;
extern volatile CAN2IDAR6STR _CAN2IDAR6 @(REG_BASE + 0x000001DA);
#define CAN2IDAR6 _CAN2IDAR6.Byte
#define CAN2IDAR6_AC0 _CAN2IDAR6.Bits.AC0
#define CAN2IDAR6_AC1 _CAN2IDAR6.Bits.AC1
#define CAN2IDAR6_AC2 _CAN2IDAR6.Bits.AC2
#define CAN2IDAR6_AC3 _CAN2IDAR6.Bits.AC3
#define CAN2IDAR6_AC4 _CAN2IDAR6.Bits.AC4
#define CAN2IDAR6_AC5 _CAN2IDAR6.Bits.AC5
#define CAN2IDAR6_AC6 _CAN2IDAR6.Bits.AC6
#define CAN2IDAR6_AC7 _CAN2IDAR6.Bits.AC7
#define CAN2IDAR6_AC _CAN2IDAR6.MergedBits.grpAC


/*** CAN2IDAR7 - MSCAN 2 Identifier Acceptance Register 7; 0x000001DB ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN2IDAR7STR;
extern volatile CAN2IDAR7STR _CAN2IDAR7 @(REG_BASE + 0x000001DB);
#define CAN2IDAR7 _CAN2IDAR7.Byte
#define CAN2IDAR7_AC0 _CAN2IDAR7.Bits.AC0
#define CAN2IDAR7_AC1 _CAN2IDAR7.Bits.AC1
#define CAN2IDAR7_AC2 _CAN2IDAR7.Bits.AC2
#define CAN2IDAR7_AC3 _CAN2IDAR7.Bits.AC3
#define CAN2IDAR7_AC4 _CAN2IDAR7.Bits.AC4
#define CAN2IDAR7_AC5 _CAN2IDAR7.Bits.AC5
#define CAN2IDAR7_AC6 _CAN2IDAR7.Bits.AC6
#define CAN2IDAR7_AC7 _CAN2IDAR7.Bits.AC7
#define CAN2IDAR7_AC _CAN2IDAR7.MergedBits.grpAC


/*** CAN2IDMR4 - MSCAN 2 Identifier Mask Register 4; 0x000001DC ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN2IDMR4STR;
extern volatile CAN2IDMR4STR _CAN2IDMR4 @(REG_BASE + 0x000001DC);
#define CAN2IDMR4 _CAN2IDMR4.Byte
#define CAN2IDMR4_AM0 _CAN2IDMR4.Bits.AM0
#define CAN2IDMR4_AM1 _CAN2IDMR4.Bits.AM1
#define CAN2IDMR4_AM2 _CAN2IDMR4.Bits.AM2
#define CAN2IDMR4_AM3 _CAN2IDMR4.Bits.AM3
#define CAN2IDMR4_AM4 _CAN2IDMR4.Bits.AM4
#define CAN2IDMR4_AM5 _CAN2IDMR4.Bits.AM5
#define CAN2IDMR4_AM6 _CAN2IDMR4.Bits.AM6
#define CAN2IDMR4_AM7 _CAN2IDMR4.Bits.AM7
#define CAN2IDMR4_AM _CAN2IDMR4.MergedBits.grpAM


/*** CAN2IDMR5 - MSCAN 2 Identifier Mask Register 5; 0x000001DD ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN2IDMR5STR;
extern volatile CAN2IDMR5STR _CAN2IDMR5 @(REG_BASE + 0x000001DD);
#define CAN2IDMR5 _CAN2IDMR5.Byte
#define CAN2IDMR5_AM0 _CAN2IDMR5.Bits.AM0
#define CAN2IDMR5_AM1 _CAN2IDMR5.Bits.AM1
#define CAN2IDMR5_AM2 _CAN2IDMR5.Bits.AM2
#define CAN2IDMR5_AM3 _CAN2IDMR5.Bits.AM3
#define CAN2IDMR5_AM4 _CAN2IDMR5.Bits.AM4
#define CAN2IDMR5_AM5 _CAN2IDMR5.Bits.AM5
#define CAN2IDMR5_AM6 _CAN2IDMR5.Bits.AM6
#define CAN2IDMR5_AM7 _CAN2IDMR5.Bits.AM7
#define CAN2IDMR5_AM _CAN2IDMR5.MergedBits.grpAM


/*** CAN2IDMR6 - MSCAN 2 Identifier Mask Register 6; 0x000001DE ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN2IDMR6STR;
extern volatile CAN2IDMR6STR _CAN2IDMR6 @(REG_BASE + 0x000001DE);
#define CAN2IDMR6 _CAN2IDMR6.Byte
#define CAN2IDMR6_AM0 _CAN2IDMR6.Bits.AM0
#define CAN2IDMR6_AM1 _CAN2IDMR6.Bits.AM1
#define CAN2IDMR6_AM2 _CAN2IDMR6.Bits.AM2
#define CAN2IDMR6_AM3 _CAN2IDMR6.Bits.AM3
#define CAN2IDMR6_AM4 _CAN2IDMR6.Bits.AM4
#define CAN2IDMR6_AM5 _CAN2IDMR6.Bits.AM5
#define CAN2IDMR6_AM6 _CAN2IDMR6.Bits.AM6
#define CAN2IDMR6_AM7 _CAN2IDMR6.Bits.AM7
#define CAN2IDMR6_AM _CAN2IDMR6.MergedBits.grpAM


/*** CAN2IDMR7 - MSCAN 2 Identifier Mask Register 7; 0x000001DF ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN2IDMR7STR;
extern volatile CAN2IDMR7STR _CAN2IDMR7 @(REG_BASE + 0x000001DF);
#define CAN2IDMR7 _CAN2IDMR7.Byte
#define CAN2IDMR7_AM0 _CAN2IDMR7.Bits.AM0
#define CAN2IDMR7_AM1 _CAN2IDMR7.Bits.AM1
#define CAN2IDMR7_AM2 _CAN2IDMR7.Bits.AM2
#define CAN2IDMR7_AM3 _CAN2IDMR7.Bits.AM3
#define CAN2IDMR7_AM4 _CAN2IDMR7.Bits.AM4
#define CAN2IDMR7_AM5 _CAN2IDMR7.Bits.AM5
#define CAN2IDMR7_AM6 _CAN2IDMR7.Bits.AM6
#define CAN2IDMR7_AM7 _CAN2IDMR7.Bits.AM7
#define CAN2IDMR7_AM _CAN2IDMR7.MergedBits.grpAM


/*** CAN2RXIDR0 - MSCAN 2 Receive Identifier Register 0; 0x000001E0 ***/
typedef union {
  byte Byte;
  struct {
    byte ID21        :1;                                       /* Extended format identifier Bit 21 */
    byte ID22        :1;                                       /* Extended format identifier Bit 22 */
    byte ID23        :1;                                       /* Extended format identifier Bit 23 */
    byte ID24        :1;                                       /* Extended format identifier Bit 24 */
    byte ID25        :1;                                       /* Extended format identifier Bit 25 */
    byte ID26        :1;                                       /* Extended format identifier Bit 26 */
    byte ID27        :1;                                       /* Extended format identifier Bit 27 */
    byte ID28        :1;                                       /* Extended format identifier Bit 28 */
  } Bits;
  struct {
    byte grpID_21 :8;
  } MergedBits;
} CAN2RXIDR0STR;
extern volatile CAN2RXIDR0STR _CAN2RXIDR0 @(REG_BASE + 0x000001E0);
#define CAN2RXIDR0 _CAN2RXIDR0.Byte
#define CAN2RXIDR0_ID21 _CAN2RXIDR0.Bits.ID21
#define CAN2RXIDR0_ID22 _CAN2RXIDR0.Bits.ID22
#define CAN2RXIDR0_ID23 _CAN2RXIDR0.Bits.ID23
#define CAN2RXIDR0_ID24 _CAN2RXIDR0.Bits.ID24
#define CAN2RXIDR0_ID25 _CAN2RXIDR0.Bits.ID25
#define CAN2RXIDR0_ID26 _CAN2RXIDR0.Bits.ID26
#define CAN2RXIDR0_ID27 _CAN2RXIDR0.Bits.ID27
#define CAN2RXIDR0_ID28 _CAN2RXIDR0.Bits.ID28
#define CAN2RXIDR0_ID_21 _CAN2RXIDR0.MergedBits.grpID_21
#define CAN2RXIDR0_ID CAN2RXIDR0_ID_21


/*** CAN2RXIDR1 - MSCAN 2 Receive Identifier Register 1; 0x000001E1 ***/
typedef union {
  byte Byte;
  struct {
    byte ID15        :1;                                       /* Extended format identifier Bit 15 */
    byte ID16        :1;                                       /* Extended format identifier Bit 16 */
    byte ID17        :1;                                       /* Extended format identifier Bit 17 */
    byte IDE         :1;                                       /* ID Extended */
    byte SRR         :1;                                       /* Substitute Remote Request */
    byte ID18        :1;                                       /* Extended format identifier Bit 18 */
    byte ID19        :1;                                       /* Extended format identifier Bit 19 */
    byte ID20        :1;                                       /* Extended format identifier Bit 20 */
  } Bits;
  struct {
    byte grpID_15 :3;
    byte         :1;
    byte         :1;
    byte grpID_18 :3;
  } MergedBits;
} CAN2RXIDR1STR;
extern volatile CAN2RXIDR1STR _CAN2RXIDR1 @(REG_BASE + 0x000001E1);
#define CAN2RXIDR1 _CAN2RXIDR1.Byte
#define CAN2RXIDR1_ID15 _CAN2RXIDR1.Bits.ID15
#define CAN2RXIDR1_ID16 _CAN2RXIDR1.Bits.ID16
#define CAN2RXIDR1_ID17 _CAN2RXIDR1.Bits.ID17
#define CAN2RXIDR1_IDE _CAN2RXIDR1.Bits.IDE
#define CAN2RXIDR1_SRR _CAN2RXIDR1.Bits.SRR
#define CAN2RXIDR1_ID18 _CAN2RXIDR1.Bits.ID18
#define CAN2RXIDR1_ID19 _CAN2RXIDR1.Bits.ID19
#define CAN2RXIDR1_ID20 _CAN2RXIDR1.Bits.ID20
#define CAN2RXIDR1_ID_15 _CAN2RXIDR1.MergedBits.grpID_15
#define CAN2RXIDR1_ID_18 _CAN2RXIDR1.MergedBits.grpID_18
#define CAN2RXIDR1_ID CAN2RXIDR1_ID_15


/*** CAN2RXIDR2 - MSCAN 2 Receive Identifier Register 2; 0x000001E2 ***/
typedef union {
  byte Byte;
  struct {
    byte ID7         :1;                                       /* Extended format identifier Bit 7 */
    byte ID8         :1;                                       /* Extended format identifier Bit 8 */
    byte ID9         :1;                                       /* Extended format identifier Bit 9 */
    byte ID10        :1;                                       /* Extended format identifier Bit 10 */
    byte ID11        :1;                                       /* Extended format identifier Bit 11 */
    byte ID12        :1;                                       /* Extended format identifier Bit 12 */
    byte ID13        :1;                                       /* Extended format identifier Bit 13 */
    byte ID14        :1;                                       /* Extended format identifier Bit 14 */
  } Bits;
  struct {
    byte grpID_7 :8;
  } MergedBits;
} CAN2RXIDR2STR;
extern volatile CAN2RXIDR2STR _CAN2RXIDR2 @(REG_BASE + 0x000001E2);
#define CAN2RXIDR2 _CAN2RXIDR2.Byte
#define CAN2RXIDR2_ID7 _CAN2RXIDR2.Bits.ID7
#define CAN2RXIDR2_ID8 _CAN2RXIDR2.Bits.ID8
#define CAN2RXIDR2_ID9 _CAN2RXIDR2.Bits.ID9
#define CAN2RXIDR2_ID10 _CAN2RXIDR2.Bits.ID10
#define CAN2RXIDR2_ID11 _CAN2RXIDR2.Bits.ID11
#define CAN2RXIDR2_ID12 _CAN2RXIDR2.Bits.ID12
#define CAN2RXIDR2_ID13 _CAN2RXIDR2.Bits.ID13
#define CAN2RXIDR2_ID14 _CAN2RXIDR2.Bits.ID14
#define CAN2RXIDR2_ID_7 _CAN2RXIDR2.MergedBits.grpID_7
#define CAN2RXIDR2_ID CAN2RXIDR2_ID_7


/*** CAN2RXIDR3 - MSCAN 2 Receive Identifier Register 3; 0x000001E3 ***/
typedef union {
  byte Byte;
  struct {
    byte RTR         :1;                                       /* Remote Transmission Request */
    byte ID0         :1;                                       /* Extended format identifier Bit 0 */
    byte ID1         :1;                                       /* Extended format identifier Bit 1 */
    byte ID2         :1;                                       /* Extended format identifier Bit 2 */
    byte ID3         :1;                                       /* Extended format identifier Bit 3 */
    byte ID4         :1;                                       /* Extended format identifier Bit 4 */
    byte ID5         :1;                                       /* Extended format identifier Bit 5 */
    byte ID6         :1;                                       /* Extended format identifier Bit 6 */
  } Bits;
  struct {
    byte         :1;
    byte grpID   :7;
  } MergedBits;
} CAN2RXIDR3STR;
extern volatile CAN2RXIDR3STR _CAN2RXIDR3 @(REG_BASE + 0x000001E3);
#define CAN2RXIDR3 _CAN2RXIDR3.Byte
#define CAN2RXIDR3_RTR _CAN2RXIDR3.Bits.RTR
#define CAN2RXIDR3_ID0 _CAN2RXIDR3.Bits.ID0
#define CAN2RXIDR3_ID1 _CAN2RXIDR3.Bits.ID1
#define CAN2RXIDR3_ID2 _CAN2RXIDR3.Bits.ID2
#define CAN2RXIDR3_ID3 _CAN2RXIDR3.Bits.ID3
#define CAN2RXIDR3_ID4 _CAN2RXIDR3.Bits.ID4
#define CAN2RXIDR3_ID5 _CAN2RXIDR3.Bits.ID5
#define CAN2RXIDR3_ID6 _CAN2RXIDR3.Bits.ID6
#define CAN2RXIDR3_ID _CAN2RXIDR3.MergedBits.grpID


/*** CAN2RXDSR0 - MSCAN 2 Receive Data Segment Register 0; 0x000001E4 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2RXDSR0STR;
extern volatile CAN2RXDSR0STR _CAN2RXDSR0 @(REG_BASE + 0x000001E4);
#define CAN2RXDSR0 _CAN2RXDSR0.Byte
#define CAN2RXDSR0_DB0 _CAN2RXDSR0.Bits.DB0
#define CAN2RXDSR0_DB1 _CAN2RXDSR0.Bits.DB1
#define CAN2RXDSR0_DB2 _CAN2RXDSR0.Bits.DB2
#define CAN2RXDSR0_DB3 _CAN2RXDSR0.Bits.DB3
#define CAN2RXDSR0_DB4 _CAN2RXDSR0.Bits.DB4
#define CAN2RXDSR0_DB5 _CAN2RXDSR0.Bits.DB5
#define CAN2RXDSR0_DB6 _CAN2RXDSR0.Bits.DB6
#define CAN2RXDSR0_DB7 _CAN2RXDSR0.Bits.DB7
#define CAN2RXDSR0_DB _CAN2RXDSR0.MergedBits.grpDB


/*** CAN2RXDSR1 - MSCAN 2 Receive Data Segment Register 1; 0x000001E5 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2RXDSR1STR;
extern volatile CAN2RXDSR1STR _CAN2RXDSR1 @(REG_BASE + 0x000001E5);
#define CAN2RXDSR1 _CAN2RXDSR1.Byte
#define CAN2RXDSR1_DB0 _CAN2RXDSR1.Bits.DB0
#define CAN2RXDSR1_DB1 _CAN2RXDSR1.Bits.DB1
#define CAN2RXDSR1_DB2 _CAN2RXDSR1.Bits.DB2
#define CAN2RXDSR1_DB3 _CAN2RXDSR1.Bits.DB3
#define CAN2RXDSR1_DB4 _CAN2RXDSR1.Bits.DB4
#define CAN2RXDSR1_DB5 _CAN2RXDSR1.Bits.DB5
#define CAN2RXDSR1_DB6 _CAN2RXDSR1.Bits.DB6
#define CAN2RXDSR1_DB7 _CAN2RXDSR1.Bits.DB7
#define CAN2RXDSR1_DB _CAN2RXDSR1.MergedBits.grpDB


/*** CAN2RXDSR2 - MSCAN 2 Receive Data Segment Register 2; 0x000001E6 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2RXDSR2STR;
extern volatile CAN2RXDSR2STR _CAN2RXDSR2 @(REG_BASE + 0x000001E6);
#define CAN2RXDSR2 _CAN2RXDSR2.Byte
#define CAN2RXDSR2_DB0 _CAN2RXDSR2.Bits.DB0
#define CAN2RXDSR2_DB1 _CAN2RXDSR2.Bits.DB1
#define CAN2RXDSR2_DB2 _CAN2RXDSR2.Bits.DB2
#define CAN2RXDSR2_DB3 _CAN2RXDSR2.Bits.DB3
#define CAN2RXDSR2_DB4 _CAN2RXDSR2.Bits.DB4
#define CAN2RXDSR2_DB5 _CAN2RXDSR2.Bits.DB5
#define CAN2RXDSR2_DB6 _CAN2RXDSR2.Bits.DB6
#define CAN2RXDSR2_DB7 _CAN2RXDSR2.Bits.DB7
#define CAN2RXDSR2_DB _CAN2RXDSR2.MergedBits.grpDB


/*** CAN2RXDSR3 - MSCAN 2 Receive Data Segment Register 3; 0x000001E7 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2RXDSR3STR;
extern volatile CAN2RXDSR3STR _CAN2RXDSR3 @(REG_BASE + 0x000001E7);
#define CAN2RXDSR3 _CAN2RXDSR3.Byte
#define CAN2RXDSR3_DB0 _CAN2RXDSR3.Bits.DB0
#define CAN2RXDSR3_DB1 _CAN2RXDSR3.Bits.DB1
#define CAN2RXDSR3_DB2 _CAN2RXDSR3.Bits.DB2
#define CAN2RXDSR3_DB3 _CAN2RXDSR3.Bits.DB3
#define CAN2RXDSR3_DB4 _CAN2RXDSR3.Bits.DB4
#define CAN2RXDSR3_DB5 _CAN2RXDSR3.Bits.DB5
#define CAN2RXDSR3_DB6 _CAN2RXDSR3.Bits.DB6
#define CAN2RXDSR3_DB7 _CAN2RXDSR3.Bits.DB7
#define CAN2RXDSR3_DB _CAN2RXDSR3.MergedBits.grpDB


/*** CAN2RXDSR4 - MSCAN 2 Receive Data Segment Register 4; 0x000001E8 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2RXDSR4STR;
extern volatile CAN2RXDSR4STR _CAN2RXDSR4 @(REG_BASE + 0x000001E8);
#define CAN2RXDSR4 _CAN2RXDSR4.Byte
#define CAN2RXDSR4_DB0 _CAN2RXDSR4.Bits.DB0
#define CAN2RXDSR4_DB1 _CAN2RXDSR4.Bits.DB1
#define CAN2RXDSR4_DB2 _CAN2RXDSR4.Bits.DB2
#define CAN2RXDSR4_DB3 _CAN2RXDSR4.Bits.DB3
#define CAN2RXDSR4_DB4 _CAN2RXDSR4.Bits.DB4
#define CAN2RXDSR4_DB5 _CAN2RXDSR4.Bits.DB5
#define CAN2RXDSR4_DB6 _CAN2RXDSR4.Bits.DB6
#define CAN2RXDSR4_DB7 _CAN2RXDSR4.Bits.DB7
#define CAN2RXDSR4_DB _CAN2RXDSR4.MergedBits.grpDB


/*** CAN2RXDSR5 - MSCAN 2 Receive Data Segment Register 5; 0x000001E9 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2RXDSR5STR;
extern volatile CAN2RXDSR5STR _CAN2RXDSR5 @(REG_BASE + 0x000001E9);
#define CAN2RXDSR5 _CAN2RXDSR5.Byte
#define CAN2RXDSR5_DB0 _CAN2RXDSR5.Bits.DB0
#define CAN2RXDSR5_DB1 _CAN2RXDSR5.Bits.DB1
#define CAN2RXDSR5_DB2 _CAN2RXDSR5.Bits.DB2
#define CAN2RXDSR5_DB3 _CAN2RXDSR5.Bits.DB3
#define CAN2RXDSR5_DB4 _CAN2RXDSR5.Bits.DB4
#define CAN2RXDSR5_DB5 _CAN2RXDSR5.Bits.DB5
#define CAN2RXDSR5_DB6 _CAN2RXDSR5.Bits.DB6
#define CAN2RXDSR5_DB7 _CAN2RXDSR5.Bits.DB7
#define CAN2RXDSR5_DB _CAN2RXDSR5.MergedBits.grpDB


/*** CAN2RXDSR6 - MSCAN 2 Receive Data Segment Register 6; 0x000001EA ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2RXDSR6STR;
extern volatile CAN2RXDSR6STR _CAN2RXDSR6 @(REG_BASE + 0x000001EA);
#define CAN2RXDSR6 _CAN2RXDSR6.Byte
#define CAN2RXDSR6_DB0 _CAN2RXDSR6.Bits.DB0
#define CAN2RXDSR6_DB1 _CAN2RXDSR6.Bits.DB1
#define CAN2RXDSR6_DB2 _CAN2RXDSR6.Bits.DB2
#define CAN2RXDSR6_DB3 _CAN2RXDSR6.Bits.DB3
#define CAN2RXDSR6_DB4 _CAN2RXDSR6.Bits.DB4
#define CAN2RXDSR6_DB5 _CAN2RXDSR6.Bits.DB5
#define CAN2RXDSR6_DB6 _CAN2RXDSR6.Bits.DB6
#define CAN2RXDSR6_DB7 _CAN2RXDSR6.Bits.DB7
#define CAN2RXDSR6_DB _CAN2RXDSR6.MergedBits.grpDB


/*** CAN2RXDSR7 - MSCAN 2 Receive Data Segment Register 7; 0x000001EB ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2RXDSR7STR;
extern volatile CAN2RXDSR7STR _CAN2RXDSR7 @(REG_BASE + 0x000001EB);
#define CAN2RXDSR7 _CAN2RXDSR7.Byte
#define CAN2RXDSR7_DB0 _CAN2RXDSR7.Bits.DB0
#define CAN2RXDSR7_DB1 _CAN2RXDSR7.Bits.DB1
#define CAN2RXDSR7_DB2 _CAN2RXDSR7.Bits.DB2
#define CAN2RXDSR7_DB3 _CAN2RXDSR7.Bits.DB3
#define CAN2RXDSR7_DB4 _CAN2RXDSR7.Bits.DB4
#define CAN2RXDSR7_DB5 _CAN2RXDSR7.Bits.DB5
#define CAN2RXDSR7_DB6 _CAN2RXDSR7.Bits.DB6
#define CAN2RXDSR7_DB7 _CAN2RXDSR7.Bits.DB7
#define CAN2RXDSR7_DB _CAN2RXDSR7.MergedBits.grpDB


/*** CAN2RXDLR - MSCAN 2 Receive Data Length Register; 0x000001EC ***/
typedef union {
  byte Byte;
  struct {
    byte DLC0        :1;                                       /* Data Length Code Bit 0 */
    byte DLC1        :1;                                       /* Data Length Code Bit 1 */
    byte DLC2        :1;                                       /* Data Length Code Bit 2 */
    byte DLC3        :1;                                       /* Data Length Code Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDLC  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN2RXDLRSTR;
extern volatile CAN2RXDLRSTR _CAN2RXDLR @(REG_BASE + 0x000001EC);
#define CAN2RXDLR _CAN2RXDLR.Byte
#define CAN2RXDLR_DLC0 _CAN2RXDLR.Bits.DLC0
#define CAN2RXDLR_DLC1 _CAN2RXDLR.Bits.DLC1
#define CAN2RXDLR_DLC2 _CAN2RXDLR.Bits.DLC2
#define CAN2RXDLR_DLC3 _CAN2RXDLR.Bits.DLC3
#define CAN2RXDLR_DLC _CAN2RXDLR.MergedBits.grpDLC


/*** CAN2TXIDR0 - MSCAN 2 Transmit Identifier Register 0; 0x000001F0 ***/
typedef union {
  byte Byte;
  struct {
    byte ID21        :1;                                       /* Extended format identifier Bit 21 */
    byte ID22        :1;                                       /* Extended format identifier Bit 22 */
    byte ID23        :1;                                       /* Extended format identifier Bit 23 */
    byte ID24        :1;                                       /* Extended format identifier Bit 24 */
    byte ID25        :1;                                       /* Extended format identifier Bit 25 */
    byte ID26        :1;                                       /* Extended format identifier Bit 26 */
    byte ID27        :1;                                       /* Extended format identifier Bit 27 */
    byte ID28        :1;                                       /* Extended format identifier Bit 28 */
  } Bits;
  struct {
    byte grpID_21 :8;
  } MergedBits;
} CAN2TXIDR0STR;
extern volatile CAN2TXIDR0STR _CAN2TXIDR0 @(REG_BASE + 0x000001F0);
#define CAN2TXIDR0 _CAN2TXIDR0.Byte
#define CAN2TXIDR0_ID21 _CAN2TXIDR0.Bits.ID21
#define CAN2TXIDR0_ID22 _CAN2TXIDR0.Bits.ID22
#define CAN2TXIDR0_ID23 _CAN2TXIDR0.Bits.ID23
#define CAN2TXIDR0_ID24 _CAN2TXIDR0.Bits.ID24
#define CAN2TXIDR0_ID25 _CAN2TXIDR0.Bits.ID25
#define CAN2TXIDR0_ID26 _CAN2TXIDR0.Bits.ID26
#define CAN2TXIDR0_ID27 _CAN2TXIDR0.Bits.ID27
#define CAN2TXIDR0_ID28 _CAN2TXIDR0.Bits.ID28
#define CAN2TXIDR0_ID_21 _CAN2TXIDR0.MergedBits.grpID_21
#define CAN2TXIDR0_ID CAN2TXIDR0_ID_21


/*** CAN2TXIDR1 - MSCAN 2 Transmit Identifier Register 1; 0x000001F1 ***/
typedef union {
  byte Byte;
  struct {
    byte ID15        :1;                                       /* Extended format identifier Bit 15 */
    byte ID16        :1;                                       /* Extended format identifier Bit 16 */
    byte ID17        :1;                                       /* Extended format identifier Bit 17 */
    byte IDE         :1;                                       /* ID Extended */
    byte SRR         :1;                                       /* Substitute Remote Request */
    byte ID18        :1;                                       /* Extended format identifier Bit 18 */
    byte ID19        :1;                                       /* Extended format identifier Bit 19 */
    byte ID20        :1;                                       /* Extended format identifier Bit 20 */
  } Bits;
  struct {
    byte grpID_15 :3;
    byte         :1;
    byte         :1;
    byte grpID_18 :3;
  } MergedBits;
} CAN2TXIDR1STR;
extern volatile CAN2TXIDR1STR _CAN2TXIDR1 @(REG_BASE + 0x000001F1);
#define CAN2TXIDR1 _CAN2TXIDR1.Byte
#define CAN2TXIDR1_ID15 _CAN2TXIDR1.Bits.ID15
#define CAN2TXIDR1_ID16 _CAN2TXIDR1.Bits.ID16
#define CAN2TXIDR1_ID17 _CAN2TXIDR1.Bits.ID17
#define CAN2TXIDR1_IDE _CAN2TXIDR1.Bits.IDE
#define CAN2TXIDR1_SRR _CAN2TXIDR1.Bits.SRR
#define CAN2TXIDR1_ID18 _CAN2TXIDR1.Bits.ID18
#define CAN2TXIDR1_ID19 _CAN2TXIDR1.Bits.ID19
#define CAN2TXIDR1_ID20 _CAN2TXIDR1.Bits.ID20
#define CAN2TXIDR1_ID_15 _CAN2TXIDR1.MergedBits.grpID_15
#define CAN2TXIDR1_ID_18 _CAN2TXIDR1.MergedBits.grpID_18
#define CAN2TXIDR1_ID CAN2TXIDR1_ID_15


/*** CAN2TXIDR2 - MSCAN 2 Transmit Identifier Register 2; 0x000001F2 ***/
typedef union {
  byte Byte;
  struct {
    byte ID7         :1;                                       /* Extended format identifier Bit 7 */
    byte ID8         :1;                                       /* Extended format identifier Bit 8 */
    byte ID9         :1;                                       /* Extended format identifier Bit 9 */
    byte ID10        :1;                                       /* Extended format identifier Bit 10 */
    byte ID11        :1;                                       /* Extended format identifier Bit 11 */
    byte ID12        :1;                                       /* Extended format identifier Bit 12 */
    byte ID13        :1;                                       /* Extended format identifier Bit 13 */
    byte ID14        :1;                                       /* Extended format identifier Bit 14 */
  } Bits;
  struct {
    byte grpID_7 :8;
  } MergedBits;
} CAN2TXIDR2STR;
extern volatile CAN2TXIDR2STR _CAN2TXIDR2 @(REG_BASE + 0x000001F2);
#define CAN2TXIDR2 _CAN2TXIDR2.Byte
#define CAN2TXIDR2_ID7 _CAN2TXIDR2.Bits.ID7
#define CAN2TXIDR2_ID8 _CAN2TXIDR2.Bits.ID8
#define CAN2TXIDR2_ID9 _CAN2TXIDR2.Bits.ID9
#define CAN2TXIDR2_ID10 _CAN2TXIDR2.Bits.ID10
#define CAN2TXIDR2_ID11 _CAN2TXIDR2.Bits.ID11
#define CAN2TXIDR2_ID12 _CAN2TXIDR2.Bits.ID12
#define CAN2TXIDR2_ID13 _CAN2TXIDR2.Bits.ID13
#define CAN2TXIDR2_ID14 _CAN2TXIDR2.Bits.ID14
#define CAN2TXIDR2_ID_7 _CAN2TXIDR2.MergedBits.grpID_7
#define CAN2TXIDR2_ID CAN2TXIDR2_ID_7


/*** CAN2TXIDR3 - MSCAN 2 Transmit Identifier Register 3; 0x000001F3 ***/
typedef union {
  byte Byte;
  struct {
    byte RTR         :1;                                       /* Remote Transmission Request */
    byte ID0         :1;                                       /* Extended format identifier Bit 0 */
    byte ID1         :1;                                       /* Extended format identifier Bit 1 */
    byte ID2         :1;                                       /* Extended format identifier Bit 2 */
    byte ID3         :1;                                       /* Extended format identifier Bit 3 */
    byte ID4         :1;                                       /* Extended format identifier Bit 4 */
    byte ID5         :1;                                       /* Extended format identifier Bit 5 */
    byte ID6         :1;                                       /* Extended format identifier Bit 6 */
  } Bits;
  struct {
    byte         :1;
    byte grpID   :7;
  } MergedBits;
} CAN2TXIDR3STR;
extern volatile CAN2TXIDR3STR _CAN2TXIDR3 @(REG_BASE + 0x000001F3);
#define CAN2TXIDR3 _CAN2TXIDR3.Byte
#define CAN2TXIDR3_RTR _CAN2TXIDR3.Bits.RTR
#define CAN2TXIDR3_ID0 _CAN2TXIDR3.Bits.ID0
#define CAN2TXIDR3_ID1 _CAN2TXIDR3.Bits.ID1
#define CAN2TXIDR3_ID2 _CAN2TXIDR3.Bits.ID2
#define CAN2TXIDR3_ID3 _CAN2TXIDR3.Bits.ID3
#define CAN2TXIDR3_ID4 _CAN2TXIDR3.Bits.ID4
#define CAN2TXIDR3_ID5 _CAN2TXIDR3.Bits.ID5
#define CAN2TXIDR3_ID6 _CAN2TXIDR3.Bits.ID6
#define CAN2TXIDR3_ID _CAN2TXIDR3.MergedBits.grpID


/*** CAN2TXDSR0 - MSCAN 2 Transmit Data Segment Register 0; 0x000001F4 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2TXDSR0STR;
extern volatile CAN2TXDSR0STR _CAN2TXDSR0 @(REG_BASE + 0x000001F4);
#define CAN2TXDSR0 _CAN2TXDSR0.Byte
#define CAN2TXDSR0_DB0 _CAN2TXDSR0.Bits.DB0
#define CAN2TXDSR0_DB1 _CAN2TXDSR0.Bits.DB1
#define CAN2TXDSR0_DB2 _CAN2TXDSR0.Bits.DB2
#define CAN2TXDSR0_DB3 _CAN2TXDSR0.Bits.DB3
#define CAN2TXDSR0_DB4 _CAN2TXDSR0.Bits.DB4
#define CAN2TXDSR0_DB5 _CAN2TXDSR0.Bits.DB5
#define CAN2TXDSR0_DB6 _CAN2TXDSR0.Bits.DB6
#define CAN2TXDSR0_DB7 _CAN2TXDSR0.Bits.DB7
#define CAN2TXDSR0_DB _CAN2TXDSR0.MergedBits.grpDB


/*** CAN2TXDSR1 - MSCAN 2 Transmit Data Segment Register 1; 0x000001F5 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2TXDSR1STR;
extern volatile CAN2TXDSR1STR _CAN2TXDSR1 @(REG_BASE + 0x000001F5);
#define CAN2TXDSR1 _CAN2TXDSR1.Byte
#define CAN2TXDSR1_DB0 _CAN2TXDSR1.Bits.DB0
#define CAN2TXDSR1_DB1 _CAN2TXDSR1.Bits.DB1
#define CAN2TXDSR1_DB2 _CAN2TXDSR1.Bits.DB2
#define CAN2TXDSR1_DB3 _CAN2TXDSR1.Bits.DB3
#define CAN2TXDSR1_DB4 _CAN2TXDSR1.Bits.DB4
#define CAN2TXDSR1_DB5 _CAN2TXDSR1.Bits.DB5
#define CAN2TXDSR1_DB6 _CAN2TXDSR1.Bits.DB6
#define CAN2TXDSR1_DB7 _CAN2TXDSR1.Bits.DB7
#define CAN2TXDSR1_DB _CAN2TXDSR1.MergedBits.grpDB


/*** CAN2TXDSR2 - MSCAN 2 Transmit Data Segment Register 2; 0x000001F6 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2TXDSR2STR;
extern volatile CAN2TXDSR2STR _CAN2TXDSR2 @(REG_BASE + 0x000001F6);
#define CAN2TXDSR2 _CAN2TXDSR2.Byte
#define CAN2TXDSR2_DB0 _CAN2TXDSR2.Bits.DB0
#define CAN2TXDSR2_DB1 _CAN2TXDSR2.Bits.DB1
#define CAN2TXDSR2_DB2 _CAN2TXDSR2.Bits.DB2
#define CAN2TXDSR2_DB3 _CAN2TXDSR2.Bits.DB3
#define CAN2TXDSR2_DB4 _CAN2TXDSR2.Bits.DB4
#define CAN2TXDSR2_DB5 _CAN2TXDSR2.Bits.DB5
#define CAN2TXDSR2_DB6 _CAN2TXDSR2.Bits.DB6
#define CAN2TXDSR2_DB7 _CAN2TXDSR2.Bits.DB7
#define CAN2TXDSR2_DB _CAN2TXDSR2.MergedBits.grpDB


/*** CAN2TXDSR3 - MSCAN 2 Transmit Data Segment Register 3; 0x000001F7 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2TXDSR3STR;
extern volatile CAN2TXDSR3STR _CAN2TXDSR3 @(REG_BASE + 0x000001F7);
#define CAN2TXDSR3 _CAN2TXDSR3.Byte
#define CAN2TXDSR3_DB0 _CAN2TXDSR3.Bits.DB0
#define CAN2TXDSR3_DB1 _CAN2TXDSR3.Bits.DB1
#define CAN2TXDSR3_DB2 _CAN2TXDSR3.Bits.DB2
#define CAN2TXDSR3_DB3 _CAN2TXDSR3.Bits.DB3
#define CAN2TXDSR3_DB4 _CAN2TXDSR3.Bits.DB4
#define CAN2TXDSR3_DB5 _CAN2TXDSR3.Bits.DB5
#define CAN2TXDSR3_DB6 _CAN2TXDSR3.Bits.DB6
#define CAN2TXDSR3_DB7 _CAN2TXDSR3.Bits.DB7
#define CAN2TXDSR3_DB _CAN2TXDSR3.MergedBits.grpDB


/*** CAN2TXDSR4 - MSCAN 2 Transmit Data Segment Register 4; 0x000001F8 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2TXDSR4STR;
extern volatile CAN2TXDSR4STR _CAN2TXDSR4 @(REG_BASE + 0x000001F8);
#define CAN2TXDSR4 _CAN2TXDSR4.Byte
#define CAN2TXDSR4_DB0 _CAN2TXDSR4.Bits.DB0
#define CAN2TXDSR4_DB1 _CAN2TXDSR4.Bits.DB1
#define CAN2TXDSR4_DB2 _CAN2TXDSR4.Bits.DB2
#define CAN2TXDSR4_DB3 _CAN2TXDSR4.Bits.DB3
#define CAN2TXDSR4_DB4 _CAN2TXDSR4.Bits.DB4
#define CAN2TXDSR4_DB5 _CAN2TXDSR4.Bits.DB5
#define CAN2TXDSR4_DB6 _CAN2TXDSR4.Bits.DB6
#define CAN2TXDSR4_DB7 _CAN2TXDSR4.Bits.DB7
#define CAN2TXDSR4_DB _CAN2TXDSR4.MergedBits.grpDB


/*** CAN2TXDSR5 - MSCAN 2 Transmit Data Segment Register 5; 0x000001F9 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2TXDSR5STR;
extern volatile CAN2TXDSR5STR _CAN2TXDSR5 @(REG_BASE + 0x000001F9);
#define CAN2TXDSR5 _CAN2TXDSR5.Byte
#define CAN2TXDSR5_DB0 _CAN2TXDSR5.Bits.DB0
#define CAN2TXDSR5_DB1 _CAN2TXDSR5.Bits.DB1
#define CAN2TXDSR5_DB2 _CAN2TXDSR5.Bits.DB2
#define CAN2TXDSR5_DB3 _CAN2TXDSR5.Bits.DB3
#define CAN2TXDSR5_DB4 _CAN2TXDSR5.Bits.DB4
#define CAN2TXDSR5_DB5 _CAN2TXDSR5.Bits.DB5
#define CAN2TXDSR5_DB6 _CAN2TXDSR5.Bits.DB6
#define CAN2TXDSR5_DB7 _CAN2TXDSR5.Bits.DB7
#define CAN2TXDSR5_DB _CAN2TXDSR5.MergedBits.grpDB


/*** CAN2TXDSR6 - MSCAN 2 Transmit Data Segment Register 6; 0x000001FA ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2TXDSR6STR;
extern volatile CAN2TXDSR6STR _CAN2TXDSR6 @(REG_BASE + 0x000001FA);
#define CAN2TXDSR6 _CAN2TXDSR6.Byte
#define CAN2TXDSR6_DB0 _CAN2TXDSR6.Bits.DB0
#define CAN2TXDSR6_DB1 _CAN2TXDSR6.Bits.DB1
#define CAN2TXDSR6_DB2 _CAN2TXDSR6.Bits.DB2
#define CAN2TXDSR6_DB3 _CAN2TXDSR6.Bits.DB3
#define CAN2TXDSR6_DB4 _CAN2TXDSR6.Bits.DB4
#define CAN2TXDSR6_DB5 _CAN2TXDSR6.Bits.DB5
#define CAN2TXDSR6_DB6 _CAN2TXDSR6.Bits.DB6
#define CAN2TXDSR6_DB7 _CAN2TXDSR6.Bits.DB7
#define CAN2TXDSR6_DB _CAN2TXDSR6.MergedBits.grpDB


/*** CAN2TXDSR7 - MSCAN 2 Transmit Data Segment Register 7; 0x000001FB ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN2TXDSR7STR;
extern volatile CAN2TXDSR7STR _CAN2TXDSR7 @(REG_BASE + 0x000001FB);
#define CAN2TXDSR7 _CAN2TXDSR7.Byte
#define CAN2TXDSR7_DB0 _CAN2TXDSR7.Bits.DB0
#define CAN2TXDSR7_DB1 _CAN2TXDSR7.Bits.DB1
#define CAN2TXDSR7_DB2 _CAN2TXDSR7.Bits.DB2
#define CAN2TXDSR7_DB3 _CAN2TXDSR7.Bits.DB3
#define CAN2TXDSR7_DB4 _CAN2TXDSR7.Bits.DB4
#define CAN2TXDSR7_DB5 _CAN2TXDSR7.Bits.DB5
#define CAN2TXDSR7_DB6 _CAN2TXDSR7.Bits.DB6
#define CAN2TXDSR7_DB7 _CAN2TXDSR7.Bits.DB7
#define CAN2TXDSR7_DB _CAN2TXDSR7.MergedBits.grpDB


/*** CAN2TXDLR - MSCAN 2 Transmit Data Length Register; 0x000001FC ***/
typedef union {
  byte Byte;
  struct {
    byte DLC0        :1;                                       /* Data Length Code Bit 0 */
    byte DLC1        :1;                                       /* Data Length Code Bit 1 */
    byte DLC2        :1;                                       /* Data Length Code Bit 2 */
    byte DLC3        :1;                                       /* Data Length Code Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDLC  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN2TXDLRSTR;
extern volatile CAN2TXDLRSTR _CAN2TXDLR @(REG_BASE + 0x000001FC);
#define CAN2TXDLR _CAN2TXDLR.Byte
#define CAN2TXDLR_DLC0 _CAN2TXDLR.Bits.DLC0
#define CAN2TXDLR_DLC1 _CAN2TXDLR.Bits.DLC1
#define CAN2TXDLR_DLC2 _CAN2TXDLR.Bits.DLC2
#define CAN2TXDLR_DLC3 _CAN2TXDLR.Bits.DLC3
#define CAN2TXDLR_DLC _CAN2TXDLR.MergedBits.grpDLC


/*** CAN2TXTBPR - MSCAN 2 Transmit Buffer Priority; 0x000001FF ***/
typedef union {
  byte Byte;
  struct {
    byte PRIO0       :1;                                       /* Transmit Buffer Priority Bit 0 */
    byte PRIO1       :1;                                       /* Transmit Buffer Priority Bit 1 */
    byte PRIO2       :1;                                       /* Transmit Buffer Priority Bit 2 */
    byte PRIO3       :1;                                       /* Transmit Buffer Priority Bit 3 */
    byte PRIO4       :1;                                       /* Transmit Buffer Priority Bit 4 */
    byte PRIO5       :1;                                       /* Transmit Buffer Priority Bit 5 */
    byte PRIO6       :1;                                       /* Transmit Buffer Priority Bit 6 */
    byte PRIO7       :1;                                       /* Transmit Buffer Priority Bit 7 */
  } Bits;
  struct {
    byte grpPRIO :8;
  } MergedBits;
} CAN2TXTBPRSTR;
extern volatile CAN2TXTBPRSTR _CAN2TXTBPR @(REG_BASE + 0x000001FF);
#define CAN2TXTBPR _CAN2TXTBPR.Byte
#define CAN2TXTBPR_PRIO0 _CAN2TXTBPR.Bits.PRIO0
#define CAN2TXTBPR_PRIO1 _CAN2TXTBPR.Bits.PRIO1
#define CAN2TXTBPR_PRIO2 _CAN2TXTBPR.Bits.PRIO2
#define CAN2TXTBPR_PRIO3 _CAN2TXTBPR.Bits.PRIO3
#define CAN2TXTBPR_PRIO4 _CAN2TXTBPR.Bits.PRIO4
#define CAN2TXTBPR_PRIO5 _CAN2TXTBPR.Bits.PRIO5
#define CAN2TXTBPR_PRIO6 _CAN2TXTBPR.Bits.PRIO6
#define CAN2TXTBPR_PRIO7 _CAN2TXTBPR.Bits.PRIO7
#define CAN2TXTBPR_PRIO _CAN2TXTBPR.MergedBits.grpPRIO


/*** CAN3CTL0 - MSCAN 3 Control 0 Register; 0x00000200 ***/
typedef union {
  byte Byte;
  struct {
    byte INITRQ      :1;                                       /* Initialization Mode Request */
    byte SLPRQ       :1;                                       /* Sleep Mode Request */
    byte WUPE        :1;                                       /* Wake-Up Enable */
    byte TIME        :1;                                       /* Timer Enable */
    byte SYNCH       :1;                                       /* Synchronized Status */
    byte CSWAI       :1;                                       /* CAN Stops in Wait Mode */
    byte RXACT       :1;                                       /* Receiver Active Status */
    byte RXFRM       :1;                                       /* Received Frame Flag */
  } Bits;
} CAN3CTL0STR;
extern volatile CAN3CTL0STR _CAN3CTL0 @(REG_BASE + 0x00000200);
#define CAN3CTL0 _CAN3CTL0.Byte
#define CAN3CTL0_INITRQ _CAN3CTL0.Bits.INITRQ
#define CAN3CTL0_SLPRQ _CAN3CTL0.Bits.SLPRQ
#define CAN3CTL0_WUPE _CAN3CTL0.Bits.WUPE
#define CAN3CTL0_TIME _CAN3CTL0.Bits.TIME
#define CAN3CTL0_SYNCH _CAN3CTL0.Bits.SYNCH
#define CAN3CTL0_CSWAI _CAN3CTL0.Bits.CSWAI
#define CAN3CTL0_RXACT _CAN3CTL0.Bits.RXACT
#define CAN3CTL0_RXFRM _CAN3CTL0.Bits.RXFRM


/*** CAN3CTL1 - MSCAN 3 Control 1 Register; 0x00000201 ***/
typedef union {
  byte Byte;
  struct {
    byte INITAK      :1;                                       /* Initialization Mode Acknowledge */
    byte SLPAK       :1;                                       /* Sleep Mode Acknowledge */
    byte WUPM        :1;                                       /* Wake-Up Mode */
    byte             :1; 
    byte LISTEN      :1;                                       /* Listen Only Mode */
    byte LOOPB       :1;                                       /* Loop Back Self Test Mode */
    byte CLKSRC      :1;                                       /* MSCAN 3 Clock Source */
    byte CANE        :1;                                       /* MSCAN 3 Enable */
  } Bits;
} CAN3CTL1STR;
extern volatile CAN3CTL1STR _CAN3CTL1 @(REG_BASE + 0x00000201);
#define CAN3CTL1 _CAN3CTL1.Byte
#define CAN3CTL1_INITAK _CAN3CTL1.Bits.INITAK
#define CAN3CTL1_SLPAK _CAN3CTL1.Bits.SLPAK
#define CAN3CTL1_WUPM _CAN3CTL1.Bits.WUPM
#define CAN3CTL1_LISTEN _CAN3CTL1.Bits.LISTEN
#define CAN3CTL1_LOOPB _CAN3CTL1.Bits.LOOPB
#define CAN3CTL1_CLKSRC _CAN3CTL1.Bits.CLKSRC
#define CAN3CTL1_CANE _CAN3CTL1.Bits.CANE


/*** CAN3BTR0 - MSCAN 3 Bus Timing Register 0; 0x00000202 ***/
typedef union {
  byte Byte;
  struct {
    byte BRP0        :1;                                       /* Baud Rate Prescaler 0 */
    byte BRP1        :1;                                       /* Baud Rate Prescaler 1 */
    byte BRP2        :1;                                       /* Baud Rate Prescaler 2 */
    byte BRP3        :1;                                       /* Baud Rate Prescaler 3 */
    byte BRP4        :1;                                       /* Baud Rate Prescaler 4 */
    byte BRP5        :1;                                       /* Baud Rate Prescaler 5 */
    byte SJW0        :1;                                       /* Synchronization Jump Width 0 */
    byte SJW1        :1;                                       /* Synchronization Jump Width 1 */
  } Bits;
  struct {
    byte grpBRP  :6;
    byte grpSJW  :2;
  } MergedBits;
} CAN3BTR0STR;
extern volatile CAN3BTR0STR _CAN3BTR0 @(REG_BASE + 0x00000202);
#define CAN3BTR0 _CAN3BTR0.Byte
#define CAN3BTR0_BRP0 _CAN3BTR0.Bits.BRP0
#define CAN3BTR0_BRP1 _CAN3BTR0.Bits.BRP1
#define CAN3BTR0_BRP2 _CAN3BTR0.Bits.BRP2
#define CAN3BTR0_BRP3 _CAN3BTR0.Bits.BRP3
#define CAN3BTR0_BRP4 _CAN3BTR0.Bits.BRP4
#define CAN3BTR0_BRP5 _CAN3BTR0.Bits.BRP5
#define CAN3BTR0_SJW0 _CAN3BTR0.Bits.SJW0
#define CAN3BTR0_SJW1 _CAN3BTR0.Bits.SJW1
#define CAN3BTR0_BRP _CAN3BTR0.MergedBits.grpBRP
#define CAN3BTR0_SJW _CAN3BTR0.MergedBits.grpSJW


/*** CAN3BTR1 - MSCAN 3 Bus Timing Register 1; 0x00000203 ***/
typedef union {
  byte Byte;
  struct {
    byte TSEG10      :1;                                       /* Time Segment 1 */
    byte TSEG11      :1;                                       /* Time Segment 1 */
    byte TSEG12      :1;                                       /* Time Segment 1 */
    byte TSEG13      :1;                                       /* Time Segment 1 */
    byte TSEG20      :1;                                       /* Time Segment 2 */
    byte TSEG21      :1;                                       /* Time Segment 2 */
    byte TSEG22      :1;                                       /* Time Segment 2 */
    byte SAMP        :1;                                       /* Sampling */
  } Bits;
  struct {
    byte grpTSEG_10 :4;
    byte grpTSEG_20 :3;
    byte         :1;
  } MergedBits;
} CAN3BTR1STR;
extern volatile CAN3BTR1STR _CAN3BTR1 @(REG_BASE + 0x00000203);
#define CAN3BTR1 _CAN3BTR1.Byte
#define CAN3BTR1_TSEG10 _CAN3BTR1.Bits.TSEG10
#define CAN3BTR1_TSEG11 _CAN3BTR1.Bits.TSEG11
#define CAN3BTR1_TSEG12 _CAN3BTR1.Bits.TSEG12
#define CAN3BTR1_TSEG13 _CAN3BTR1.Bits.TSEG13
#define CAN3BTR1_TSEG20 _CAN3BTR1.Bits.TSEG20
#define CAN3BTR1_TSEG21 _CAN3BTR1.Bits.TSEG21
#define CAN3BTR1_TSEG22 _CAN3BTR1.Bits.TSEG22
#define CAN3BTR1_SAMP _CAN3BTR1.Bits.SAMP
#define CAN3BTR1_TSEG_10 _CAN3BTR1.MergedBits.grpTSEG_10
#define CAN3BTR1_TSEG_20 _CAN3BTR1.MergedBits.grpTSEG_20
#define CAN3BTR1_TSEG CAN3BTR1_TSEG_10


/*** CAN3RFLG - MSCAN 3 Receiver Flag Register; 0x00000204 ***/
typedef union {
  byte Byte;
  struct {
    byte RXF         :1;                                       /* Receive Buffer Full */
    byte OVRIF       :1;                                       /* Overrun Interrupt Flag */
    byte TSTAT0      :1;                                       /* Transmitter Status Bit 0 */
    byte TSTAT1      :1;                                       /* Transmitter Status Bit 1 */
    byte RSTAT0      :1;                                       /* Receiver Status Bit 0 */
    byte RSTAT1      :1;                                       /* Receiver Status Bit 1 */
    byte CSCIF       :1;                                       /* CAN Status Change Interrupt Flag */
    byte WUPIF       :1;                                       /* Wake-up Interrupt Flag */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpTSTAT :2;
    byte grpRSTAT :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN3RFLGSTR;
extern volatile CAN3RFLGSTR _CAN3RFLG @(REG_BASE + 0x00000204);
#define CAN3RFLG _CAN3RFLG.Byte
#define CAN3RFLG_RXF _CAN3RFLG.Bits.RXF
#define CAN3RFLG_OVRIF _CAN3RFLG.Bits.OVRIF
#define CAN3RFLG_TSTAT0 _CAN3RFLG.Bits.TSTAT0
#define CAN3RFLG_TSTAT1 _CAN3RFLG.Bits.TSTAT1
#define CAN3RFLG_RSTAT0 _CAN3RFLG.Bits.RSTAT0
#define CAN3RFLG_RSTAT1 _CAN3RFLG.Bits.RSTAT1
#define CAN3RFLG_CSCIF _CAN3RFLG.Bits.CSCIF
#define CAN3RFLG_WUPIF _CAN3RFLG.Bits.WUPIF
#define CAN3RFLG_TSTAT _CAN3RFLG.MergedBits.grpTSTAT
#define CAN3RFLG_RSTAT _CAN3RFLG.MergedBits.grpRSTAT


/*** CAN3RIER - MSCAN 3 Receiver Interrupt Enable Register; 0x00000205 ***/
typedef union {
  byte Byte;
  struct {
    byte RXFIE       :1;                                       /* Receiver Full Interrupt Enable */
    byte OVRIE       :1;                                       /* Overrun Interrupt Enable */
    byte TSTATE0     :1;                                       /* Transmitter Status Change Enable 0 */
    byte TSTATE1     :1;                                       /* Transmitter Status Change Enable 1 */
    byte RSTATE0     :1;                                       /* Receiver Status Change Enable 0 */
    byte RSTATE1     :1;                                       /* Receiver Status Change Enable 1 */
    byte CSCIE       :1;                                       /* CAN Status Change Interrupt Enable */
    byte WUPIE       :1;                                       /* Wake-up Interrupt Enable */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpTSTATE :2;
    byte grpRSTATE :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN3RIERSTR;
extern volatile CAN3RIERSTR _CAN3RIER @(REG_BASE + 0x00000205);
#define CAN3RIER _CAN3RIER.Byte
#define CAN3RIER_RXFIE _CAN3RIER.Bits.RXFIE
#define CAN3RIER_OVRIE _CAN3RIER.Bits.OVRIE
#define CAN3RIER_TSTATE0 _CAN3RIER.Bits.TSTATE0
#define CAN3RIER_TSTATE1 _CAN3RIER.Bits.TSTATE1
#define CAN3RIER_RSTATE0 _CAN3RIER.Bits.RSTATE0
#define CAN3RIER_RSTATE1 _CAN3RIER.Bits.RSTATE1
#define CAN3RIER_CSCIE _CAN3RIER.Bits.CSCIE
#define CAN3RIER_WUPIE _CAN3RIER.Bits.WUPIE
#define CAN3RIER_TSTATE _CAN3RIER.MergedBits.grpTSTATE
#define CAN3RIER_RSTATE _CAN3RIER.MergedBits.grpRSTATE


/*** CAN3TFLG - MSCAN 3 Transmitter Flag Register; 0x00000206 ***/
typedef union {
  byte Byte;
  struct {
    byte TXE0        :1;                                       /* Transmitter Buffer Empty 0 */
    byte TXE1        :1;                                       /* Transmitter Buffer Empty 1 */
    byte TXE2        :1;                                       /* Transmitter Buffer Empty 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTXE  :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN3TFLGSTR;
extern volatile CAN3TFLGSTR _CAN3TFLG @(REG_BASE + 0x00000206);
#define CAN3TFLG _CAN3TFLG.Byte
#define CAN3TFLG_TXE0 _CAN3TFLG.Bits.TXE0
#define CAN3TFLG_TXE1 _CAN3TFLG.Bits.TXE1
#define CAN3TFLG_TXE2 _CAN3TFLG.Bits.TXE2
#define CAN3TFLG_TXE _CAN3TFLG.MergedBits.grpTXE


/*** CAN3TIER - MSCAN 3 Transmitter Interrupt Enable Register; 0x00000207 ***/
typedef union {
  byte Byte;
  struct {
    byte TXEIE0      :1;                                       /* Transmitter Empty Interrupt Enable 0 */
    byte TXEIE1      :1;                                       /* Transmitter Empty Interrupt Enable 1 */
    byte TXEIE2      :1;                                       /* Transmitter Empty Interrupt Enable 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTXEIE :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN3TIERSTR;
extern volatile CAN3TIERSTR _CAN3TIER @(REG_BASE + 0x00000207);
#define CAN3TIER _CAN3TIER.Byte
#define CAN3TIER_TXEIE0 _CAN3TIER.Bits.TXEIE0
#define CAN3TIER_TXEIE1 _CAN3TIER.Bits.TXEIE1
#define CAN3TIER_TXEIE2 _CAN3TIER.Bits.TXEIE2
#define CAN3TIER_TXEIE _CAN3TIER.MergedBits.grpTXEIE


/*** CAN3TARQ - MSCAN 3 Transmitter Message Abort Request; 0x00000208 ***/
typedef union {
  byte Byte;
  struct {
    byte ABTRQ0      :1;                                       /* Abort Request 0 */
    byte ABTRQ1      :1;                                       /* Abort Request 1 */
    byte ABTRQ2      :1;                                       /* Abort Request 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpABTRQ :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN3TARQSTR;
extern volatile CAN3TARQSTR _CAN3TARQ @(REG_BASE + 0x00000208);
#define CAN3TARQ _CAN3TARQ.Byte
#define CAN3TARQ_ABTRQ0 _CAN3TARQ.Bits.ABTRQ0
#define CAN3TARQ_ABTRQ1 _CAN3TARQ.Bits.ABTRQ1
#define CAN3TARQ_ABTRQ2 _CAN3TARQ.Bits.ABTRQ2
#define CAN3TARQ_ABTRQ _CAN3TARQ.MergedBits.grpABTRQ


/*** CAN3TAAK - MSCAN 3 Transmitter Message Abort Control; 0x00000209 ***/
typedef union {
  byte Byte;
  struct {
    byte ABTAK0      :1;                                       /* Abort Acknowledge 0 */
    byte ABTAK1      :1;                                       /* Abort Acknowledge 1 */
    byte ABTAK2      :1;                                       /* Abort Acknowledge 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpABTAK :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN3TAAKSTR;
extern volatile CAN3TAAKSTR _CAN3TAAK @(REG_BASE + 0x00000209);
#define CAN3TAAK _CAN3TAAK.Byte
#define CAN3TAAK_ABTAK0 _CAN3TAAK.Bits.ABTAK0
#define CAN3TAAK_ABTAK1 _CAN3TAAK.Bits.ABTAK1
#define CAN3TAAK_ABTAK2 _CAN3TAAK.Bits.ABTAK2
#define CAN3TAAK_ABTAK _CAN3TAAK.MergedBits.grpABTAK


/*** CAN3TBSEL - MSCAN 3 Transmit Buffer Selection; 0x0000020A ***/
typedef union {
  byte Byte;
  struct {
    byte TX0         :1;                                       /* Transmit Buffer Select 0 */
    byte TX1         :1;                                       /* Transmit Buffer Select 1 */
    byte TX2         :1;                                       /* Transmit Buffer Select 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTX   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN3TBSELSTR;
extern volatile CAN3TBSELSTR _CAN3TBSEL @(REG_BASE + 0x0000020A);
#define CAN3TBSEL _CAN3TBSEL.Byte
#define CAN3TBSEL_TX0 _CAN3TBSEL.Bits.TX0
#define CAN3TBSEL_TX1 _CAN3TBSEL.Bits.TX1
#define CAN3TBSEL_TX2 _CAN3TBSEL.Bits.TX2
#define CAN3TBSEL_TX _CAN3TBSEL.MergedBits.grpTX


/*** CAN3IDAC - MSCAN 3 Identifier Acceptance Control Register; 0x0000020B ***/
typedef union {
  byte Byte;
  struct {
    byte IDHIT0      :1;                                       /* Identifier Acceptance Hit Indicator 0 */
    byte IDHIT1      :1;                                       /* Identifier Acceptance Hit Indicator 1 */
    byte IDHIT2      :1;                                       /* Identifier Acceptance Hit Indicator 2 */
    byte             :1; 
    byte IDAM0       :1;                                       /* Identifier Acceptance Mode 0 */
    byte IDAM1       :1;                                       /* Identifier Acceptance Mode 1 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpIDHIT :3;
    byte         :1;
    byte grpIDAM :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN3IDACSTR;
extern volatile CAN3IDACSTR _CAN3IDAC @(REG_BASE + 0x0000020B);
#define CAN3IDAC _CAN3IDAC.Byte
#define CAN3IDAC_IDHIT0 _CAN3IDAC.Bits.IDHIT0
#define CAN3IDAC_IDHIT1 _CAN3IDAC.Bits.IDHIT1
#define CAN3IDAC_IDHIT2 _CAN3IDAC.Bits.IDHIT2
#define CAN3IDAC_IDAM0 _CAN3IDAC.Bits.IDAM0
#define CAN3IDAC_IDAM1 _CAN3IDAC.Bits.IDAM1
#define CAN3IDAC_IDHIT _CAN3IDAC.MergedBits.grpIDHIT
#define CAN3IDAC_IDAM _CAN3IDAC.MergedBits.grpIDAM


/*** CAN3RXERR - MSCAN 3 Receive Error Counter Register; 0x0000020E ***/
typedef union {
  byte Byte;
  struct {
    byte RXERR0      :1;                                       /* Bit 0 */
    byte RXERR1      :1;                                       /* Bit 1 */
    byte RXERR2      :1;                                       /* Bit 2 */
    byte RXERR3      :1;                                       /* Bit 3 */
    byte RXERR4      :1;                                       /* Bit 4 */
    byte RXERR5      :1;                                       /* Bit 5 */
    byte RXERR6      :1;                                       /* Bit 6 */
    byte RXERR7      :1;                                       /* Bit 7 */
  } Bits;
  struct {
    byte grpRXERR :8;
  } MergedBits;
} CAN3RXERRSTR;
extern volatile CAN3RXERRSTR _CAN3RXERR @(REG_BASE + 0x0000020E);
#define CAN3RXERR _CAN3RXERR.Byte
#define CAN3RXERR_RXERR0 _CAN3RXERR.Bits.RXERR0
#define CAN3RXERR_RXERR1 _CAN3RXERR.Bits.RXERR1
#define CAN3RXERR_RXERR2 _CAN3RXERR.Bits.RXERR2
#define CAN3RXERR_RXERR3 _CAN3RXERR.Bits.RXERR3
#define CAN3RXERR_RXERR4 _CAN3RXERR.Bits.RXERR4
#define CAN3RXERR_RXERR5 _CAN3RXERR.Bits.RXERR5
#define CAN3RXERR_RXERR6 _CAN3RXERR.Bits.RXERR6
#define CAN3RXERR_RXERR7 _CAN3RXERR.Bits.RXERR7
#define CAN3RXERR_RXERR _CAN3RXERR.MergedBits.grpRXERR


/*** CAN3TXERR - MSCAN 3 Transmit Error Counter Register; 0x0000020F ***/
typedef union {
  byte Byte;
  struct {
    byte TXERR0      :1;                                       /* Bit 0 */
    byte TXERR1      :1;                                       /* Bit 1 */
    byte TXERR2      :1;                                       /* Bit 2 */
    byte TXERR3      :1;                                       /* Bit 3 */
    byte TXERR4      :1;                                       /* Bit 4 */
    byte TXERR5      :1;                                       /* Bit 5 */
    byte TXERR6      :1;                                       /* Bit 6 */
    byte TXERR7      :1;                                       /* Bit 7 */
  } Bits;
  struct {
    byte grpTXERR :8;
  } MergedBits;
} CAN3TXERRSTR;
extern volatile CAN3TXERRSTR _CAN3TXERR @(REG_BASE + 0x0000020F);
#define CAN3TXERR _CAN3TXERR.Byte
#define CAN3TXERR_TXERR0 _CAN3TXERR.Bits.TXERR0
#define CAN3TXERR_TXERR1 _CAN3TXERR.Bits.TXERR1
#define CAN3TXERR_TXERR2 _CAN3TXERR.Bits.TXERR2
#define CAN3TXERR_TXERR3 _CAN3TXERR.Bits.TXERR3
#define CAN3TXERR_TXERR4 _CAN3TXERR.Bits.TXERR4
#define CAN3TXERR_TXERR5 _CAN3TXERR.Bits.TXERR5
#define CAN3TXERR_TXERR6 _CAN3TXERR.Bits.TXERR6
#define CAN3TXERR_TXERR7 _CAN3TXERR.Bits.TXERR7
#define CAN3TXERR_TXERR _CAN3TXERR.MergedBits.grpTXERR


/*** CAN3IDAR0 - MSCAN 3 Identifier Acceptance Register 0; 0x00000210 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN3IDAR0STR;
extern volatile CAN3IDAR0STR _CAN3IDAR0 @(REG_BASE + 0x00000210);
#define CAN3IDAR0 _CAN3IDAR0.Byte
#define CAN3IDAR0_AC0 _CAN3IDAR0.Bits.AC0
#define CAN3IDAR0_AC1 _CAN3IDAR0.Bits.AC1
#define CAN3IDAR0_AC2 _CAN3IDAR0.Bits.AC2
#define CAN3IDAR0_AC3 _CAN3IDAR0.Bits.AC3
#define CAN3IDAR0_AC4 _CAN3IDAR0.Bits.AC4
#define CAN3IDAR0_AC5 _CAN3IDAR0.Bits.AC5
#define CAN3IDAR0_AC6 _CAN3IDAR0.Bits.AC6
#define CAN3IDAR0_AC7 _CAN3IDAR0.Bits.AC7
#define CAN3IDAR0_AC _CAN3IDAR0.MergedBits.grpAC


/*** CAN3IDAR1 - MSCAN 3 Identifier Acceptance Register 1; 0x00000211 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN3IDAR1STR;
extern volatile CAN3IDAR1STR _CAN3IDAR1 @(REG_BASE + 0x00000211);
#define CAN3IDAR1 _CAN3IDAR1.Byte
#define CAN3IDAR1_AC0 _CAN3IDAR1.Bits.AC0
#define CAN3IDAR1_AC1 _CAN3IDAR1.Bits.AC1
#define CAN3IDAR1_AC2 _CAN3IDAR1.Bits.AC2
#define CAN3IDAR1_AC3 _CAN3IDAR1.Bits.AC3
#define CAN3IDAR1_AC4 _CAN3IDAR1.Bits.AC4
#define CAN3IDAR1_AC5 _CAN3IDAR1.Bits.AC5
#define CAN3IDAR1_AC6 _CAN3IDAR1.Bits.AC6
#define CAN3IDAR1_AC7 _CAN3IDAR1.Bits.AC7
#define CAN3IDAR1_AC _CAN3IDAR1.MergedBits.grpAC


/*** CAN3IDAR2 - MSCAN 3 Identifier Acceptance Register 2; 0x00000212 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN3IDAR2STR;
extern volatile CAN3IDAR2STR _CAN3IDAR2 @(REG_BASE + 0x00000212);
#define CAN3IDAR2 _CAN3IDAR2.Byte
#define CAN3IDAR2_AC0 _CAN3IDAR2.Bits.AC0
#define CAN3IDAR2_AC1 _CAN3IDAR2.Bits.AC1
#define CAN3IDAR2_AC2 _CAN3IDAR2.Bits.AC2
#define CAN3IDAR2_AC3 _CAN3IDAR2.Bits.AC3
#define CAN3IDAR2_AC4 _CAN3IDAR2.Bits.AC4
#define CAN3IDAR2_AC5 _CAN3IDAR2.Bits.AC5
#define CAN3IDAR2_AC6 _CAN3IDAR2.Bits.AC6
#define CAN3IDAR2_AC7 _CAN3IDAR2.Bits.AC7
#define CAN3IDAR2_AC _CAN3IDAR2.MergedBits.grpAC


/*** CAN3IDAR3 - MSCAN 3 Identifier Acceptance Register 3; 0x00000213 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN3IDAR3STR;
extern volatile CAN3IDAR3STR _CAN3IDAR3 @(REG_BASE + 0x00000213);
#define CAN3IDAR3 _CAN3IDAR3.Byte
#define CAN3IDAR3_AC0 _CAN3IDAR3.Bits.AC0
#define CAN3IDAR3_AC1 _CAN3IDAR3.Bits.AC1
#define CAN3IDAR3_AC2 _CAN3IDAR3.Bits.AC2
#define CAN3IDAR3_AC3 _CAN3IDAR3.Bits.AC3
#define CAN3IDAR3_AC4 _CAN3IDAR3.Bits.AC4
#define CAN3IDAR3_AC5 _CAN3IDAR3.Bits.AC5
#define CAN3IDAR3_AC6 _CAN3IDAR3.Bits.AC6
#define CAN3IDAR3_AC7 _CAN3IDAR3.Bits.AC7
#define CAN3IDAR3_AC _CAN3IDAR3.MergedBits.grpAC


/*** CAN3IDMR0 - MSCAN 3 Identifier Mask Register 0; 0x00000214 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN3IDMR0STR;
extern volatile CAN3IDMR0STR _CAN3IDMR0 @(REG_BASE + 0x00000214);
#define CAN3IDMR0 _CAN3IDMR0.Byte
#define CAN3IDMR0_AM0 _CAN3IDMR0.Bits.AM0
#define CAN3IDMR0_AM1 _CAN3IDMR0.Bits.AM1
#define CAN3IDMR0_AM2 _CAN3IDMR0.Bits.AM2
#define CAN3IDMR0_AM3 _CAN3IDMR0.Bits.AM3
#define CAN3IDMR0_AM4 _CAN3IDMR0.Bits.AM4
#define CAN3IDMR0_AM5 _CAN3IDMR0.Bits.AM5
#define CAN3IDMR0_AM6 _CAN3IDMR0.Bits.AM6
#define CAN3IDMR0_AM7 _CAN3IDMR0.Bits.AM7
#define CAN3IDMR0_AM _CAN3IDMR0.MergedBits.grpAM


/*** CAN3IDMR1 - MSCAN 3 Identifier Mask Register 1; 0x00000215 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN3IDMR1STR;
extern volatile CAN3IDMR1STR _CAN3IDMR1 @(REG_BASE + 0x00000215);
#define CAN3IDMR1 _CAN3IDMR1.Byte
#define CAN3IDMR1_AM0 _CAN3IDMR1.Bits.AM0
#define CAN3IDMR1_AM1 _CAN3IDMR1.Bits.AM1
#define CAN3IDMR1_AM2 _CAN3IDMR1.Bits.AM2
#define CAN3IDMR1_AM3 _CAN3IDMR1.Bits.AM3
#define CAN3IDMR1_AM4 _CAN3IDMR1.Bits.AM4
#define CAN3IDMR1_AM5 _CAN3IDMR1.Bits.AM5
#define CAN3IDMR1_AM6 _CAN3IDMR1.Bits.AM6
#define CAN3IDMR1_AM7 _CAN3IDMR1.Bits.AM7
#define CAN3IDMR1_AM _CAN3IDMR1.MergedBits.grpAM


/*** CAN3IDMR2 - MSCAN 3 Identifier Mask Register 2; 0x00000216 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN3IDMR2STR;
extern volatile CAN3IDMR2STR _CAN3IDMR2 @(REG_BASE + 0x00000216);
#define CAN3IDMR2 _CAN3IDMR2.Byte
#define CAN3IDMR2_AM0 _CAN3IDMR2.Bits.AM0
#define CAN3IDMR2_AM1 _CAN3IDMR2.Bits.AM1
#define CAN3IDMR2_AM2 _CAN3IDMR2.Bits.AM2
#define CAN3IDMR2_AM3 _CAN3IDMR2.Bits.AM3
#define CAN3IDMR2_AM4 _CAN3IDMR2.Bits.AM4
#define CAN3IDMR2_AM5 _CAN3IDMR2.Bits.AM5
#define CAN3IDMR2_AM6 _CAN3IDMR2.Bits.AM6
#define CAN3IDMR2_AM7 _CAN3IDMR2.Bits.AM7
#define CAN3IDMR2_AM _CAN3IDMR2.MergedBits.grpAM


/*** CAN3IDMR3 - MSCAN 3 Identifier Mask Register 3; 0x00000217 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN3IDMR3STR;
extern volatile CAN3IDMR3STR _CAN3IDMR3 @(REG_BASE + 0x00000217);
#define CAN3IDMR3 _CAN3IDMR3.Byte
#define CAN3IDMR3_AM0 _CAN3IDMR3.Bits.AM0
#define CAN3IDMR3_AM1 _CAN3IDMR3.Bits.AM1
#define CAN3IDMR3_AM2 _CAN3IDMR3.Bits.AM2
#define CAN3IDMR3_AM3 _CAN3IDMR3.Bits.AM3
#define CAN3IDMR3_AM4 _CAN3IDMR3.Bits.AM4
#define CAN3IDMR3_AM5 _CAN3IDMR3.Bits.AM5
#define CAN3IDMR3_AM6 _CAN3IDMR3.Bits.AM6
#define CAN3IDMR3_AM7 _CAN3IDMR3.Bits.AM7
#define CAN3IDMR3_AM _CAN3IDMR3.MergedBits.grpAM


/*** CAN3IDAR4 - MSCAN 3 Identifier Acceptance Register 4; 0x00000218 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN3IDAR4STR;
extern volatile CAN3IDAR4STR _CAN3IDAR4 @(REG_BASE + 0x00000218);
#define CAN3IDAR4 _CAN3IDAR4.Byte
#define CAN3IDAR4_AC0 _CAN3IDAR4.Bits.AC0
#define CAN3IDAR4_AC1 _CAN3IDAR4.Bits.AC1
#define CAN3IDAR4_AC2 _CAN3IDAR4.Bits.AC2
#define CAN3IDAR4_AC3 _CAN3IDAR4.Bits.AC3
#define CAN3IDAR4_AC4 _CAN3IDAR4.Bits.AC4
#define CAN3IDAR4_AC5 _CAN3IDAR4.Bits.AC5
#define CAN3IDAR4_AC6 _CAN3IDAR4.Bits.AC6
#define CAN3IDAR4_AC7 _CAN3IDAR4.Bits.AC7
#define CAN3IDAR4_AC _CAN3IDAR4.MergedBits.grpAC


/*** CAN3IDAR5 - MSCAN 3 Identifier Acceptance Register 5; 0x00000219 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN3IDAR5STR;
extern volatile CAN3IDAR5STR _CAN3IDAR5 @(REG_BASE + 0x00000219);
#define CAN3IDAR5 _CAN3IDAR5.Byte
#define CAN3IDAR5_AC0 _CAN3IDAR5.Bits.AC0
#define CAN3IDAR5_AC1 _CAN3IDAR5.Bits.AC1
#define CAN3IDAR5_AC2 _CAN3IDAR5.Bits.AC2
#define CAN3IDAR5_AC3 _CAN3IDAR5.Bits.AC3
#define CAN3IDAR5_AC4 _CAN3IDAR5.Bits.AC4
#define CAN3IDAR5_AC5 _CAN3IDAR5.Bits.AC5
#define CAN3IDAR5_AC6 _CAN3IDAR5.Bits.AC6
#define CAN3IDAR5_AC7 _CAN3IDAR5.Bits.AC7
#define CAN3IDAR5_AC _CAN3IDAR5.MergedBits.grpAC


/*** CAN3IDAR6 - MSCAN 3 Identifier Acceptance Register 6; 0x0000021A ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN3IDAR6STR;
extern volatile CAN3IDAR6STR _CAN3IDAR6 @(REG_BASE + 0x0000021A);
#define CAN3IDAR6 _CAN3IDAR6.Byte
#define CAN3IDAR6_AC0 _CAN3IDAR6.Bits.AC0
#define CAN3IDAR6_AC1 _CAN3IDAR6.Bits.AC1
#define CAN3IDAR6_AC2 _CAN3IDAR6.Bits.AC2
#define CAN3IDAR6_AC3 _CAN3IDAR6.Bits.AC3
#define CAN3IDAR6_AC4 _CAN3IDAR6.Bits.AC4
#define CAN3IDAR6_AC5 _CAN3IDAR6.Bits.AC5
#define CAN3IDAR6_AC6 _CAN3IDAR6.Bits.AC6
#define CAN3IDAR6_AC7 _CAN3IDAR6.Bits.AC7
#define CAN3IDAR6_AC _CAN3IDAR6.MergedBits.grpAC


/*** CAN3IDAR7 - MSCAN 3 Identifier Acceptance Register 7; 0x0000021B ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN3IDAR7STR;
extern volatile CAN3IDAR7STR _CAN3IDAR7 @(REG_BASE + 0x0000021B);
#define CAN3IDAR7 _CAN3IDAR7.Byte
#define CAN3IDAR7_AC0 _CAN3IDAR7.Bits.AC0
#define CAN3IDAR7_AC1 _CAN3IDAR7.Bits.AC1
#define CAN3IDAR7_AC2 _CAN3IDAR7.Bits.AC2
#define CAN3IDAR7_AC3 _CAN3IDAR7.Bits.AC3
#define CAN3IDAR7_AC4 _CAN3IDAR7.Bits.AC4
#define CAN3IDAR7_AC5 _CAN3IDAR7.Bits.AC5
#define CAN3IDAR7_AC6 _CAN3IDAR7.Bits.AC6
#define CAN3IDAR7_AC7 _CAN3IDAR7.Bits.AC7
#define CAN3IDAR7_AC _CAN3IDAR7.MergedBits.grpAC


/*** CAN3IDMR4 - MSCAN 3 Identifier Mask Register 4; 0x0000021C ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN3IDMR4STR;
extern volatile CAN3IDMR4STR _CAN3IDMR4 @(REG_BASE + 0x0000021C);
#define CAN3IDMR4 _CAN3IDMR4.Byte
#define CAN3IDMR4_AM0 _CAN3IDMR4.Bits.AM0
#define CAN3IDMR4_AM1 _CAN3IDMR4.Bits.AM1
#define CAN3IDMR4_AM2 _CAN3IDMR4.Bits.AM2
#define CAN3IDMR4_AM3 _CAN3IDMR4.Bits.AM3
#define CAN3IDMR4_AM4 _CAN3IDMR4.Bits.AM4
#define CAN3IDMR4_AM5 _CAN3IDMR4.Bits.AM5
#define CAN3IDMR4_AM6 _CAN3IDMR4.Bits.AM6
#define CAN3IDMR4_AM7 _CAN3IDMR4.Bits.AM7
#define CAN3IDMR4_AM _CAN3IDMR4.MergedBits.grpAM


/*** CAN3IDMR5 - MSCAN 3 Identifier Mask Register 5; 0x0000021D ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN3IDMR5STR;
extern volatile CAN3IDMR5STR _CAN3IDMR5 @(REG_BASE + 0x0000021D);
#define CAN3IDMR5 _CAN3IDMR5.Byte
#define CAN3IDMR5_AM0 _CAN3IDMR5.Bits.AM0
#define CAN3IDMR5_AM1 _CAN3IDMR5.Bits.AM1
#define CAN3IDMR5_AM2 _CAN3IDMR5.Bits.AM2
#define CAN3IDMR5_AM3 _CAN3IDMR5.Bits.AM3
#define CAN3IDMR5_AM4 _CAN3IDMR5.Bits.AM4
#define CAN3IDMR5_AM5 _CAN3IDMR5.Bits.AM5
#define CAN3IDMR5_AM6 _CAN3IDMR5.Bits.AM6
#define CAN3IDMR5_AM7 _CAN3IDMR5.Bits.AM7
#define CAN3IDMR5_AM _CAN3IDMR5.MergedBits.grpAM


/*** CAN3IDMR6 - MSCAN 3 Identifier Mask Register 6; 0x0000021E ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN3IDMR6STR;
extern volatile CAN3IDMR6STR _CAN3IDMR6 @(REG_BASE + 0x0000021E);
#define CAN3IDMR6 _CAN3IDMR6.Byte
#define CAN3IDMR6_AM0 _CAN3IDMR6.Bits.AM0
#define CAN3IDMR6_AM1 _CAN3IDMR6.Bits.AM1
#define CAN3IDMR6_AM2 _CAN3IDMR6.Bits.AM2
#define CAN3IDMR6_AM3 _CAN3IDMR6.Bits.AM3
#define CAN3IDMR6_AM4 _CAN3IDMR6.Bits.AM4
#define CAN3IDMR6_AM5 _CAN3IDMR6.Bits.AM5
#define CAN3IDMR6_AM6 _CAN3IDMR6.Bits.AM6
#define CAN3IDMR6_AM7 _CAN3IDMR6.Bits.AM7
#define CAN3IDMR6_AM _CAN3IDMR6.MergedBits.grpAM


/*** CAN3IDMR7 - MSCAN 3 Identifier Mask Register 7; 0x0000021F ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN3IDMR7STR;
extern volatile CAN3IDMR7STR _CAN3IDMR7 @(REG_BASE + 0x0000021F);
#define CAN3IDMR7 _CAN3IDMR7.Byte
#define CAN3IDMR7_AM0 _CAN3IDMR7.Bits.AM0
#define CAN3IDMR7_AM1 _CAN3IDMR7.Bits.AM1
#define CAN3IDMR7_AM2 _CAN3IDMR7.Bits.AM2
#define CAN3IDMR7_AM3 _CAN3IDMR7.Bits.AM3
#define CAN3IDMR7_AM4 _CAN3IDMR7.Bits.AM4
#define CAN3IDMR7_AM5 _CAN3IDMR7.Bits.AM5
#define CAN3IDMR7_AM6 _CAN3IDMR7.Bits.AM6
#define CAN3IDMR7_AM7 _CAN3IDMR7.Bits.AM7
#define CAN3IDMR7_AM _CAN3IDMR7.MergedBits.grpAM


/*** CAN3RXIDR0 - MSCAN 3 Receive Identifier Register 0; 0x00000220 ***/
typedef union {
  byte Byte;
  struct {
    byte ID21        :1;                                       /* Extended format identifier Bit 21 */
    byte ID22        :1;                                       /* Extended format identifier Bit 22 */
    byte ID23        :1;                                       /* Extended format identifier Bit 23 */
    byte ID24        :1;                                       /* Extended format identifier Bit 24 */
    byte ID25        :1;                                       /* Extended format identifier Bit 25 */
    byte ID26        :1;                                       /* Extended format identifier Bit 26 */
    byte ID27        :1;                                       /* Extended format identifier Bit 27 */
    byte ID28        :1;                                       /* Extended format identifier Bit 28 */
  } Bits;
  struct {
    byte grpID_21 :8;
  } MergedBits;
} CAN3RXIDR0STR;
extern volatile CAN3RXIDR0STR _CAN3RXIDR0 @(REG_BASE + 0x00000220);
#define CAN3RXIDR0 _CAN3RXIDR0.Byte
#define CAN3RXIDR0_ID21 _CAN3RXIDR0.Bits.ID21
#define CAN3RXIDR0_ID22 _CAN3RXIDR0.Bits.ID22
#define CAN3RXIDR0_ID23 _CAN3RXIDR0.Bits.ID23
#define CAN3RXIDR0_ID24 _CAN3RXIDR0.Bits.ID24
#define CAN3RXIDR0_ID25 _CAN3RXIDR0.Bits.ID25
#define CAN3RXIDR0_ID26 _CAN3RXIDR0.Bits.ID26
#define CAN3RXIDR0_ID27 _CAN3RXIDR0.Bits.ID27
#define CAN3RXIDR0_ID28 _CAN3RXIDR0.Bits.ID28
#define CAN3RXIDR0_ID_21 _CAN3RXIDR0.MergedBits.grpID_21
#define CAN3RXIDR0_ID CAN3RXIDR0_ID_21


/*** CAN3RXIDR1 - MSCAN 3 Receive Identifier Register 1; 0x00000221 ***/
typedef union {
  byte Byte;
  struct {
    byte ID15        :1;                                       /* Extended format identifier Bit 15 */
    byte ID16        :1;                                       /* Extended format identifier Bit 16 */
    byte ID17        :1;                                       /* Extended format identifier Bit 17 */
    byte IDE         :1;                                       /* ID Extended */
    byte SRR         :1;                                       /* Substitute Remote Request */
    byte ID18        :1;                                       /* Extended format identifier Bit 18 */
    byte ID19        :1;                                       /* Extended format identifier Bit 19 */
    byte ID20        :1;                                       /* Extended format identifier Bit 20 */
  } Bits;
  struct {
    byte grpID_15 :3;
    byte         :1;
    byte         :1;
    byte grpID_18 :3;
  } MergedBits;
} CAN3RXIDR1STR;
extern volatile CAN3RXIDR1STR _CAN3RXIDR1 @(REG_BASE + 0x00000221);
#define CAN3RXIDR1 _CAN3RXIDR1.Byte
#define CAN3RXIDR1_ID15 _CAN3RXIDR1.Bits.ID15
#define CAN3RXIDR1_ID16 _CAN3RXIDR1.Bits.ID16
#define CAN3RXIDR1_ID17 _CAN3RXIDR1.Bits.ID17
#define CAN3RXIDR1_IDE _CAN3RXIDR1.Bits.IDE
#define CAN3RXIDR1_SRR _CAN3RXIDR1.Bits.SRR
#define CAN3RXIDR1_ID18 _CAN3RXIDR1.Bits.ID18
#define CAN3RXIDR1_ID19 _CAN3RXIDR1.Bits.ID19
#define CAN3RXIDR1_ID20 _CAN3RXIDR1.Bits.ID20
#define CAN3RXIDR1_ID_15 _CAN3RXIDR1.MergedBits.grpID_15
#define CAN3RXIDR1_ID_18 _CAN3RXIDR1.MergedBits.grpID_18
#define CAN3RXIDR1_ID CAN3RXIDR1_ID_15


/*** CAN3RXIDR2 - MSCAN 3 Receive Identifier Register 2; 0x00000222 ***/
typedef union {
  byte Byte;
  struct {
    byte ID7         :1;                                       /* Extended format identifier Bit 7 */
    byte ID8         :1;                                       /* Extended format identifier Bit 8 */
    byte ID9         :1;                                       /* Extended format identifier Bit 9 */
    byte ID10        :1;                                       /* Extended format identifier Bit 10 */
    byte ID11        :1;                                       /* Extended format identifier Bit 11 */
    byte ID12        :1;                                       /* Extended format identifier Bit 12 */
    byte ID13        :1;                                       /* Extended format identifier Bit 13 */
    byte ID14        :1;                                       /* Extended format identifier Bit 14 */
  } Bits;
  struct {
    byte grpID_7 :8;
  } MergedBits;
} CAN3RXIDR2STR;
extern volatile CAN3RXIDR2STR _CAN3RXIDR2 @(REG_BASE + 0x00000222);
#define CAN3RXIDR2 _CAN3RXIDR2.Byte
#define CAN3RXIDR2_ID7 _CAN3RXIDR2.Bits.ID7
#define CAN3RXIDR2_ID8 _CAN3RXIDR2.Bits.ID8
#define CAN3RXIDR2_ID9 _CAN3RXIDR2.Bits.ID9
#define CAN3RXIDR2_ID10 _CAN3RXIDR2.Bits.ID10
#define CAN3RXIDR2_ID11 _CAN3RXIDR2.Bits.ID11
#define CAN3RXIDR2_ID12 _CAN3RXIDR2.Bits.ID12
#define CAN3RXIDR2_ID13 _CAN3RXIDR2.Bits.ID13
#define CAN3RXIDR2_ID14 _CAN3RXIDR2.Bits.ID14
#define CAN3RXIDR2_ID_7 _CAN3RXIDR2.MergedBits.grpID_7
#define CAN3RXIDR2_ID CAN3RXIDR2_ID_7


/*** CAN3RXIDR3 - MSCAN 3 Receive Identifier Register 3; 0x00000223 ***/
typedef union {
  byte Byte;
  struct {
    byte RTR         :1;                                       /* Remote Transmission Request */
    byte ID0         :1;                                       /* Extended format identifier Bit 0 */
    byte ID1         :1;                                       /* Extended format identifier Bit 1 */
    byte ID2         :1;                                       /* Extended format identifier Bit 2 */
    byte ID3         :1;                                       /* Extended format identifier Bit 3 */
    byte ID4         :1;                                       /* Extended format identifier Bit 4 */
    byte ID5         :1;                                       /* Extended format identifier Bit 5 */
    byte ID6         :1;                                       /* Extended format identifier Bit 6 */
  } Bits;
  struct {
    byte         :1;
    byte grpID   :7;
  } MergedBits;
} CAN3RXIDR3STR;
extern volatile CAN3RXIDR3STR _CAN3RXIDR3 @(REG_BASE + 0x00000223);
#define CAN3RXIDR3 _CAN3RXIDR3.Byte
#define CAN3RXIDR3_RTR _CAN3RXIDR3.Bits.RTR
#define CAN3RXIDR3_ID0 _CAN3RXIDR3.Bits.ID0
#define CAN3RXIDR3_ID1 _CAN3RXIDR3.Bits.ID1
#define CAN3RXIDR3_ID2 _CAN3RXIDR3.Bits.ID2
#define CAN3RXIDR3_ID3 _CAN3RXIDR3.Bits.ID3
#define CAN3RXIDR3_ID4 _CAN3RXIDR3.Bits.ID4
#define CAN3RXIDR3_ID5 _CAN3RXIDR3.Bits.ID5
#define CAN3RXIDR3_ID6 _CAN3RXIDR3.Bits.ID6
#define CAN3RXIDR3_ID _CAN3RXIDR3.MergedBits.grpID


/*** CAN3RXDSR0 - MSCAN 3 Receive Data Segment Register 0; 0x00000224 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3RXDSR0STR;
extern volatile CAN3RXDSR0STR _CAN3RXDSR0 @(REG_BASE + 0x00000224);
#define CAN3RXDSR0 _CAN3RXDSR0.Byte
#define CAN3RXDSR0_DB0 _CAN3RXDSR0.Bits.DB0
#define CAN3RXDSR0_DB1 _CAN3RXDSR0.Bits.DB1
#define CAN3RXDSR0_DB2 _CAN3RXDSR0.Bits.DB2
#define CAN3RXDSR0_DB3 _CAN3RXDSR0.Bits.DB3
#define CAN3RXDSR0_DB4 _CAN3RXDSR0.Bits.DB4
#define CAN3RXDSR0_DB5 _CAN3RXDSR0.Bits.DB5
#define CAN3RXDSR0_DB6 _CAN3RXDSR0.Bits.DB6
#define CAN3RXDSR0_DB7 _CAN3RXDSR0.Bits.DB7
#define CAN3RXDSR0_DB _CAN3RXDSR0.MergedBits.grpDB


/*** CAN3RXDSR1 - MSCAN 3 Receive Data Segment Register 1; 0x00000225 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3RXDSR1STR;
extern volatile CAN3RXDSR1STR _CAN3RXDSR1 @(REG_BASE + 0x00000225);
#define CAN3RXDSR1 _CAN3RXDSR1.Byte
#define CAN3RXDSR1_DB0 _CAN3RXDSR1.Bits.DB0
#define CAN3RXDSR1_DB1 _CAN3RXDSR1.Bits.DB1
#define CAN3RXDSR1_DB2 _CAN3RXDSR1.Bits.DB2
#define CAN3RXDSR1_DB3 _CAN3RXDSR1.Bits.DB3
#define CAN3RXDSR1_DB4 _CAN3RXDSR1.Bits.DB4
#define CAN3RXDSR1_DB5 _CAN3RXDSR1.Bits.DB5
#define CAN3RXDSR1_DB6 _CAN3RXDSR1.Bits.DB6
#define CAN3RXDSR1_DB7 _CAN3RXDSR1.Bits.DB7
#define CAN3RXDSR1_DB _CAN3RXDSR1.MergedBits.grpDB


/*** CAN3RXDSR2 - MSCAN 3 Receive Data Segment Register 2; 0x00000226 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3RXDSR2STR;
extern volatile CAN3RXDSR2STR _CAN3RXDSR2 @(REG_BASE + 0x00000226);
#define CAN3RXDSR2 _CAN3RXDSR2.Byte
#define CAN3RXDSR2_DB0 _CAN3RXDSR2.Bits.DB0
#define CAN3RXDSR2_DB1 _CAN3RXDSR2.Bits.DB1
#define CAN3RXDSR2_DB2 _CAN3RXDSR2.Bits.DB2
#define CAN3RXDSR2_DB3 _CAN3RXDSR2.Bits.DB3
#define CAN3RXDSR2_DB4 _CAN3RXDSR2.Bits.DB4
#define CAN3RXDSR2_DB5 _CAN3RXDSR2.Bits.DB5
#define CAN3RXDSR2_DB6 _CAN3RXDSR2.Bits.DB6
#define CAN3RXDSR2_DB7 _CAN3RXDSR2.Bits.DB7
#define CAN3RXDSR2_DB _CAN3RXDSR2.MergedBits.grpDB


/*** CAN3RXDSR3 - MSCAN 3 Receive Data Segment Register 3; 0x00000227 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3RXDSR3STR;
extern volatile CAN3RXDSR3STR _CAN3RXDSR3 @(REG_BASE + 0x00000227);
#define CAN3RXDSR3 _CAN3RXDSR3.Byte
#define CAN3RXDSR3_DB0 _CAN3RXDSR3.Bits.DB0
#define CAN3RXDSR3_DB1 _CAN3RXDSR3.Bits.DB1
#define CAN3RXDSR3_DB2 _CAN3RXDSR3.Bits.DB2
#define CAN3RXDSR3_DB3 _CAN3RXDSR3.Bits.DB3
#define CAN3RXDSR3_DB4 _CAN3RXDSR3.Bits.DB4
#define CAN3RXDSR3_DB5 _CAN3RXDSR3.Bits.DB5
#define CAN3RXDSR3_DB6 _CAN3RXDSR3.Bits.DB6
#define CAN3RXDSR3_DB7 _CAN3RXDSR3.Bits.DB7
#define CAN3RXDSR3_DB _CAN3RXDSR3.MergedBits.grpDB


/*** CAN3RXDSR4 - MSCAN 3 Receive Data Segment Register 4; 0x00000228 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3RXDSR4STR;
extern volatile CAN3RXDSR4STR _CAN3RXDSR4 @(REG_BASE + 0x00000228);
#define CAN3RXDSR4 _CAN3RXDSR4.Byte
#define CAN3RXDSR4_DB0 _CAN3RXDSR4.Bits.DB0
#define CAN3RXDSR4_DB1 _CAN3RXDSR4.Bits.DB1
#define CAN3RXDSR4_DB2 _CAN3RXDSR4.Bits.DB2
#define CAN3RXDSR4_DB3 _CAN3RXDSR4.Bits.DB3
#define CAN3RXDSR4_DB4 _CAN3RXDSR4.Bits.DB4
#define CAN3RXDSR4_DB5 _CAN3RXDSR4.Bits.DB5
#define CAN3RXDSR4_DB6 _CAN3RXDSR4.Bits.DB6
#define CAN3RXDSR4_DB7 _CAN3RXDSR4.Bits.DB7
#define CAN3RXDSR4_DB _CAN3RXDSR4.MergedBits.grpDB


/*** CAN3RXDSR5 - MSCAN 3 Receive Data Segment Register 5; 0x00000229 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3RXDSR5STR;
extern volatile CAN3RXDSR5STR _CAN3RXDSR5 @(REG_BASE + 0x00000229);
#define CAN3RXDSR5 _CAN3RXDSR5.Byte
#define CAN3RXDSR5_DB0 _CAN3RXDSR5.Bits.DB0
#define CAN3RXDSR5_DB1 _CAN3RXDSR5.Bits.DB1
#define CAN3RXDSR5_DB2 _CAN3RXDSR5.Bits.DB2
#define CAN3RXDSR5_DB3 _CAN3RXDSR5.Bits.DB3
#define CAN3RXDSR5_DB4 _CAN3RXDSR5.Bits.DB4
#define CAN3RXDSR5_DB5 _CAN3RXDSR5.Bits.DB5
#define CAN3RXDSR5_DB6 _CAN3RXDSR5.Bits.DB6
#define CAN3RXDSR5_DB7 _CAN3RXDSR5.Bits.DB7
#define CAN3RXDSR5_DB _CAN3RXDSR5.MergedBits.grpDB


/*** CAN3RXDSR6 - MSCAN 3 Receive Data Segment Register 6; 0x0000022A ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3RXDSR6STR;
extern volatile CAN3RXDSR6STR _CAN3RXDSR6 @(REG_BASE + 0x0000022A);
#define CAN3RXDSR6 _CAN3RXDSR6.Byte
#define CAN3RXDSR6_DB0 _CAN3RXDSR6.Bits.DB0
#define CAN3RXDSR6_DB1 _CAN3RXDSR6.Bits.DB1
#define CAN3RXDSR6_DB2 _CAN3RXDSR6.Bits.DB2
#define CAN3RXDSR6_DB3 _CAN3RXDSR6.Bits.DB3
#define CAN3RXDSR6_DB4 _CAN3RXDSR6.Bits.DB4
#define CAN3RXDSR6_DB5 _CAN3RXDSR6.Bits.DB5
#define CAN3RXDSR6_DB6 _CAN3RXDSR6.Bits.DB6
#define CAN3RXDSR6_DB7 _CAN3RXDSR6.Bits.DB7
#define CAN3RXDSR6_DB _CAN3RXDSR6.MergedBits.grpDB


/*** CAN3RXDSR7 - MSCAN 3 Receive Data Segment Register 7; 0x0000022B ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3RXDSR7STR;
extern volatile CAN3RXDSR7STR _CAN3RXDSR7 @(REG_BASE + 0x0000022B);
#define CAN3RXDSR7 _CAN3RXDSR7.Byte
#define CAN3RXDSR7_DB0 _CAN3RXDSR7.Bits.DB0
#define CAN3RXDSR7_DB1 _CAN3RXDSR7.Bits.DB1
#define CAN3RXDSR7_DB2 _CAN3RXDSR7.Bits.DB2
#define CAN3RXDSR7_DB3 _CAN3RXDSR7.Bits.DB3
#define CAN3RXDSR7_DB4 _CAN3RXDSR7.Bits.DB4
#define CAN3RXDSR7_DB5 _CAN3RXDSR7.Bits.DB5
#define CAN3RXDSR7_DB6 _CAN3RXDSR7.Bits.DB6
#define CAN3RXDSR7_DB7 _CAN3RXDSR7.Bits.DB7
#define CAN3RXDSR7_DB _CAN3RXDSR7.MergedBits.grpDB


/*** CAN3RXDLR - MSCAN 3 Receive Data Length Register; 0x0000022C ***/
typedef union {
  byte Byte;
  struct {
    byte DLC0        :1;                                       /* Data Length Code Bit 0 */
    byte DLC1        :1;                                       /* Data Length Code Bit 1 */
    byte DLC2        :1;                                       /* Data Length Code Bit 2 */
    byte DLC3        :1;                                       /* Data Length Code Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDLC  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN3RXDLRSTR;
extern volatile CAN3RXDLRSTR _CAN3RXDLR @(REG_BASE + 0x0000022C);
#define CAN3RXDLR _CAN3RXDLR.Byte
#define CAN3RXDLR_DLC0 _CAN3RXDLR.Bits.DLC0
#define CAN3RXDLR_DLC1 _CAN3RXDLR.Bits.DLC1
#define CAN3RXDLR_DLC2 _CAN3RXDLR.Bits.DLC2
#define CAN3RXDLR_DLC3 _CAN3RXDLR.Bits.DLC3
#define CAN3RXDLR_DLC _CAN3RXDLR.MergedBits.grpDLC


/*** CAN3TXIDR0 - MSCAN 3 Transmit Identifier Register 0; 0x00000230 ***/
typedef union {
  byte Byte;
  struct {
    byte ID21        :1;                                       /* Extended format identifier Bit 21 */
    byte ID22        :1;                                       /* Extended format identifier Bit 22 */
    byte ID23        :1;                                       /* Extended format identifier Bit 23 */
    byte ID24        :1;                                       /* Extended format identifier Bit 24 */
    byte ID25        :1;                                       /* Extended format identifier Bit 25 */
    byte ID26        :1;                                       /* Extended format identifier Bit 26 */
    byte ID27        :1;                                       /* Extended format identifier Bit 27 */
    byte ID28        :1;                                       /* Extended format identifier Bit 28 */
  } Bits;
  struct {
    byte grpID_21 :8;
  } MergedBits;
} CAN3TXIDR0STR;
extern volatile CAN3TXIDR0STR _CAN3TXIDR0 @(REG_BASE + 0x00000230);
#define CAN3TXIDR0 _CAN3TXIDR0.Byte
#define CAN3TXIDR0_ID21 _CAN3TXIDR0.Bits.ID21
#define CAN3TXIDR0_ID22 _CAN3TXIDR0.Bits.ID22
#define CAN3TXIDR0_ID23 _CAN3TXIDR0.Bits.ID23
#define CAN3TXIDR0_ID24 _CAN3TXIDR0.Bits.ID24
#define CAN3TXIDR0_ID25 _CAN3TXIDR0.Bits.ID25
#define CAN3TXIDR0_ID26 _CAN3TXIDR0.Bits.ID26
#define CAN3TXIDR0_ID27 _CAN3TXIDR0.Bits.ID27
#define CAN3TXIDR0_ID28 _CAN3TXIDR0.Bits.ID28
#define CAN3TXIDR0_ID_21 _CAN3TXIDR0.MergedBits.grpID_21
#define CAN3TXIDR0_ID CAN3TXIDR0_ID_21


/*** CAN3TXIDR1 - MSCAN 3 Transmit Identifier Register 1; 0x00000231 ***/
typedef union {
  byte Byte;
  struct {
    byte ID15        :1;                                       /* Extended format identifier Bit 15 */
    byte ID16        :1;                                       /* Extended format identifier Bit 16 */
    byte ID17        :1;                                       /* Extended format identifier Bit 17 */
    byte IDE         :1;                                       /* ID Extended */
    byte SRR         :1;                                       /* Substitute Remote Request */
    byte ID18        :1;                                       /* Extended format identifier Bit 18 */
    byte ID19        :1;                                       /* Extended format identifier Bit 19 */
    byte ID20        :1;                                       /* Extended format identifier Bit 20 */
  } Bits;
  struct {
    byte grpID_15 :3;
    byte         :1;
    byte         :1;
    byte grpID_18 :3;
  } MergedBits;
} CAN3TXIDR1STR;
extern volatile CAN3TXIDR1STR _CAN3TXIDR1 @(REG_BASE + 0x00000231);
#define CAN3TXIDR1 _CAN3TXIDR1.Byte
#define CAN3TXIDR1_ID15 _CAN3TXIDR1.Bits.ID15
#define CAN3TXIDR1_ID16 _CAN3TXIDR1.Bits.ID16
#define CAN3TXIDR1_ID17 _CAN3TXIDR1.Bits.ID17
#define CAN3TXIDR1_IDE _CAN3TXIDR1.Bits.IDE
#define CAN3TXIDR1_SRR _CAN3TXIDR1.Bits.SRR
#define CAN3TXIDR1_ID18 _CAN3TXIDR1.Bits.ID18
#define CAN3TXIDR1_ID19 _CAN3TXIDR1.Bits.ID19
#define CAN3TXIDR1_ID20 _CAN3TXIDR1.Bits.ID20
#define CAN3TXIDR1_ID_15 _CAN3TXIDR1.MergedBits.grpID_15
#define CAN3TXIDR1_ID_18 _CAN3TXIDR1.MergedBits.grpID_18
#define CAN3TXIDR1_ID CAN3TXIDR1_ID_15


/*** CAN3TXIDR2 - MSCAN 3 Transmit Identifier Register 2; 0x00000232 ***/
typedef union {
  byte Byte;
  struct {
    byte ID7         :1;                                       /* Extended format identifier Bit 7 */
    byte ID8         :1;                                       /* Extended format identifier Bit 8 */
    byte ID9         :1;                                       /* Extended format identifier Bit 9 */
    byte ID10        :1;                                       /* Extended format identifier Bit 10 */
    byte ID11        :1;                                       /* Extended format identifier Bit 11 */
    byte ID12        :1;                                       /* Extended format identifier Bit 12 */
    byte ID13        :1;                                       /* Extended format identifier Bit 13 */
    byte ID14        :1;                                       /* Extended format identifier Bit 14 */
  } Bits;
  struct {
    byte grpID_7 :8;
  } MergedBits;
} CAN3TXIDR2STR;
extern volatile CAN3TXIDR2STR _CAN3TXIDR2 @(REG_BASE + 0x00000232);
#define CAN3TXIDR2 _CAN3TXIDR2.Byte
#define CAN3TXIDR2_ID7 _CAN3TXIDR2.Bits.ID7
#define CAN3TXIDR2_ID8 _CAN3TXIDR2.Bits.ID8
#define CAN3TXIDR2_ID9 _CAN3TXIDR2.Bits.ID9
#define CAN3TXIDR2_ID10 _CAN3TXIDR2.Bits.ID10
#define CAN3TXIDR2_ID11 _CAN3TXIDR2.Bits.ID11
#define CAN3TXIDR2_ID12 _CAN3TXIDR2.Bits.ID12
#define CAN3TXIDR2_ID13 _CAN3TXIDR2.Bits.ID13
#define CAN3TXIDR2_ID14 _CAN3TXIDR2.Bits.ID14
#define CAN3TXIDR2_ID_7 _CAN3TXIDR2.MergedBits.grpID_7
#define CAN3TXIDR2_ID CAN3TXIDR2_ID_7


/*** CAN3TXIDR3 - MSCAN 3 Transmit Identifier Register 3; 0x00000233 ***/
typedef union {
  byte Byte;
  struct {
    byte RTR         :1;                                       /* Remote Transmission Request */
    byte ID0         :1;                                       /* Extended format identifier Bit 0 */
    byte ID1         :1;                                       /* Extended format identifier Bit 1 */
    byte ID2         :1;                                       /* Extended format identifier Bit 2 */
    byte ID3         :1;                                       /* Extended format identifier Bit 3 */
    byte ID4         :1;                                       /* Extended format identifier Bit 4 */
    byte ID5         :1;                                       /* Extended format identifier Bit 5 */
    byte ID6         :1;                                       /* Extended format identifier Bit 6 */
  } Bits;
  struct {
    byte         :1;
    byte grpID   :7;
  } MergedBits;
} CAN3TXIDR3STR;
extern volatile CAN3TXIDR3STR _CAN3TXIDR3 @(REG_BASE + 0x00000233);
#define CAN3TXIDR3 _CAN3TXIDR3.Byte
#define CAN3TXIDR3_RTR _CAN3TXIDR3.Bits.RTR
#define CAN3TXIDR3_ID0 _CAN3TXIDR3.Bits.ID0
#define CAN3TXIDR3_ID1 _CAN3TXIDR3.Bits.ID1
#define CAN3TXIDR3_ID2 _CAN3TXIDR3.Bits.ID2
#define CAN3TXIDR3_ID3 _CAN3TXIDR3.Bits.ID3
#define CAN3TXIDR3_ID4 _CAN3TXIDR3.Bits.ID4
#define CAN3TXIDR3_ID5 _CAN3TXIDR3.Bits.ID5
#define CAN3TXIDR3_ID6 _CAN3TXIDR3.Bits.ID6
#define CAN3TXIDR3_ID _CAN3TXIDR3.MergedBits.grpID


/*** CAN3TXDSR0 - MSCAN 3 Transmit Data Segment Register 0; 0x00000234 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3TXDSR0STR;
extern volatile CAN3TXDSR0STR _CAN3TXDSR0 @(REG_BASE + 0x00000234);
#define CAN3TXDSR0 _CAN3TXDSR0.Byte
#define CAN3TXDSR0_DB0 _CAN3TXDSR0.Bits.DB0
#define CAN3TXDSR0_DB1 _CAN3TXDSR0.Bits.DB1
#define CAN3TXDSR0_DB2 _CAN3TXDSR0.Bits.DB2
#define CAN3TXDSR0_DB3 _CAN3TXDSR0.Bits.DB3
#define CAN3TXDSR0_DB4 _CAN3TXDSR0.Bits.DB4
#define CAN3TXDSR0_DB5 _CAN3TXDSR0.Bits.DB5
#define CAN3TXDSR0_DB6 _CAN3TXDSR0.Bits.DB6
#define CAN3TXDSR0_DB7 _CAN3TXDSR0.Bits.DB7
#define CAN3TXDSR0_DB _CAN3TXDSR0.MergedBits.grpDB


/*** CAN3TXDSR1 - MSCAN 3 Transmit Data Segment Register 1; 0x00000235 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3TXDSR1STR;
extern volatile CAN3TXDSR1STR _CAN3TXDSR1 @(REG_BASE + 0x00000235);
#define CAN3TXDSR1 _CAN3TXDSR1.Byte
#define CAN3TXDSR1_DB0 _CAN3TXDSR1.Bits.DB0
#define CAN3TXDSR1_DB1 _CAN3TXDSR1.Bits.DB1
#define CAN3TXDSR1_DB2 _CAN3TXDSR1.Bits.DB2
#define CAN3TXDSR1_DB3 _CAN3TXDSR1.Bits.DB3
#define CAN3TXDSR1_DB4 _CAN3TXDSR1.Bits.DB4
#define CAN3TXDSR1_DB5 _CAN3TXDSR1.Bits.DB5
#define CAN3TXDSR1_DB6 _CAN3TXDSR1.Bits.DB6
#define CAN3TXDSR1_DB7 _CAN3TXDSR1.Bits.DB7
#define CAN3TXDSR1_DB _CAN3TXDSR1.MergedBits.grpDB


/*** CAN3TXDSR2 - MSCAN 3 Transmit Data Segment Register 2; 0x00000236 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3TXDSR2STR;
extern volatile CAN3TXDSR2STR _CAN3TXDSR2 @(REG_BASE + 0x00000236);
#define CAN3TXDSR2 _CAN3TXDSR2.Byte
#define CAN3TXDSR2_DB0 _CAN3TXDSR2.Bits.DB0
#define CAN3TXDSR2_DB1 _CAN3TXDSR2.Bits.DB1
#define CAN3TXDSR2_DB2 _CAN3TXDSR2.Bits.DB2
#define CAN3TXDSR2_DB3 _CAN3TXDSR2.Bits.DB3
#define CAN3TXDSR2_DB4 _CAN3TXDSR2.Bits.DB4
#define CAN3TXDSR2_DB5 _CAN3TXDSR2.Bits.DB5
#define CAN3TXDSR2_DB6 _CAN3TXDSR2.Bits.DB6
#define CAN3TXDSR2_DB7 _CAN3TXDSR2.Bits.DB7
#define CAN3TXDSR2_DB _CAN3TXDSR2.MergedBits.grpDB


/*** CAN3TXDSR3 - MSCAN 3 Transmit Data Segment Register 3; 0x00000237 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3TXDSR3STR;
extern volatile CAN3TXDSR3STR _CAN3TXDSR3 @(REG_BASE + 0x00000237);
#define CAN3TXDSR3 _CAN3TXDSR3.Byte
#define CAN3TXDSR3_DB0 _CAN3TXDSR3.Bits.DB0
#define CAN3TXDSR3_DB1 _CAN3TXDSR3.Bits.DB1
#define CAN3TXDSR3_DB2 _CAN3TXDSR3.Bits.DB2
#define CAN3TXDSR3_DB3 _CAN3TXDSR3.Bits.DB3
#define CAN3TXDSR3_DB4 _CAN3TXDSR3.Bits.DB4
#define CAN3TXDSR3_DB5 _CAN3TXDSR3.Bits.DB5
#define CAN3TXDSR3_DB6 _CAN3TXDSR3.Bits.DB6
#define CAN3TXDSR3_DB7 _CAN3TXDSR3.Bits.DB7
#define CAN3TXDSR3_DB _CAN3TXDSR3.MergedBits.grpDB


/*** CAN3TXDSR4 - MSCAN 3 Transmit Data Segment Register 4; 0x00000238 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3TXDSR4STR;
extern volatile CAN3TXDSR4STR _CAN3TXDSR4 @(REG_BASE + 0x00000238);
#define CAN3TXDSR4 _CAN3TXDSR4.Byte
#define CAN3TXDSR4_DB0 _CAN3TXDSR4.Bits.DB0
#define CAN3TXDSR4_DB1 _CAN3TXDSR4.Bits.DB1
#define CAN3TXDSR4_DB2 _CAN3TXDSR4.Bits.DB2
#define CAN3TXDSR4_DB3 _CAN3TXDSR4.Bits.DB3
#define CAN3TXDSR4_DB4 _CAN3TXDSR4.Bits.DB4
#define CAN3TXDSR4_DB5 _CAN3TXDSR4.Bits.DB5
#define CAN3TXDSR4_DB6 _CAN3TXDSR4.Bits.DB6
#define CAN3TXDSR4_DB7 _CAN3TXDSR4.Bits.DB7
#define CAN3TXDSR4_DB _CAN3TXDSR4.MergedBits.grpDB


/*** CAN3TXDSR5 - MSCAN 3 Transmit Data Segment Register 5; 0x00000239 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3TXDSR5STR;
extern volatile CAN3TXDSR5STR _CAN3TXDSR5 @(REG_BASE + 0x00000239);
#define CAN3TXDSR5 _CAN3TXDSR5.Byte
#define CAN3TXDSR5_DB0 _CAN3TXDSR5.Bits.DB0
#define CAN3TXDSR5_DB1 _CAN3TXDSR5.Bits.DB1
#define CAN3TXDSR5_DB2 _CAN3TXDSR5.Bits.DB2
#define CAN3TXDSR5_DB3 _CAN3TXDSR5.Bits.DB3
#define CAN3TXDSR5_DB4 _CAN3TXDSR5.Bits.DB4
#define CAN3TXDSR5_DB5 _CAN3TXDSR5.Bits.DB5
#define CAN3TXDSR5_DB6 _CAN3TXDSR5.Bits.DB6
#define CAN3TXDSR5_DB7 _CAN3TXDSR5.Bits.DB7
#define CAN3TXDSR5_DB _CAN3TXDSR5.MergedBits.grpDB


/*** CAN3TXDSR6 - MSCAN 3 Transmit Data Segment Register 6; 0x0000023A ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3TXDSR6STR;
extern volatile CAN3TXDSR6STR _CAN3TXDSR6 @(REG_BASE + 0x0000023A);
#define CAN3TXDSR6 _CAN3TXDSR6.Byte
#define CAN3TXDSR6_DB0 _CAN3TXDSR6.Bits.DB0
#define CAN3TXDSR6_DB1 _CAN3TXDSR6.Bits.DB1
#define CAN3TXDSR6_DB2 _CAN3TXDSR6.Bits.DB2
#define CAN3TXDSR6_DB3 _CAN3TXDSR6.Bits.DB3
#define CAN3TXDSR6_DB4 _CAN3TXDSR6.Bits.DB4
#define CAN3TXDSR6_DB5 _CAN3TXDSR6.Bits.DB5
#define CAN3TXDSR6_DB6 _CAN3TXDSR6.Bits.DB6
#define CAN3TXDSR6_DB7 _CAN3TXDSR6.Bits.DB7
#define CAN3TXDSR6_DB _CAN3TXDSR6.MergedBits.grpDB


/*** CAN3TXDSR7 - MSCAN 3 Transmit Data Segment Register 7; 0x0000023B ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN3TXDSR7STR;
extern volatile CAN3TXDSR7STR _CAN3TXDSR7 @(REG_BASE + 0x0000023B);
#define CAN3TXDSR7 _CAN3TXDSR7.Byte
#define CAN3TXDSR7_DB0 _CAN3TXDSR7.Bits.DB0
#define CAN3TXDSR7_DB1 _CAN3TXDSR7.Bits.DB1
#define CAN3TXDSR7_DB2 _CAN3TXDSR7.Bits.DB2
#define CAN3TXDSR7_DB3 _CAN3TXDSR7.Bits.DB3
#define CAN3TXDSR7_DB4 _CAN3TXDSR7.Bits.DB4
#define CAN3TXDSR7_DB5 _CAN3TXDSR7.Bits.DB5
#define CAN3TXDSR7_DB6 _CAN3TXDSR7.Bits.DB6
#define CAN3TXDSR7_DB7 _CAN3TXDSR7.Bits.DB7
#define CAN3TXDSR7_DB _CAN3TXDSR7.MergedBits.grpDB


/*** CAN3TXDLR - MSCAN 3 Transmit Data Length Register; 0x0000023C ***/
typedef union {
  byte Byte;
  struct {
    byte DLC0        :1;                                       /* Data Length Code Bit 0 */
    byte DLC1        :1;                                       /* Data Length Code Bit 1 */
    byte DLC2        :1;                                       /* Data Length Code Bit 2 */
    byte DLC3        :1;                                       /* Data Length Code Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDLC  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN3TXDLRSTR;
extern volatile CAN3TXDLRSTR _CAN3TXDLR @(REG_BASE + 0x0000023C);
#define CAN3TXDLR _CAN3TXDLR.Byte
#define CAN3TXDLR_DLC0 _CAN3TXDLR.Bits.DLC0
#define CAN3TXDLR_DLC1 _CAN3TXDLR.Bits.DLC1
#define CAN3TXDLR_DLC2 _CAN3TXDLR.Bits.DLC2
#define CAN3TXDLR_DLC3 _CAN3TXDLR.Bits.DLC3
#define CAN3TXDLR_DLC _CAN3TXDLR.MergedBits.grpDLC


/*** CAN3TXTBPR - MSCAN 3 Transmit Buffer Priority; 0x0000023F ***/
typedef union {
  byte Byte;
  struct {
    byte PRIO0       :1;                                       /* Transmit Buffer Priority Bit 0 */
    byte PRIO1       :1;                                       /* Transmit Buffer Priority Bit 1 */
    byte PRIO2       :1;                                       /* Transmit Buffer Priority Bit 2 */
    byte PRIO3       :1;                                       /* Transmit Buffer Priority Bit 3 */
    byte PRIO4       :1;                                       /* Transmit Buffer Priority Bit 4 */
    byte PRIO5       :1;                                       /* Transmit Buffer Priority Bit 5 */
    byte PRIO6       :1;                                       /* Transmit Buffer Priority Bit 6 */
    byte PRIO7       :1;                                       /* Transmit Buffer Priority Bit 7 */
  } Bits;
  struct {
    byte grpPRIO :8;
  } MergedBits;
} CAN3TXTBPRSTR;
extern volatile CAN3TXTBPRSTR _CAN3TXTBPR @(REG_BASE + 0x0000023F);
#define CAN3TXTBPR _CAN3TXTBPR.Byte
#define CAN3TXTBPR_PRIO0 _CAN3TXTBPR.Bits.PRIO0
#define CAN3TXTBPR_PRIO1 _CAN3TXTBPR.Bits.PRIO1
#define CAN3TXTBPR_PRIO2 _CAN3TXTBPR.Bits.PRIO2
#define CAN3TXTBPR_PRIO3 _CAN3TXTBPR.Bits.PRIO3
#define CAN3TXTBPR_PRIO4 _CAN3TXTBPR.Bits.PRIO4
#define CAN3TXTBPR_PRIO5 _CAN3TXTBPR.Bits.PRIO5
#define CAN3TXTBPR_PRIO6 _CAN3TXTBPR.Bits.PRIO6
#define CAN3TXTBPR_PRIO7 _CAN3TXTBPR.Bits.PRIO7
#define CAN3TXTBPR_PRIO _CAN3TXTBPR.MergedBits.grpPRIO


/*** PTT - Port T I/O Register; 0x00000240 ***/
typedef union {
  byte Byte;
  struct {
    byte PTT0        :1;                                       /* Port T Bit 0 */
    byte PTT1        :1;                                       /* Port T Bit 1 */
    byte PTT2        :1;                                       /* Port T Bit 2 */
    byte PTT3        :1;                                       /* Port T Bit 3 */
    byte PTT4        :1;                                       /* Port T Bit 4 */
    byte PTT5        :1;                                       /* Port T Bit 5 */
    byte PTT6        :1;                                       /* Port T Bit 6 */
    byte PTT7        :1;                                       /* Port T Bit 7 */
  } Bits;
  struct {
    byte grpPTT  :8;
  } MergedBits;
} PTTSTR;
extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240);
#define PTT _PTT.Byte
#define PTT_PTT0 _PTT.Bits.PTT0
#define PTT_PTT1 _PTT.Bits.PTT1
#define PTT_PTT2 _PTT.Bits.PTT2
#define PTT_PTT3 _PTT.Bits.PTT3
#define PTT_PTT4 _PTT.Bits.PTT4
#define PTT_PTT5 _PTT.Bits.PTT5
#define PTT_PTT6 _PTT.Bits.PTT6
#define PTT_PTT7 _PTT.Bits.PTT7
#define PTT_PTT _PTT.MergedBits.grpPTT


/*** PTIT - Port T Input; 0x00000241 ***/
typedef union {
  byte Byte;
  struct {
    byte PTIT0       :1;                                       /* Port T Bit 0 */
    byte PTIT1       :1;                                       /* Port T Bit 1 */
    byte PTIT2       :1;                                       /* Port T Bit 2 */
    byte PTIT3       :1;                                       /* Port T Bit 3 */
    byte PTIT4       :1;                                       /* Port T Bit 4 */
    byte PTIT5       :1;                                       /* Port T Bit 5 */
    byte PTIT6       :1;                                       /* Port T Bit 6 */
    byte PTIT7       :1;                                       /* Port T Bit 7 */
  } Bits;
  struct {
    byte grpPTIT :8;
  } MergedBits;
} PTITSTR;
extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241);
#define PTIT _PTIT.Byte
#define PTIT_PTIT0 _PTIT.Bits.PTIT0
#define PTIT_PTIT1 _PTIT.Bits.PTIT1
#define PTIT_PTIT2 _PTIT.Bits.PTIT2
#define PTIT_PTIT3 _PTIT.Bits.PTIT3
#define PTIT_PTIT4 _PTIT.Bits.PTIT4
#define PTIT_PTIT5 _PTIT.Bits.PTIT5
#define PTIT_PTIT6 _PTIT.Bits.PTIT6
#define PTIT_PTIT7 _PTIT.Bits.PTIT7
#define PTIT_PTIT _PTIT.MergedBits.grpPTIT


/*** DDRT - Port T Data Direction Register; 0x00000242 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRT0       :1;                                       /* Data Direction Port T Bit 0 */
    byte DDRT1       :1;                                       /* Data Direction Port T Bit 1 */
    byte DDRT2       :1;                                       /* Data Direction Port T Bit 2 */
    byte DDRT3       :1;                                       /* Data Direction Port T Bit 3 */
    byte DDRT4       :1;                                       /* Data Direction Port T Bit 4 */
    byte DDRT5       :1;                                       /* Data Direction Port T Bit 5 */
    byte DDRT6       :1;                                       /* Data Direction Port T Bit 6 */
    byte DDRT7       :1;                                       /* Data Direction Port T Bit 7 */
  } Bits;
  struct {
    byte grpDDRT :8;
  } MergedBits;
} DDRTSTR;
extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242);
#define DDRT _DDRT.Byte
#define DDRT_DDRT0 _DDRT.Bits.DDRT0
#define DDRT_DDRT1 _DDRT.Bits.DDRT1
#define DDRT_DDRT2 _DDRT.Bits.DDRT2
#define DDRT_DDRT3 _DDRT.Bits.DDRT3
#define DDRT_DDRT4 _DDRT.Bits.DDRT4
#define DDRT_DDRT5 _DDRT.Bits.DDRT5
#define DDRT_DDRT6 _DDRT.Bits.DDRT6
#define DDRT_DDRT7 _DDRT.Bits.DDRT7
#define DDRT_DDRT _DDRT.MergedBits.grpDDRT


/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/
typedef union {
  byte Byte;
  struct {
    byte RDRT0       :1;                                       /* Reduced Drive Port T Bit 0 */
    byte RDRT1       :1;                                       /* Reduced Drive Port T Bit 1 */
    byte RDRT2       :1;                                       /* Reduced Drive Port T Bit 2 */
    byte RDRT3       :1;                                       /* Reduced Drive Port T Bit 3 */
    byte RDRT4       :1;                                       /* Reduced Drive Port T Bit 4 */
    byte RDRT5       :1;                                       /* Reduced Drive Port T Bit 5 */
    byte RDRT6       :1;                                       /* Reduced Drive Port T Bit 6 */
    byte RDRT7       :1;                                       /* Reduced Drive Port T Bit 7 */
  } Bits;
  struct {
    byte grpRDRT :8;
  } MergedBits;
} RDRTSTR;
extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243);
#define RDRT _RDRT.Byte
#define RDRT_RDRT0 _RDRT.Bits.RDRT0
#define RDRT_RDRT1 _RDRT.Bits.RDRT1
#define RDRT_RDRT2 _RDRT.Bits.RDRT2
#define RDRT_RDRT3 _RDRT.Bits.RDRT3
#define RDRT_RDRT4 _RDRT.Bits.RDRT4
#define RDRT_RDRT5 _RDRT.Bits.RDRT5
#define RDRT_RDRT6 _RDRT.Bits.RDRT6
#define RDRT_RDRT7 _RDRT.Bits.RDRT7
#define RDRT_RDRT _RDRT.MergedBits.grpRDRT


/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/
typedef union {
  byte Byte;
  struct {
    byte PERT0       :1;                                       /* Pull Device Enable Port T Bit 0 */
    byte PERT1       :1;                                       /* Pull Device Enable Port T Bit 1 */
    byte PERT2       :1;                                       /* Pull Device Enable Port T Bit 2 */
    byte PERT3       :1;                                       /* Pull Device Enable Port T Bit 3 */
    byte PERT4       :1;                                       /* Pull Device Enable Port T Bit 4 */
    byte PERT5       :1;                                       /* Pull Device Enable Port T Bit 5 */
    byte PERT6       :1;                                       /* Pull Device Enable Port T Bit 6 */
    byte PERT7       :1;                                       /* Pull Device Enable Port T Bit 7 */
  } Bits;
  struct {
    byte grpPERT :8;
  } MergedBits;
} PERTSTR;
extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244);
#define PERT _PERT.Byte
#define PERT_PERT0 _PERT.Bits.PERT0
#define PERT_PERT1 _PERT.Bits.PERT1
#define PERT_PERT2 _PERT.Bits.PERT2
#define PERT_PERT3 _PERT.Bits.PERT3
#define PERT_PERT4 _PERT.Bits.PERT4
#define PERT_PERT5 _PERT.Bits.PERT5
#define PERT_PERT6 _PERT.Bits.PERT6
#define PERT_PERT7 _PERT.Bits.PERT7
#define PERT_PERT _PERT.MergedBits.grpPERT


/*** PPST - Port T Polarity Select Register; 0x00000245 ***/
typedef union {
  byte Byte;
  struct {
    byte PPST0       :1;                                       /* Pull Select Port T Bit 0 */
    byte PPST1       :1;                                       /* Pull Select Port T Bit 1 */
    byte PPST2       :1;                                       /* Pull Select Port T Bit 2 */
    byte PPST3       :1;                                       /* Pull Select Port T Bit 3 */
    byte PPST4       :1;                                       /* Pull Select Port T Bit 4 */
    byte PPST5       :1;                                       /* Pull Select Port T Bit 5 */
    byte PPST6       :1;                                       /* Pull Select Port T Bit 6 */
    byte PPST7       :1;                                       /* Pull Select Port T Bit 7 */
  } Bits;
  struct {
    byte grpPPST :8;
  } MergedBits;
} PPSTSTR;
extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245);
#define PPST _PPST.Byte
#define PPST_PPST0 _PPST.Bits.PPST0
#define PPST_PPST1 _PPST.Bits.PPST1
#define PPST_PPST2 _PPST.Bits.PPST2
#define PPST_PPST3 _PPST.Bits.PPST3
#define PPST_PPST4 _PPST.Bits.PPST4
#define PPST_PPST5 _PPST.Bits.PPST5
#define PPST_PPST6 _PPST.Bits.PPST6
#define PPST_PPST7 _PPST.Bits.PPST7
#define PPST_PPST _PPST.MergedBits.grpPPST


/*** PTS - Port S I/O Register; 0x00000248 ***/
typedef union {
  byte Byte;
  struct {
    byte PTS0        :1;                                       /* Port S Bit 0 */
    byte PTS1        :1;                                       /* Port S Bit 1 */
    byte PTS2        :1;                                       /* Port S Bit 2 */
    byte PTS3        :1;                                       /* Port S Bit 3 */
    byte PTS4        :1;                                       /* Port S Bit 4 */
    byte PTS5        :1;                                       /* Port S Bit 5 */
    byte PTS6        :1;                                       /* Port S Bit 6 */
    byte PTS7        :1;                                       /* Port S Bit 7 */
  } Bits;
  struct {
    byte grpPTS  :8;
  } MergedBits;
} PTSSTR;
extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248);
#define PTS _PTS.Byte
#define PTS_PTS0 _PTS.Bits.PTS0
#define PTS_PTS1 _PTS.Bits.PTS1
#define PTS_PTS2 _PTS.Bits.PTS2
#define PTS_PTS3 _PTS.Bits.PTS3
#define PTS_PTS4 _PTS.Bits.PTS4
#define PTS_PTS5 _PTS.Bits.PTS5
#define PTS_PTS6 _PTS.Bits.PTS6
#define PTS_PTS7 _PTS.Bits.PTS7
#define PTS_PTS _PTS.MergedBits.grpPTS


/*** PTIS - Port S Input; 0x00000249 ***/
typedef union {
  byte Byte;
  struct {
    byte PTIS0       :1;                                       /* Port S Bit 0 */
    byte PTIS1       :1;                                       /* Port S Bit 1 */
    byte PTIS2       :1;                                       /* Port S Bit 2 */
    byte PTIS3       :1;                                       /* Port S Bit 3 */
    byte PTIS4       :1;                                       /* Port S Bit 4 */
    byte PTIS5       :1;                                       /* Port S Bit 5 */
    byte PTIS6       :1;                                       /* Port S Bit 6 */
    byte PTIS7       :1;                                       /* Port S Bit 7 */
  } Bits;
  struct {
    byte grpPTIS :8;
  } MergedBits;
} PTISSTR;
extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249);
#define PTIS _PTIS.Byte
#define PTIS_PTIS0 _PTIS.Bits.PTIS0
#define PTIS_PTIS1 _PTIS.Bits.PTIS1
#define PTIS_PTIS2 _PTIS.Bits.PTIS2
#define PTIS_PTIS3 _PTIS.Bits.PTIS3
#define PTIS_PTIS4 _PTIS.Bits.PTIS4
#define PTIS_PTIS5 _PTIS.Bits.PTIS5
#define PTIS_PTIS6 _PTIS.Bits.PTIS6
#define PTIS_PTIS7 _PTIS.Bits.PTIS7
#define PTIS_PTIS _PTIS.MergedBits.grpPTIS


/*** DDRS - Port S Data Direction Register; 0x0000024A ***/
typedef union {
  byte Byte;
  struct {
    byte DDRS0       :1;                                       /* Data Direction Port S Bit 0 */
    byte DDRS1       :1;                                       /* Data Direction Port S Bit 1 */
    byte DDRS2       :1;                                       /* Data Direction Port S Bit  2 */
    byte DDRS3       :1;                                       /* Data Direction Port S Bit 3 */
    byte DDRS4       :1;                                       /* Data Direction Port S Bit 4 */
    byte DDRS5       :1;                                       /* Data Direction Port S Bit 5 */
    byte DDRS6       :1;                                       /* Data Direction Port S Bit 6 */
    byte DDRS7       :1;                                       /* Data Direction Port S Bit 7 */
  } Bits;
  struct {
    byte grpDDRS :8;
  } MergedBits;
} DDRSSTR;
extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A);
#define DDRS _DDRS.Byte
#define DDRS_DDRS0 _DDRS.Bits.DDRS0
#define DDRS_DDRS1 _DDRS.Bits.DDRS1
#define DDRS_DDRS2 _DDRS.Bits.DDRS2
#define DDRS_DDRS3 _DDRS.Bits.DDRS3
#define DDRS_DDRS4 _DDRS.Bits.DDRS4
#define DDRS_DDRS5 _DDRS.Bits.DDRS5
#define DDRS_DDRS6 _DDRS.Bits.DDRS6
#define DDRS_DDRS7 _DDRS.Bits.DDRS7
#define DDRS_DDRS _DDRS.MergedBits.grpDDRS


/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/
typedef union {
  byte Byte;
  struct {
    byte RDRS0       :1;                                       /* Reduced Drive Port S Bit 0 */
    byte RDRS1       :1;                                       /* Reduced Drive Port S Bit 1 */
    byte RDRS2       :1;                                       /* Reduced Drive Port S Bit 2 */
    byte RDRS3       :1;                                       /* Reduced Drive Port S Bit 3 */
    byte RDRS4       :1;                                       /* Reduced Drive Port S Bit 4 */
    byte RDRS5       :1;                                       /* Reduced Drive Port S Bit 5 */
    byte RDRS6       :1;                                       /* Reduced Drive Port S Bit 6 */
    byte RDRS7       :1;                                       /* Reduced Drive Port S Bit 7 */
  } Bits;
  struct {
    byte grpRDRS :8;
  } MergedBits;
} RDRSSTR;
extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B);
#define RDRS _RDRS.Byte
#define RDRS_RDRS0 _RDRS.Bits.RDRS0
#define RDRS_RDRS1 _RDRS.Bits.RDRS1
#define RDRS_RDRS2 _RDRS.Bits.RDRS2
#define RDRS_RDRS3 _RDRS.Bits.RDRS3
#define RDRS_RDRS4 _RDRS.Bits.RDRS4
#define RDRS_RDRS5 _RDRS.Bits.RDRS5
#define RDRS_RDRS6 _RDRS.Bits.RDRS6
#define RDRS_RDRS7 _RDRS.Bits.RDRS7
#define RDRS_RDRS _RDRS.MergedBits.grpRDRS


/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/
typedef union {
  byte Byte;
  struct {
    byte PERS0       :1;                                       /* Pull Device Enable Port S Bit 0 */
    byte PERS1       :1;                                       /* Pull Device Enable Port S Bit 1 */
    byte PERS2       :1;                                       /* Pull Device Enable Port S Bit 2 */
    byte PERS3       :1;                                       /* Pull Device Enable Port S Bit 3 */
    byte PERS4       :1;                                       /* Pull Device Enable Port S Bit 4 */
    byte PERS5       :1;                                       /* Pull Device Enable Port S Bit 5 */
    byte PERS6       :1;                                       /* Pull Device Enable Port S Bit 6 */
    byte PERS7       :1;                                       /* Pull Device Enable Port S Bit 7 */
  } Bits;
  struct {
    byte grpPERS :8;
  } MergedBits;
} PERSSTR;
extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C);
#define PERS _PERS.Byte
#define PERS_PERS0 _PERS.Bits.PERS0
#define PERS_PERS1 _PERS.Bits.PERS1
#define PERS_PERS2 _PERS.Bits.PERS2
#define PERS_PERS3 _PERS.Bits.PERS3
#define PERS_PERS4 _PERS.Bits.PERS4
#define PERS_PERS5 _PERS.Bits.PERS5
#define PERS_PERS6 _PERS.Bits.PERS6
#define PERS_PERS7 _PERS.Bits.PERS7
#define PERS_PERS _PERS.MergedBits.grpPERS


/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/
typedef union {
  byte Byte;
  struct {
    byte PPSS0       :1;                                       /* Pull Select Port S Bit 0 */
    byte PPSS1       :1;                                       /* Pull Select Port S Bit 1 */
    byte PPSS2       :1;                                       /* Pull Select Port S Bit 2 */
    byte PPSS3       :1;                                       /* Pull Select Port S Bit 3 */
    byte PPSS4       :1;                                       /* Pull Select Port S Bit 4 */
    byte PPSS5       :1;                                       /* Pull Select Port S Bit 5 */
    byte PPSS6       :1;                                       /* Pull Select Port S Bit 6 */
    byte PPSS7       :1;                                       /* Pull Select Port S Bit 7 */
  } Bits;
  struct {
    byte grpPPSS :8;
  } MergedBits;
} PPSSSTR;
extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D);
#define PPSS _PPSS.Byte
#define PPSS_PPSS0 _PPSS.Bits.PPSS0
#define PPSS_PPSS1 _PPSS.Bits.PPSS1
#define PPSS_PPSS2 _PPSS.Bits.PPSS2
#define PPSS_PPSS3 _PPSS.Bits.PPSS3
#define PPSS_PPSS4 _PPSS.Bits.PPSS4
#define PPSS_PPSS5 _PPSS.Bits.PPSS5
#define PPSS_PPSS6 _PPSS.Bits.PPSS6
#define PPSS_PPSS7 _PPSS.Bits.PPSS7
#define PPSS_PPSS _PPSS.MergedBits.grpPPSS


/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/
typedef union {
  byte Byte;
  struct {
    byte WOMS0       :1;                                       /* Wired-Or Mode Port S Bit 0 */
    byte WOMS1       :1;                                       /* Wired-Or Mode Port S Bit 1 */
    byte WOMS2       :1;                                       /* Wired-Or Mode Port S Bit 2 */
    byte WOMS3       :1;                                       /* Wired-Or Mode Port S Bit 3 */
    byte WOMS4       :1;                                       /* Wired-Or Mode Port S Bit 4 */
    byte WOMS5       :1;                                       /* Wired-Or Mode Port S Bit 5 */
    byte WOMS6       :1;                                       /* Wired-Or Mode Port S Bit 6 */
    byte WOMS7       :1;                                       /* Wired-Or Mode Port S Bit 7 */
  } Bits;
  struct {
    byte grpWOMS :8;
  } MergedBits;
} WOMSSTR;
extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E);
#define WOMS _WOMS.Byte
#define WOMS_WOMS0 _WOMS.Bits.WOMS0
#define WOMS_WOMS1 _WOMS.Bits.WOMS1
#define WOMS_WOMS2 _WOMS.Bits.WOMS2
#define WOMS_WOMS3 _WOMS.Bits.WOMS3
#define WOMS_WOMS4 _WOMS.Bits.WOMS4
#define WOMS_WOMS5 _WOMS.Bits.WOMS5
#define WOMS_WOMS6 _WOMS.Bits.WOMS6
#define WOMS_WOMS7 _WOMS.Bits.WOMS7
#define WOMS_WOMS _WOMS.MergedBits.grpWOMS


/*** PTM - Port M I/O Register; 0x00000250 ***/
typedef union {
  byte Byte;
  struct {
    byte PTM0        :1;                                       /* Port T Bit 0 */
    byte PTM1        :1;                                       /* Port T Bit 1 */
    byte PTM2        :1;                                       /* Port T Bit 2 */
    byte PTM3        :1;                                       /* Port T Bit 3 */
    byte PTM4        :1;                                       /* Port T Bit 4 */
    byte PTM5        :1;                                       /* Port T Bit 5 */
    byte PTM6        :1;                                       /* Port T Bit 6 */
    byte PTM7        :1;                                       /* Port T Bit 7 */
  } Bits;
  struct {
    byte grpPTM  :8;
  } MergedBits;
} PTMSTR;
extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250);
#define PTM _PTM.Byte
#define PTM_PTM0 _PTM.Bits.PTM0
#define PTM_PTM1 _PTM.Bits.PTM1
#define PTM_PTM2 _PTM.Bits.PTM2
#define PTM_PTM3 _PTM.Bits.PTM3
#define PTM_PTM4 _PTM.Bits.PTM4
#define PTM_PTM5 _PTM.Bits.PTM5
#define PTM_PTM6 _PTM.Bits.PTM6
#define PTM_PTM7 _PTM.Bits.PTM7
#define PTM_PTM _PTM.MergedBits.grpPTM


/*** PTIM - Port M Input; 0x00000251 ***/
typedef union {
  byte Byte;
  struct {
    byte PTIM0       :1;                                       /* Port M Bit 0 */
    byte PTIM1       :1;                                       /* Port M Bit 1 */
    byte PTIM2       :1;                                       /* Port M Bit 2 */
    byte PTIM3       :1;                                       /* Port M Bit 3 */
    byte PTIM4       :1;                                       /* Port M Bit 4 */
    byte PTIM5       :1;                                       /* Port M Bit 5 */
    byte PTIM6       :1;                                       /* Port M Bit 6 */
    byte PTIM7       :1;                                       /* Port M Bit 7 */
  } Bits;
  struct {
    byte grpPTIM :8;
  } MergedBits;
} PTIMSTR;
extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251);
#define PTIM _PTIM.Byte
#define PTIM_PTIM0 _PTIM.Bits.PTIM0
#define PTIM_PTIM1 _PTIM.Bits.PTIM1
#define PTIM_PTIM2 _PTIM.Bits.PTIM2
#define PTIM_PTIM3 _PTIM.Bits.PTIM3
#define PTIM_PTIM4 _PTIM.Bits.PTIM4
#define PTIM_PTIM5 _PTIM.Bits.PTIM5
#define PTIM_PTIM6 _PTIM.Bits.PTIM6
#define PTIM_PTIM7 _PTIM.Bits.PTIM7
#define PTIM_PTIM _PTIM.MergedBits.grpPTIM


/*** DDRM - Port M Data Direction Register; 0x00000252 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRM0       :1;                                       /* Data Direction Port M Bit 0 */
    byte DDRM1       :1;                                       /* Data Direction Port M Bit 1 */
    byte DDRM2       :1;                                       /* Data Direction Port M Bit 2 */
    byte DDRM3       :1;                                       /* Data Direction Port M Bit 3 */
    byte DDRM4       :1;                                       /* Data Direction Port M Bit 4 */
    byte DDRM5       :1;                                       /* Data Direction Port M Bit 5 */
    byte DDRM6       :1;                                       /* Data Direction Port M Bit 6 */
    byte DDRM7       :1;                                       /* Data Direction Port M Bit 7 */
  } Bits;
  struct {
    byte grpDDRM :8;
  } MergedBits;
} DDRMSTR;
extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252);
#define DDRM _DDRM.Byte
#define DDRM_DDRM0 _DDRM.Bits.DDRM0
#define DDRM_DDRM1 _DDRM.Bits.DDRM1
#define DDRM_DDRM2 _DDRM.Bits.DDRM2
#define DDRM_DDRM3 _DDRM.Bits.DDRM3
#define DDRM_DDRM4 _DDRM.Bits.DDRM4
#define DDRM_DDRM5 _DDRM.Bits.DDRM5
#define DDRM_DDRM6 _DDRM.Bits.DDRM6
#define DDRM_DDRM7 _DDRM.Bits.DDRM7
#define DDRM_DDRM _DDRM.MergedBits.grpDDRM


/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/
typedef union {
  byte Byte;
  struct {
    byte RDRM0       :1;                                       /* Reduced Drive Port M Bit 0 */
    byte RDRM1       :1;                                       /* Reduced Drive Port M Bit 1 */
    byte RDRM2       :1;                                       /* Reduced Drive Port M Bit 2 */
    byte RDRM3       :1;                                       /* Reduced Drive Port M Bit 3 */
    byte RDRM4       :1;                                       /* Reduced Drive Port M Bit 4 */
    byte RDRM5       :1;                                       /* Reduced Drive Port M Bit 5 */
    byte RDRM6       :1;                                       /* Reduced Drive Port M Bit 6 */
    byte RDRM7       :1;                                       /* Reduced Drive Port M Bit 7 */
  } Bits;
  struct {
    byte grpRDRM :8;
  } MergedBits;
} RDRMSTR;
extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253);
#define RDRM _RDRM.Byte
#define RDRM_RDRM0 _RDRM.Bits.RDRM0
#define RDRM_RDRM1 _RDRM.Bits.RDRM1
#define RDRM_RDRM2 _RDRM.Bits.RDRM2
#define RDRM_RDRM3 _RDRM.Bits.RDRM3
#define RDRM_RDRM4 _RDRM.Bits.RDRM4
#define RDRM_RDRM5 _RDRM.Bits.RDRM5
#define RDRM_RDRM6 _RDRM.Bits.RDRM6
#define RDRM_RDRM7 _RDRM.Bits.RDRM7
#define RDRM_RDRM _RDRM.MergedBits.grpRDRM


/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/
typedef union {
  byte Byte;
  struct {
    byte PERM0       :1;                                       /* Pull Device Enable Port M Bit 0 */
    byte PERM1       :1;                                       /* Pull Device Enable Port M Bit 1 */
    byte PERM2       :1;                                       /* Pull Device Enable Port M Bit 2 */
    byte PERM3       :1;                                       /* Pull Device Enable Port M Bit 3 */
    byte PERM4       :1;                                       /* Pull Device Enable Port M Bit 4 */
    byte PERM5       :1;                                       /* Pull Device Enable Port M Bit 5 */
    byte PERM6       :1;                                       /* Pull Device Enable Port M Bit 6 */
    byte PERM7       :1;                                       /* Pull Device Enable Port M Bit 7 */
  } Bits;
  struct {
    byte grpPERM :8;
  } MergedBits;
} PERMSTR;
extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254);
#define PERM _PERM.Byte
#define PERM_PERM0 _PERM.Bits.PERM0
#define PERM_PERM1 _PERM.Bits.PERM1
#define PERM_PERM2 _PERM.Bits.PERM2
#define PERM_PERM3 _PERM.Bits.PERM3
#define PERM_PERM4 _PERM.Bits.PERM4
#define PERM_PERM5 _PERM.Bits.PERM5
#define PERM_PERM6 _PERM.Bits.PERM6
#define PERM_PERM7 _PERM.Bits.PERM7
#define PERM_PERM _PERM.MergedBits.grpPERM


/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/
typedef union {
  byte Byte;
  struct {
    byte PPSM0       :1;                                       /* Pull Select Port M Bit 0 */
    byte PPSM1       :1;                                       /* Pull Select Port M Bit 1 */
    byte PPSM2       :1;                                       /* Pull Select Port M Bit 2 */
    byte PPSM3       :1;                                       /* Pull Select Port M Bit 3 */
    byte PPSM4       :1;                                       /* Pull Select Port M Bit 4 */
    byte PPSM5       :1;                                       /* Pull Select Port M Bit 5 */
    byte PPSM6       :1;                                       /* Pull Select Port M Bit 6 */
    byte PPSM7       :1;                                       /* Pull Select Port M Bit 7 */
  } Bits;
  struct {
    byte grpPPSM :8;
  } MergedBits;
} PPSMSTR;
extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255);
#define PPSM _PPSM.Byte
#define PPSM_PPSM0 _PPSM.Bits.PPSM0
#define PPSM_PPSM1 _PPSM.Bits.PPSM1
#define PPSM_PPSM2 _PPSM.Bits.PPSM2
#define PPSM_PPSM3 _PPSM.Bits.PPSM3
#define PPSM_PPSM4 _PPSM.Bits.PPSM4
#define PPSM_PPSM5 _PPSM.Bits.PPSM5
#define PPSM_PPSM6 _PPSM.Bits.PPSM6
#define PPSM_PPSM7 _PPSM.Bits.PPSM7
#define PPSM_PPSM _PPSM.MergedBits.grpPPSM


/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/
typedef union {
  byte Byte;
  struct {
    byte WOMM0       :1;                                       /* Wired-Or Mode Port M Bit 0 */
    byte WOMM1       :1;                                       /* Wired-Or Mode Port M Bit 1 */
    byte WOMM2       :1;                                       /* Wired-Or Mode Port M Bit 2 */
    byte WOMM3       :1;                                       /* Wired-Or Mode Port M Bit 3 */
    byte WOMM4       :1;                                       /* Wired-Or Mode Port M Bit 4 */
    byte WOMM5       :1;                                       /* Wired-Or Mode Port M Bit 5 */
    byte WOMM6       :1;                                       /* Wired-Or Mode Port M Bit 6 */
    byte WOMM7       :1;                                       /* Wired-Or Mode Port M Bit 7 */
  } Bits;
  struct {
    byte grpWOMM :8;
  } MergedBits;
} WOMMSTR;
extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256);
#define WOMM _WOMM.Byte
#define WOMM_WOMM0 _WOMM.Bits.WOMM0
#define WOMM_WOMM1 _WOMM.Bits.WOMM1
#define WOMM_WOMM2 _WOMM.Bits.WOMM2
#define WOMM_WOMM3 _WOMM.Bits.WOMM3
#define WOMM_WOMM4 _WOMM.Bits.WOMM4
#define WOMM_WOMM5 _WOMM.Bits.WOMM5
#define WOMM_WOMM6 _WOMM.Bits.WOMM6
#define WOMM_WOMM7 _WOMM.Bits.WOMM7
#define WOMM_WOMM _WOMM.MergedBits.grpWOMM


/*** MODRR - Module Routing Register; 0x00000257 ***/
typedef union {
  byte Byte;
  struct {
    byte MODRR0      :1;                                       /* CAN0 Routing */
    byte MODRR1      :1;                                       /* CAN0 Routing */
    byte MODRR2      :1;                                       /* CAN4 Routing */
    byte MODRR3      :1;                                       /* CAN4 Routing */
    byte MODRR4      :1;                                       /* SPI0 Routing */
    byte MODRR5      :1;                                       /* SPI1 Routing */
    byte MODRR6      :1;                                       /* SPI2 Routing */
    byte             :1; 
  } Bits;
  struct {
    byte grpMODRR :7;
    byte         :1;
  } MergedBits;
} MODRRSTR;
extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000257);
#define MODRR _MODRR.Byte
#define MODRR_MODRR0 _MODRR.Bits.MODRR0
#define MODRR_MODRR1 _MODRR.Bits.MODRR1
#define MODRR_MODRR2 _MODRR.Bits.MODRR2
#define MODRR_MODRR3 _MODRR.Bits.MODRR3
#define MODRR_MODRR4 _MODRR.Bits.MODRR4
#define MODRR_MODRR5 _MODRR.Bits.MODRR5
#define MODRR_MODRR6 _MODRR.Bits.MODRR6
#define MODRR_MODRR _MODRR.MergedBits.grpMODRR


/*** PTP - Port P I/O Register; 0x00000258 ***/
typedef union {
  byte Byte;
  struct {
    byte PTP0        :1;                                       /* Port P Bit 0 */
    byte PTP1        :1;                                       /* Port P Bit 1 */
    byte PTP2        :1;                                       /* Port P Bit 2 */
    byte PTP3        :1;                                       /* Port P Bit 3 */
    byte PTP4        :1;                                       /* Port P Bit 4 */
    byte PTP5        :1;                                       /* Port P Bit 5 */
    byte PTP6        :1;                                       /* Port P Bit 6 */
    byte PTP7        :1;                                       /* Port P Bit 7 */
  } Bits;
  struct {
    byte grpPTP  :8;
  } MergedBits;
} PTPSTR;
extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258);
#define PTP _PTP.Byte
#define PTP_PTP0 _PTP.Bits.PTP0
#define PTP_PTP1 _PTP.Bits.PTP1
#define PTP_PTP2 _PTP.Bits.PTP2
#define PTP_PTP3 _PTP.Bits.PTP3
#define PTP_PTP4 _PTP.Bits.PTP4
#define PTP_PTP5 _PTP.Bits.PTP5
#define PTP_PTP6 _PTP.Bits.PTP6
#define PTP_PTP7 _PTP.Bits.PTP7
#define PTP_PTP _PTP.MergedBits.grpPTP


/*** PTIP - Port P Input; 0x00000259 ***/
typedef union {
  byte Byte;
  struct {
    byte PTIP0       :1;                                       /* Port P Bit 0 */
    byte PTIP1       :1;                                       /* Port P Bit 1 */
    byte PTIP2       :1;                                       /* Port P Bit 2 */
    byte PTIP3       :1;                                       /* Port P Bit 3 */
    byte PTIP4       :1;                                       /* Port P Bit 4 */
    byte PTIP5       :1;                                       /* Port P Bit 5 */
    byte PTIP6       :1;                                       /* Port P Bit 6 */
    byte PTIP7       :1;                                       /* Port P Bit 7 */
  } Bits;
  struct {
    byte grpPTIP :8;
  } MergedBits;
} PTIPSTR;
extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259);
#define PTIP _PTIP.Byte
#define PTIP_PTIP0 _PTIP.Bits.PTIP0
#define PTIP_PTIP1 _PTIP.Bits.PTIP1
#define PTIP_PTIP2 _PTIP.Bits.PTIP2
#define PTIP_PTIP3 _PTIP.Bits.PTIP3
#define PTIP_PTIP4 _PTIP.Bits.PTIP4
#define PTIP_PTIP5 _PTIP.Bits.PTIP5
#define PTIP_PTIP6 _PTIP.Bits.PTIP6
#define PTIP_PTIP7 _PTIP.Bits.PTIP7
#define PTIP_PTIP _PTIP.MergedBits.grpPTIP


/*** DDRP - Port P Data Direction Register; 0x0000025A ***/
typedef union {
  byte Byte;
  struct {
    byte DDRP0       :1;                                       /* Data Direction Port P Bit 0 */
    byte DDRP1       :1;                                       /* Data Direction Port P Bit 1 */
    byte DDRP2       :1;                                       /* Data Direction Port P Bit 2 */
    byte DDRP3       :1;                                       /* Data Direction Port P Bit 3 */
    byte DDRP4       :1;                                       /* Data Direction Port P Bit 4 */
    byte DDRP5       :1;                                       /* Data Direction Port P Bit 5 */
    byte DDRP6       :1;                                       /* Data Direction Port P Bit 6 */
    byte DDRP7       :1;                                       /* Data Direction Port P Bit 7 */
  } Bits;
  struct {
    byte grpDDRP :8;
  } MergedBits;
} DDRPSTR;
extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A);
#define DDRP _DDRP.Byte
#define DDRP_DDRP0 _DDRP.Bits.DDRP0
#define DDRP_DDRP1 _DDRP.Bits.DDRP1
#define DDRP_DDRP2 _DDRP.Bits.DDRP2
#define DDRP_DDRP3 _DDRP.Bits.DDRP3
#define DDRP_DDRP4 _DDRP.Bits.DDRP4
#define DDRP_DDRP5 _DDRP.Bits.DDRP5
#define DDRP_DDRP6 _DDRP.Bits.DDRP6
#define DDRP_DDRP7 _DDRP.Bits.DDRP7
#define DDRP_DDRP _DDRP.MergedBits.grpDDRP


/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/
typedef union {
  byte Byte;
  struct {
    byte RDRP0       :1;                                       /* Reduced Drive Port P Bit 0 */
    byte RDRP1       :1;                                       /* Reduced Drive Port P Bit 1 */
    byte RDRP2       :1;                                       /* Reduced Drive Port P Bit 2 */
    byte RDRP3       :1;                                       /* Reduced Drive Port P Bit 3 */
    byte RDRP4       :1;                                       /* Reduced Drive Port P Bit 4 */
    byte RDRP5       :1;                                       /* Reduced Drive Port P Bit 5 */
    byte RDRP6       :1;                                       /* Reduced Drive Port P Bit 6 */
    byte RDRP7       :1;                                       /* Reduced Drive Port P Bit 7 */
  } Bits;
  struct {
    byte grpRDRP :8;
  } MergedBits;
} RDRPSTR;
extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B);
#define RDRP _RDRP.Byte
#define RDRP_RDRP0 _RDRP.Bits.RDRP0
#define RDRP_RDRP1 _RDRP.Bits.RDRP1
#define RDRP_RDRP2 _RDRP.Bits.RDRP2
#define RDRP_RDRP3 _RDRP.Bits.RDRP3
#define RDRP_RDRP4 _RDRP.Bits.RDRP4
#define RDRP_RDRP5 _RDRP.Bits.RDRP5
#define RDRP_RDRP6 _RDRP.Bits.RDRP6
#define RDRP_RDRP7 _RDRP.Bits.RDRP7
#define RDRP_RDRP _RDRP.MergedBits.grpRDRP


/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/
typedef union {
  byte Byte;
  struct {
    byte PERP0       :1;                                       /* Pull Device Enable Port P Bit 0 */
    byte PERP1       :1;                                       /* Pull Device Enable Port P Bit 1 */
    byte PERP2       :1;                                       /* Pull Device Enable Port P Bit 2 */
    byte PERP3       :1;                                       /* Pull Device Enable Port P Bit 3 */
    byte PERP4       :1;                                       /* Pull Device Enable Port P Bit 4 */
    byte PERP5       :1;                                       /* Pull Device Enable Port P Bit 5 */
    byte PERP6       :1;                                       /* Pull Device Enable Port P Bit 6 */
    byte PERP7       :1;                                       /* Pull Device Enable Port P Bit 7 */
  } Bits;
  struct {
    byte grpPERP :8;
  } MergedBits;
} PERPSTR;
extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C);
#define PERP _PERP.Byte
#define PERP_PERP0 _PERP.Bits.PERP0
#define PERP_PERP1 _PERP.Bits.PERP1
#define PERP_PERP2 _PERP.Bits.PERP2
#define PERP_PERP3 _PERP.Bits.PERP3
#define PERP_PERP4 _PERP.Bits.PERP4
#define PERP_PERP5 _PERP.Bits.PERP5
#define PERP_PERP6 _PERP.Bits.PERP6
#define PERP_PERP7 _PERP.Bits.PERP7
#define PERP_PERP _PERP.MergedBits.grpPERP


/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/
typedef union {
  byte Byte;
  struct {
    byte PPSP0       :1;                                       /* Pull Select Port P Bit 0 */
    byte PPSP1       :1;                                       /* Pull Select Port P Bit 1 */
    byte PPSP2       :1;                                       /* Pull Select Port P Bit 2 */
    byte PPSP3       :1;                                       /* Pull Select Port P Bit 3 */
    byte PPSP4       :1;                                       /* Pull Select Port P Bit 4 */
    byte PPSP5       :1;                                       /* Pull Select Port P Bit 5 */
    byte PPSP6       :1;                                       /* Pull Select Port P Bit 6 */
    byte PPSP7       :1;                                       /* Pull Select Port P Bit 7 */
  } Bits;
  struct {
    byte grpPPSP :8;
  } MergedBits;
} PPSPSTR;
extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D);
#define PPSP _PPSP.Byte
#define PPSP_PPSP0 _PPSP.Bits.PPSP0
#define PPSP_PPSP1 _PPSP.Bits.PPSP1
#define PPSP_PPSP2 _PPSP.Bits.PPSP2
#define PPSP_PPSP3 _PPSP.Bits.PPSP3
#define PPSP_PPSP4 _PPSP.Bits.PPSP4
#define PPSP_PPSP5 _PPSP.Bits.PPSP5
#define PPSP_PPSP6 _PPSP.Bits.PPSP6
#define PPSP_PPSP7 _PPSP.Bits.PPSP7
#define PPSP_PPSP _PPSP.MergedBits.grpPPSP


/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/
typedef union {
  byte Byte;
  struct {
    byte PIEP0       :1;                                       /* Interrupt Enable Port P Bit 0 */
    byte PIEP1       :1;                                       /* Interrupt Enable Port P Bit 1 */
    byte PIEP2       :1;                                       /* Interrupt Enable Port P Bit 2 */
    byte PIEP3       :1;                                       /* Interrupt Enable Port P Bit 3 */
    byte PIEP4       :1;                                       /* Interrupt Enable Port P Bit 4 */
    byte PIEP5       :1;                                       /* Interrupt Enable Port P Bit 5 */
    byte PIEP6       :1;                                       /* Interrupt Enable Port P Bit 6 */
    byte PIEP7       :1;                                       /* Interrupt Enable Port P Bit 7 */
  } Bits;
  struct {
    byte grpPIEP :8;
  } MergedBits;
} PIEPSTR;
extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E);
#define PIEP _PIEP.Byte
#define PIEP_PIEP0 _PIEP.Bits.PIEP0
#define PIEP_PIEP1 _PIEP.Bits.PIEP1
#define PIEP_PIEP2 _PIEP.Bits.PIEP2
#define PIEP_PIEP3 _PIEP.Bits.PIEP3
#define PIEP_PIEP4 _PIEP.Bits.PIEP4
#define PIEP_PIEP5 _PIEP.Bits.PIEP5
#define PIEP_PIEP6 _PIEP.Bits.PIEP6
#define PIEP_PIEP7 _PIEP.Bits.PIEP7
#define PIEP_PIEP _PIEP.MergedBits.grpPIEP


/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/
typedef union {
  byte Byte;
  struct {
    byte PIFP0       :1;                                       /* Interrupt Flags Port P Bit 0 */
    byte PIFP1       :1;                                       /* Interrupt Flags Port P Bit 1 */
    byte PIFP2       :1;                                       /* Interrupt Flags Port P Bit 2 */
    byte PIFP3       :1;                                       /* Interrupt Flags Port P Bit 3 */
    byte PIFP4       :1;                                       /* Interrupt Flags Port P Bit 4 */
    byte PIFP5       :1;                                       /* Interrupt Flags Port P Bit 5 */
    byte PIFP6       :1;                                       /* Interrupt Flags Port P Bit 6 */
    byte PIFP7       :1;                                       /* Interrupt Flags Port P Bit 7 */
  } Bits;
  struct {
    byte grpPIFP :8;
  } MergedBits;
} PIFPSTR;
extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F);
#define PIFP _PIFP.Byte
#define PIFP_PIFP0 _PIFP.Bits.PIFP0
#define PIFP_PIFP1 _PIFP.Bits.PIFP1
#define PIFP_PIFP2 _PIFP.Bits.PIFP2
#define PIFP_PIFP3 _PIFP.Bits.PIFP3
#define PIFP_PIFP4 _PIFP.Bits.PIFP4
#define PIFP_PIFP5 _PIFP.Bits.PIFP5
#define PIFP_PIFP6 _PIFP.Bits.PIFP6
#define PIFP_PIFP7 _PIFP.Bits.PIFP7
#define PIFP_PIFP _PIFP.MergedBits.grpPIFP


/*** PTH - Port H I/O Register; 0x00000260 ***/
typedef union {
  byte Byte;
  struct {
    byte PTH0        :1;                                       /* Port H Bit 0 */
    byte PTH1        :1;                                       /* Port H Bit 1 */
    byte PTH2        :1;                                       /* Port H Bit 2 */
    byte PTH3        :1;                                       /* Port H Bit 3 */
    byte PTH4        :1;                                       /* Port H Bit 4 */
    byte PTH5        :1;                                       /* Port H Bit 5 */
    byte PTH6        :1;                                       /* Port H Bit 6 */
    byte PTH7        :1;                                       /* Port H Bit 7 */
  } Bits;
  struct {
    byte grpPTH  :8;
  } MergedBits;
} PTHSTR;
extern volatile PTHSTR _PTH @(REG_BASE + 0x00000260);
#define PTH _PTH.Byte
#define PTH_PTH0 _PTH.Bits.PTH0
#define PTH_PTH1 _PTH.Bits.PTH1
#define PTH_PTH2 _PTH.Bits.PTH2
#define PTH_PTH3 _PTH.Bits.PTH3
#define PTH_PTH4 _PTH.Bits.PTH4
#define PTH_PTH5 _PTH.Bits.PTH5
#define PTH_PTH6 _PTH.Bits.PTH6
#define PTH_PTH7 _PTH.Bits.PTH7
#define PTH_PTH _PTH.MergedBits.grpPTH


/*** PTIH - Port H Input Register; 0x00000261 ***/
typedef union {
  byte Byte;
  struct {
    byte PTIH0       :1;                                       /* Port H Bit 0 */
    byte PTIH1       :1;                                       /* Port H Bit 1 */
    byte PTIH2       :1;                                       /* Port H Bit 2 */
    byte PTIH3       :1;                                       /* Port H Bit 3 */
    byte PTIH4       :1;                                       /* Port H Bit 4 */
    byte PTIH5       :1;                                       /* Port H Bit 5 */
    byte PTIH6       :1;                                       /* Port H Bit 6 */
    byte PTIH7       :1;                                       /* Port H Bit 7 */
  } Bits;
  struct {
    byte grpPTIH :8;
  } MergedBits;
} PTIHSTR;
extern volatile PTIHSTR _PTIH @(REG_BASE + 0x00000261);
#define PTIH _PTIH.Byte
#define PTIH_PTIH0 _PTIH.Bits.PTIH0
#define PTIH_PTIH1 _PTIH.Bits.PTIH1
#define PTIH_PTIH2 _PTIH.Bits.PTIH2
#define PTIH_PTIH3 _PTIH.Bits.PTIH3
#define PTIH_PTIH4 _PTIH.Bits.PTIH4
#define PTIH_PTIH5 _PTIH.Bits.PTIH5
#define PTIH_PTIH6 _PTIH.Bits.PTIH6
#define PTIH_PTIH7 _PTIH.Bits.PTIH7
#define PTIH_PTIH _PTIH.MergedBits.grpPTIH


/*** DDRH - Port H Data Direction Register; 0x00000262 ***/
typedef union {
  byte Byte;
  struct {
    byte DDRH0       :1;                                       /* Data Direction Port H Bit 0 */
    byte DDRH1       :1;                                       /* Data Direction Port H Bit 1 */
    byte DDRH2       :1;                                       /* Data Direction Port H Bit 2 */
    byte DDRH3       :1;                                       /* Data Direction Port H Bit 3 */
    byte DDRH4       :1;                                       /* Data Direction Port H Bit 4 */
    byte DDRH5       :1;                                       /* Data Direction Port H Bit 5 */
    byte DDRH6       :1;                                       /* Data Direction Port H Bit 6 */
    byte DDRH7       :1;                                       /* Data Direction Port H Bit 7 */
  } Bits;
  struct {
    byte grpDDRH :8;
  } MergedBits;
} DDRHSTR;
extern volatile DDRHSTR _DDRH @(REG_BASE + 0x00000262);
#define DDRH _DDRH.Byte
#define DDRH_DDRH0 _DDRH.Bits.DDRH0
#define DDRH_DDRH1 _DDRH.Bits.DDRH1
#define DDRH_DDRH2 _DDRH.Bits.DDRH2
#define DDRH_DDRH3 _DDRH.Bits.DDRH3
#define DDRH_DDRH4 _DDRH.Bits.DDRH4
#define DDRH_DDRH5 _DDRH.Bits.DDRH5
#define DDRH_DDRH6 _DDRH.Bits.DDRH6
#define DDRH_DDRH7 _DDRH.Bits.DDRH7
#define DDRH_DDRH _DDRH.MergedBits.grpDDRH


/*** RDRH - Port H Reduced Drive Register; 0x00000263 ***/
typedef union {
  byte Byte;
  struct {
    byte RDRH0       :1;                                       /* Reduced Drive Port H Bit 0 */
    byte RDRH1       :1;                                       /* Reduced Drive Port H Bit 1 */
    byte RDRH2       :1;                                       /* Reduced Drive Port H Bit 2 */
    byte RDRH3       :1;                                       /* Reduced Drive Port H Bit 3 */
    byte RDRH4       :1;                                       /* Reduced Drive Port H Bit 4 */
    byte RDRH5       :1;                                       /* Reduced Drive Port H Bit 5 */
    byte RDRH6       :1;                                       /* Reduced Drive Port H Bit 6 */
    byte RDRH7       :1;                                       /* Reduced Drive Port H Bit 7 */
  } Bits;
  struct {
    byte grpRDRH :8;
  } MergedBits;
} RDRHSTR;
extern volatile RDRHSTR _RDRH @(REG_BASE + 0x00000263);
#define RDRH _RDRH.Byte
#define RDRH_RDRH0 _RDRH.Bits.RDRH0
#define RDRH_RDRH1 _RDRH.Bits.RDRH1
#define RDRH_RDRH2 _RDRH.Bits.RDRH2
#define RDRH_RDRH3 _RDRH.Bits.RDRH3
#define RDRH_RDRH4 _RDRH.Bits.RDRH4
#define RDRH_RDRH5 _RDRH.Bits.RDRH5
#define RDRH_RDRH6 _RDRH.Bits.RDRH6
#define RDRH_RDRH7 _RDRH.Bits.RDRH7
#define RDRH_RDRH _RDRH.MergedBits.grpRDRH


/*** PERH - Port H Pull Device Enable Register; 0x00000264 ***/
typedef union {
  byte Byte;
  struct {
    byte PERH0       :1;                                       /* Pull Device Enable Port H Bit 0 */
    byte PERH1       :1;                                       /* Pull Device Enable Port H Bit 1 */
    byte PERH2       :1;                                       /* Pull Device Enable Port H Bit 2 */
    byte PERH3       :1;                                       /* Pull Device Enable Port H Bit 3 */
    byte PERH4       :1;                                       /* Pull Device Enable Port H Bit 4 */
    byte PERH5       :1;                                       /* Pull Device Enable Port H Bit 5 */
    byte PERH6       :1;                                       /* Pull Device Enable Port H Bit 6 */
    byte PERH7       :1;                                       /* Pull Device Enable Port H Bit 7 */
  } Bits;
  struct {
    byte grpPERH :8;
  } MergedBits;
} PERHSTR;
extern volatile PERHSTR _PERH @(REG_BASE + 0x00000264);
#define PERH _PERH.Byte
#define PERH_PERH0 _PERH.Bits.PERH0
#define PERH_PERH1 _PERH.Bits.PERH1
#define PERH_PERH2 _PERH.Bits.PERH2
#define PERH_PERH3 _PERH.Bits.PERH3
#define PERH_PERH4 _PERH.Bits.PERH4
#define PERH_PERH5 _PERH.Bits.PERH5
#define PERH_PERH6 _PERH.Bits.PERH6
#define PERH_PERH7 _PERH.Bits.PERH7
#define PERH_PERH _PERH.MergedBits.grpPERH


/*** PPSH - Port H Polarity Select Register; 0x00000265 ***/
typedef union {
  byte Byte;
  struct {
    byte PPSH0       :1;                                       /* Pull Select Port H Bit 0 */
    byte PPSH1       :1;                                       /* Pull Select Port H Bit 1 */
    byte PPSH2       :1;                                       /* Pull Select Port H Bit 2 */
    byte PPSH3       :1;                                       /* Pull Select Port H Bit 3 */
    byte PPSH4       :1;                                       /* Pull Select Port H Bit 4 */
    byte PPSH5       :1;                                       /* Pull Select Port H Bit 5 */
    byte PPSH6       :1;                                       /* Pull Select Port H Bit 6 */
    byte PPSH7       :1;                                       /* Pull Select Port H Bit 7 */
  } Bits;
  struct {
    byte grpPPSH :8;
  } MergedBits;
} PPSHSTR;
extern volatile PPSHSTR _PPSH @(REG_BASE + 0x00000265);
#define PPSH _PPSH.Byte
#define PPSH_PPSH0 _PPSH.Bits.PPSH0
#define PPSH_PPSH1 _PPSH.Bits.PPSH1
#define PPSH_PPSH2 _PPSH.Bits.PPSH2
#define PPSH_PPSH3 _PPSH.Bits.PPSH3
#define PPSH_PPSH4 _PPSH.Bits.PPSH4
#define PPSH_PPSH5 _PPSH.Bits.PPSH5
#define PPSH_PPSH6 _PPSH.Bits.PPSH6
#define PPSH_PPSH7 _PPSH.Bits.PPSH7
#define PPSH_PPSH _PPSH.MergedBits.grpPPSH


/*** PIEH - Port H Interrupt Enable Register; 0x00000266 ***/
typedef union {
  byte Byte;
  struct {
    byte PIEH0       :1;                                       /* Interrupt Enable Port H Bit 0 */
    byte PIEH1       :1;                                       /* Interrupt Enable Port H Bit 1 */
    byte PIEH2       :1;                                       /* Interrupt Enable Port H Bit 2 */
    byte PIEH3       :1;                                       /* Interrupt Enable Port H Bit 3 */
    byte PIEH4       :1;                                       /* Interrupt Enable Port H Bit 4 */
    byte PIEH5       :1;                                       /* Interrupt Enable Port H Bit 5 */
    byte PIEH6       :1;                                       /* Interrupt Enable Port H Bit 6 */
    byte PIEH7       :1;                                       /* Interrupt Enable Port H Bit 7 */
  } Bits;
  struct {
    byte grpPIEH :8;
  } MergedBits;
} PIEHSTR;
extern volatile PIEHSTR _PIEH @(REG_BASE + 0x00000266);
#define PIEH _PIEH.Byte
#define PIEH_PIEH0 _PIEH.Bits.PIEH0
#define PIEH_PIEH1 _PIEH.Bits.PIEH1
#define PIEH_PIEH2 _PIEH.Bits.PIEH2
#define PIEH_PIEH3 _PIEH.Bits.PIEH3
#define PIEH_PIEH4 _PIEH.Bits.PIEH4
#define PIEH_PIEH5 _PIEH.Bits.PIEH5
#define PIEH_PIEH6 _PIEH.Bits.PIEH6
#define PIEH_PIEH7 _PIEH.Bits.PIEH7
#define PIEH_PIEH _PIEH.MergedBits.grpPIEH


/*** PIFH - Port H Interrupt Flag Register; 0x00000267 ***/
typedef union {
  byte Byte;
  struct {
    byte PIFH0       :1;                                       /* Interrupt Flags Port H Bit 0 */
    byte PIFH1       :1;                                       /* Interrupt Flags Port H Bit 1 */
    byte PIFH2       :1;                                       /* Interrupt Flags Port H Bit 2 */
    byte PIFH3       :1;                                       /* Interrupt Flags Port H Bit 3 */
    byte PIFH4       :1;                                       /* Interrupt Flags Port H Bit 4 */
    byte PIFH5       :1;                                       /* Interrupt Flags Port H Bit 5 */
    byte PIFH6       :1;                                       /* Interrupt Flags Port H Bit 6 */
    byte PIFH7       :1;                                       /* Interrupt Flags Port H Bit 7 */
  } Bits;
  struct {
    byte grpPIFH :8;
  } MergedBits;
} PIFHSTR;
extern volatile PIFHSTR _PIFH @(REG_BASE + 0x00000267);
#define PIFH _PIFH.Byte
#define PIFH_PIFH0 _PIFH.Bits.PIFH0
#define PIFH_PIFH1 _PIFH.Bits.PIFH1
#define PIFH_PIFH2 _PIFH.Bits.PIFH2
#define PIFH_PIFH3 _PIFH.Bits.PIFH3
#define PIFH_PIFH4 _PIFH.Bits.PIFH4
#define PIFH_PIFH5 _PIFH.Bits.PIFH5
#define PIFH_PIFH6 _PIFH.Bits.PIFH6
#define PIFH_PIFH7 _PIFH.Bits.PIFH7
#define PIFH_PIFH _PIFH.MergedBits.grpPIFH


/*** PTJ - Port J I/O Register; 0x00000268 ***/
typedef union {
  byte Byte;
  struct {
    byte PTJ0        :1;                                       /* Port J Bit 0 */
    byte PTJ1        :1;                                       /* Port J Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte PTJ6        :1;                                       /* Port J Bit 6 */
    byte PTJ7        :1;                                       /* Port J Bit 7 */
  } Bits;
  struct {
    byte grpPTJ  :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpPTJ_6 :2;
  } MergedBits;
} PTJSTR;
extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268);
#define PTJ _PTJ.Byte
#define PTJ_PTJ0 _PTJ.Bits.PTJ0
#define PTJ_PTJ1 _PTJ.Bits.PTJ1
#define PTJ_PTJ6 _PTJ.Bits.PTJ6
#define PTJ_PTJ7 _PTJ.Bits.PTJ7
#define PTJ_PTJ _PTJ.MergedBits.grpPTJ
#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6


/*** PTIJ - Port J Input Register; 0x00000269 ***/
typedef union {
  byte Byte;
  struct {
    byte PTIJ0       :1;                                       /* Port J Bit 0 */
    byte PTIJ1       :1;                                       /* Port J Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte PTIJ6       :1;                                       /* Port J Bit 6 */
    byte PTIJ7       :1;                                       /* Port J Bit 7 */
  } Bits;
  struct {
    byte grpPTIJ :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpPTIJ_6 :2;
  } MergedBits;
} PTIJSTR;
extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269);
#define PTIJ _PTIJ.Byte
#define PTIJ_PTIJ0 _PTIJ.Bits.PTIJ0
#define PTIJ_PTIJ1 _PTIJ.Bits.PTIJ1
#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6
#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7
#define PTIJ_PTIJ _PTIJ.MergedBits.grpPTIJ
#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6


/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/
typedef union {
  byte Byte;
  struct {
    byte DDRJ0       :1;                                       /* Data Direction Port J Bit 0 */
    byte DDRJ1       :1;                                       /* Data Direction Port J Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte DDRJ6       :1;                                       /* Data Direction Port J Bit 6 */
    byte DDRJ7       :1;                                       /* Data Direction Port J Bit 7 */
  } Bits;
  struct {
    byte grpDDRJ :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpDDRJ_6 :2;
  } MergedBits;
} DDRJSTR;
extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A);
#define DDRJ _DDRJ.Byte
#define DDRJ_DDRJ0 _DDRJ.Bits.DDRJ0
#define DDRJ_DDRJ1 _DDRJ.Bits.DDRJ1
#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6
#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7
#define DDRJ_DDRJ _DDRJ.MergedBits.grpDDRJ
#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6


/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/
typedef union {
  byte Byte;
  struct {
    byte RDRJ0       :1;                                       /* Reduced Drive Port J Bit 0 */
    byte RDRJ1       :1;                                       /* Reduced Drive Port J Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte RDRJ6       :1;                                       /* Reduced Drive Port J Bit 6 */
    byte RDRJ7       :1;                                       /* Reduced Drive Port J Bit 7 */
  } Bits;
  struct {
    byte grpRDRJ :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpRDRJ_6 :2;
  } MergedBits;
} RDRJSTR;
extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B);
#define RDRJ _RDRJ.Byte
#define RDRJ_RDRJ0 _RDRJ.Bits.RDRJ0
#define RDRJ_RDRJ1 _RDRJ.Bits.RDRJ1
#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6
#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7
#define RDRJ_RDRJ _RDRJ.MergedBits.grpRDRJ
#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6


/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/
typedef union {
  byte Byte;
  struct {
    byte PERJ0       :1;                                       /* Pull Device Enable Port J Bit 0 */
    byte PERJ1       :1;                                       /* Pull Device Enable Port J Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte PERJ6       :1;                                       /* Pull Device Enable Port J Bit 6 */
    byte PERJ7       :1;                                       /* Pull Device Enable Port J Bit 7 */
  } Bits;
  struct {
    byte grpPERJ :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpPERJ_6 :2;
  } MergedBits;
} PERJSTR;
extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C);
#define PERJ _PERJ.Byte
#define PERJ_PERJ0 _PERJ.Bits.PERJ0
#define PERJ_PERJ1 _PERJ.Bits.PERJ1
#define PERJ_PERJ6 _PERJ.Bits.PERJ6
#define PERJ_PERJ7 _PERJ.Bits.PERJ7
#define PERJ_PERJ _PERJ.MergedBits.grpPERJ
#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6


/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/
typedef union {
  byte Byte;
  struct {
    byte PPSJ0       :1;                                       /* Pull Select Port J Bit 0 */
    byte PPSJ1       :1;                                       /* Pull Select Port J Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte PPSJ6       :1;                                       /* Pull Select Port J Bit 6 */
    byte PPSJ7       :1;                                       /* Pull Select Port J Bit 7 */
  } Bits;
  struct {
    byte grpPPSJ :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpPPSJ_6 :2;
  } MergedBits;
} PPSJSTR;
extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D);
#define PPSJ _PPSJ.Byte
#define PPSJ_PPSJ0 _PPSJ.Bits.PPSJ0
#define PPSJ_PPSJ1 _PPSJ.Bits.PPSJ1
#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6
#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7
#define PPSJ_PPSJ _PPSJ.MergedBits.grpPPSJ
#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6


/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/
typedef union {
  byte Byte;
  struct {
    byte PIEJ0       :1;                                       /* Interrupt Enable Port J Bit 0 */
    byte PIEJ1       :1;                                       /* Interrupt Enable Port J Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte PIEJ6       :1;                                       /* Interrupt Enable Port J Bit 6 */
    byte PIEJ7       :1;                                       /* Interrupt Enable Port J Bit 7 */
  } Bits;
  struct {
    byte grpPIEJ :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpPIEJ_6 :2;
  } MergedBits;
} PIEJSTR;
extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E);
#define PIEJ _PIEJ.Byte
#define PIEJ_PIEJ0 _PIEJ.Bits.PIEJ0
#define PIEJ_PIEJ1 _PIEJ.Bits.PIEJ1
#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6
#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7
#define PIEJ_PIEJ _PIEJ.MergedBits.grpPIEJ
#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6


/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/
typedef union {
  byte Byte;
  struct {
    byte PIFJ0       :1;                                       /* Interrupt Flags Port J Bit 0 */
    byte PIFJ1       :1;                                       /* Interrupt Flags Port J Bit 1 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte PIFJ6       :1;                                       /* Interrupt Flags Port J Bit 6 */
    byte PIFJ7       :1;                                       /* Interrupt Flags Port J Bit 7 */
  } Bits;
  struct {
    byte grpPIFJ :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpPIFJ_6 :2;
  } MergedBits;
} PIFJSTR;
extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F);
#define PIFJ _PIFJ.Byte
#define PIFJ_PIFJ0 _PIFJ.Bits.PIFJ0
#define PIFJ_PIFJ1 _PIFJ.Bits.PIFJ1
#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6
#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7
#define PIFJ_PIFJ _PIFJ.MergedBits.grpPIFJ
#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6


/*** CAN4CTL0 - MSCAN4 Control 0 Register; 0x00000280 ***/
typedef union {
  byte Byte;
  struct {
    byte INITRQ      :1;                                       /* Initialization Mode Request */
    byte SLPRQ       :1;                                       /* Sleep Mode Request */
    byte WUPE        :1;                                       /* Wake-Up Enable */
    byte TIME        :1;                                       /* Timer Enable */
    byte SYNCH       :1;                                       /* Synchronized Status */
    byte CSWAI       :1;                                       /* CAN Stops in Wait Mode */
    byte RXACT       :1;                                       /* Receiver Active Status */
    byte RXFRM       :1;                                       /* Received Frame Flag */
  } Bits;
} CAN4CTL0STR;
extern volatile CAN4CTL0STR _CAN4CTL0 @(REG_BASE + 0x00000280);
#define CAN4CTL0 _CAN4CTL0.Byte
#define CAN4CTL0_INITRQ _CAN4CTL0.Bits.INITRQ
#define CAN4CTL0_SLPRQ _CAN4CTL0.Bits.SLPRQ
#define CAN4CTL0_WUPE _CAN4CTL0.Bits.WUPE
#define CAN4CTL0_TIME _CAN4CTL0.Bits.TIME
#define CAN4CTL0_SYNCH _CAN4CTL0.Bits.SYNCH
#define CAN4CTL0_CSWAI _CAN4CTL0.Bits.CSWAI
#define CAN4CTL0_RXACT _CAN4CTL0.Bits.RXACT
#define CAN4CTL0_RXFRM _CAN4CTL0.Bits.RXFRM


/*** CAN4CTL1 - MSCAN4 Control 1 Register; 0x00000281 ***/
typedef union {
  byte Byte;
  struct {
    byte INITAK      :1;                                       /* Initialization Mode Acknowledge */
    byte SLPAK       :1;                                       /* Sleep Mode Acknowledge */
    byte WUPM        :1;                                       /* Wake-Up Mode */
    byte             :1; 
    byte LISTEN      :1;                                       /* Listen Only Mode */
    byte LOOPB       :1;                                       /* Loop Back Self Test Mode */
    byte CLKSRC      :1;                                       /* MSCAN4 Clock Source */
    byte CANE        :1;                                       /* MSCAN4 Enable */
  } Bits;
} CAN4CTL1STR;
extern volatile CAN4CTL1STR _CAN4CTL1 @(REG_BASE + 0x00000281);
#define CAN4CTL1 _CAN4CTL1.Byte
#define CAN4CTL1_INITAK _CAN4CTL1.Bits.INITAK
#define CAN4CTL1_SLPAK _CAN4CTL1.Bits.SLPAK
#define CAN4CTL1_WUPM _CAN4CTL1.Bits.WUPM
#define CAN4CTL1_LISTEN _CAN4CTL1.Bits.LISTEN
#define CAN4CTL1_LOOPB _CAN4CTL1.Bits.LOOPB
#define CAN4CTL1_CLKSRC _CAN4CTL1.Bits.CLKSRC
#define CAN4CTL1_CANE _CAN4CTL1.Bits.CANE


/*** CAN4BTR0 - MSCAN4 Bus Timing Register 0; 0x00000282 ***/
typedef union {
  byte Byte;
  struct {
    byte BRP0        :1;                                       /* Baud Rate Prescaler 0 */
    byte BRP1        :1;                                       /* Baud Rate Prescaler 1 */
    byte BRP2        :1;                                       /* Baud Rate Prescaler 2 */
    byte BRP3        :1;                                       /* Baud Rate Prescaler 3 */
    byte BRP4        :1;                                       /* Baud Rate Prescaler 4 */
    byte BRP5        :1;                                       /* Baud Rate Prescaler 5 */
    byte SJW0        :1;                                       /* Synchronization Jump Width 0 */
    byte SJW1        :1;                                       /* Synchronization Jump Width 1 */
  } Bits;
  struct {
    byte grpBRP  :6;
    byte grpSJW  :2;
  } MergedBits;
} CAN4BTR0STR;
extern volatile CAN4BTR0STR _CAN4BTR0 @(REG_BASE + 0x00000282);
#define CAN4BTR0 _CAN4BTR0.Byte
#define CAN4BTR0_BRP0 _CAN4BTR0.Bits.BRP0
#define CAN4BTR0_BRP1 _CAN4BTR0.Bits.BRP1
#define CAN4BTR0_BRP2 _CAN4BTR0.Bits.BRP2
#define CAN4BTR0_BRP3 _CAN4BTR0.Bits.BRP3
#define CAN4BTR0_BRP4 _CAN4BTR0.Bits.BRP4
#define CAN4BTR0_BRP5 _CAN4BTR0.Bits.BRP5
#define CAN4BTR0_SJW0 _CAN4BTR0.Bits.SJW0
#define CAN4BTR0_SJW1 _CAN4BTR0.Bits.SJW1
#define CAN4BTR0_BRP _CAN4BTR0.MergedBits.grpBRP
#define CAN4BTR0_SJW _CAN4BTR0.MergedBits.grpSJW


/*** CAN4BTR1 - MSCAN4 Bus Timing Register 1; 0x00000283 ***/
typedef union {
  byte Byte;
  struct {
    byte TSEG10      :1;                                       /* Time Segment 1 */
    byte TSEG11      :1;                                       /* Time Segment 1 */
    byte TSEG12      :1;                                       /* Time Segment 1 */
    byte TSEG13      :1;                                       /* Time Segment 1 */
    byte TSEG20      :1;                                       /* Time Segment 2 */
    byte TSEG21      :1;                                       /* Time Segment 2 */
    byte TSEG22      :1;                                       /* Time Segment 2 */
    byte SAMP        :1;                                       /* Sampling */
  } Bits;
  struct {
    byte grpTSEG_10 :4;
    byte grpTSEG_20 :3;
    byte         :1;
  } MergedBits;
} CAN4BTR1STR;
extern volatile CAN4BTR1STR _CAN4BTR1 @(REG_BASE + 0x00000283);
#define CAN4BTR1 _CAN4BTR1.Byte
#define CAN4BTR1_TSEG10 _CAN4BTR1.Bits.TSEG10
#define CAN4BTR1_TSEG11 _CAN4BTR1.Bits.TSEG11
#define CAN4BTR1_TSEG12 _CAN4BTR1.Bits.TSEG12
#define CAN4BTR1_TSEG13 _CAN4BTR1.Bits.TSEG13
#define CAN4BTR1_TSEG20 _CAN4BTR1.Bits.TSEG20
#define CAN4BTR1_TSEG21 _CAN4BTR1.Bits.TSEG21
#define CAN4BTR1_TSEG22 _CAN4BTR1.Bits.TSEG22
#define CAN4BTR1_SAMP _CAN4BTR1.Bits.SAMP
#define CAN4BTR1_TSEG_10 _CAN4BTR1.MergedBits.grpTSEG_10
#define CAN4BTR1_TSEG_20 _CAN4BTR1.MergedBits.grpTSEG_20
#define CAN4BTR1_TSEG CAN4BTR1_TSEG_10


/*** CAN4RFLG - MSCAN4 Receiver Flag Register; 0x00000284 ***/
typedef union {
  byte Byte;
  struct {
    byte RXF         :1;                                       /* Receive Buffer Full */
    byte OVRIF       :1;                                       /* Overrun Interrupt Flag */
    byte TSTAT0      :1;                                       /* Transmitter Status Bit 0 */
    byte TSTAT1      :1;                                       /* Transmitter Status Bit 1 */
    byte RSTAT0      :1;                                       /* Receiver Status Bit 0 */
    byte RSTAT1      :1;                                       /* Receiver Status Bit 1 */
    byte CSCIF       :1;                                       /* CAN Status Change Interrupt Flag */
    byte WUPIF       :1;                                       /* Wake-up Interrupt Flag */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpTSTAT :2;
    byte grpRSTAT :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN4RFLGSTR;
extern volatile CAN4RFLGSTR _CAN4RFLG @(REG_BASE + 0x00000284);
#define CAN4RFLG _CAN4RFLG.Byte
#define CAN4RFLG_RXF _CAN4RFLG.Bits.RXF
#define CAN4RFLG_OVRIF _CAN4RFLG.Bits.OVRIF
#define CAN4RFLG_TSTAT0 _CAN4RFLG.Bits.TSTAT0
#define CAN4RFLG_TSTAT1 _CAN4RFLG.Bits.TSTAT1
#define CAN4RFLG_RSTAT0 _CAN4RFLG.Bits.RSTAT0
#define CAN4RFLG_RSTAT1 _CAN4RFLG.Bits.RSTAT1
#define CAN4RFLG_CSCIF _CAN4RFLG.Bits.CSCIF
#define CAN4RFLG_WUPIF _CAN4RFLG.Bits.WUPIF
#define CAN4RFLG_TSTAT _CAN4RFLG.MergedBits.grpTSTAT
#define CAN4RFLG_RSTAT _CAN4RFLG.MergedBits.grpRSTAT


/*** CAN4RIER - MSCAN4 Receiver Interrupt Enable Register; 0x00000285 ***/
typedef union {
  byte Byte;
  struct {
    byte RXFIE       :1;                                       /* Receiver Full Interrupt Enable */
    byte OVRIE       :1;                                       /* Overrun Interrupt Enable */
    byte TSTATE0     :1;                                       /* Transmitter Status Change Enable 0 */
    byte TSTATE1     :1;                                       /* Transmitter Status Change Enable 1 */
    byte RSTATE0     :1;                                       /* Receiver Status Change Enable 0 */
    byte RSTATE1     :1;                                       /* Receiver Status Change Enable 1 */
    byte CSCIE       :1;                                       /* CAN Status Change Interrupt Enable */
    byte WUPIE       :1;                                       /* Wake-up Interrupt Enable */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte grpTSTATE :2;
    byte grpRSTATE :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN4RIERSTR;
extern volatile CAN4RIERSTR _CAN4RIER @(REG_BASE + 0x00000285);
#define CAN4RIER _CAN4RIER.Byte
#define CAN4RIER_RXFIE _CAN4RIER.Bits.RXFIE
#define CAN4RIER_OVRIE _CAN4RIER.Bits.OVRIE
#define CAN4RIER_TSTATE0 _CAN4RIER.Bits.TSTATE0
#define CAN4RIER_TSTATE1 _CAN4RIER.Bits.TSTATE1
#define CAN4RIER_RSTATE0 _CAN4RIER.Bits.RSTATE0
#define CAN4RIER_RSTATE1 _CAN4RIER.Bits.RSTATE1
#define CAN4RIER_CSCIE _CAN4RIER.Bits.CSCIE
#define CAN4RIER_WUPIE _CAN4RIER.Bits.WUPIE
#define CAN4RIER_TSTATE _CAN4RIER.MergedBits.grpTSTATE
#define CAN4RIER_RSTATE _CAN4RIER.MergedBits.grpRSTATE


/*** CAN4TFLG - MSCAN4 Transmitter Flag Register; 0x00000286 ***/
typedef union {
  byte Byte;
  struct {
    byte TXE0        :1;                                       /* Transmitter Buffer Empty 0 */
    byte TXE1        :1;                                       /* Transmitter Buffer Empty 1 */
    byte TXE2        :1;                                       /* Transmitter Buffer Empty 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTXE  :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN4TFLGSTR;
extern volatile CAN4TFLGSTR _CAN4TFLG @(REG_BASE + 0x00000286);
#define CAN4TFLG _CAN4TFLG.Byte
#define CAN4TFLG_TXE0 _CAN4TFLG.Bits.TXE0
#define CAN4TFLG_TXE1 _CAN4TFLG.Bits.TXE1
#define CAN4TFLG_TXE2 _CAN4TFLG.Bits.TXE2
#define CAN4TFLG_TXE _CAN4TFLG.MergedBits.grpTXE


/*** CAN4TIER - MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 ***/
typedef union {
  byte Byte;
  struct {
    byte TXEIE0      :1;                                       /* Transmitter Empty Interrupt Enable 0 */
    byte TXEIE1      :1;                                       /* Transmitter Empty Interrupt Enable 1 */
    byte TXEIE2      :1;                                       /* Transmitter Empty Interrupt Enable 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTXEIE :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN4TIERSTR;
extern volatile CAN4TIERSTR _CAN4TIER @(REG_BASE + 0x00000287);
#define CAN4TIER _CAN4TIER.Byte
#define CAN4TIER_TXEIE0 _CAN4TIER.Bits.TXEIE0
#define CAN4TIER_TXEIE1 _CAN4TIER.Bits.TXEIE1
#define CAN4TIER_TXEIE2 _CAN4TIER.Bits.TXEIE2
#define CAN4TIER_TXEIE _CAN4TIER.MergedBits.grpTXEIE


/*** CAN4TARQ - MSCAN 4 Transmitter Message Abort Request; 0x00000288 ***/
typedef union {
  byte Byte;
  struct {
    byte ABTRQ0      :1;                                       /* Abort Request 0 */
    byte ABTRQ1      :1;                                       /* Abort Request 1 */
    byte ABTRQ2      :1;                                       /* Abort Request 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpABTRQ :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN4TARQSTR;
extern volatile CAN4TARQSTR _CAN4TARQ @(REG_BASE + 0x00000288);
#define CAN4TARQ _CAN4TARQ.Byte
#define CAN4TARQ_ABTRQ0 _CAN4TARQ.Bits.ABTRQ0
#define CAN4TARQ_ABTRQ1 _CAN4TARQ.Bits.ABTRQ1
#define CAN4TARQ_ABTRQ2 _CAN4TARQ.Bits.ABTRQ2
#define CAN4TARQ_ABTRQ _CAN4TARQ.MergedBits.grpABTRQ


/*** CAN4TAAK - MSCAN4 Transmitter Message Abort Control; 0x00000289 ***/
typedef union {
  byte Byte;
  struct {
    byte ABTAK0      :1;                                       /* Abort Acknowledge 0 */
    byte ABTAK1      :1;                                       /* Abort Acknowledge 1 */
    byte ABTAK2      :1;                                       /* Abort Acknowledge 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpABTAK :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN4TAAKSTR;
extern volatile CAN4TAAKSTR _CAN4TAAK @(REG_BASE + 0x00000289);
#define CAN4TAAK _CAN4TAAK.Byte
#define CAN4TAAK_ABTAK0 _CAN4TAAK.Bits.ABTAK0
#define CAN4TAAK_ABTAK1 _CAN4TAAK.Bits.ABTAK1
#define CAN4TAAK_ABTAK2 _CAN4TAAK.Bits.ABTAK2
#define CAN4TAAK_ABTAK _CAN4TAAK.MergedBits.grpABTAK


/*** CAN4TBSEL - MSCAN4 Transmit Buffer Selection; 0x0000028A ***/
typedef union {
  byte Byte;
  struct {
    byte TX0         :1;                                       /* Transmit Buffer Select 0 */
    byte TX1         :1;                                       /* Transmit Buffer Select 1 */
    byte TX2         :1;                                       /* Transmit Buffer Select 2 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpTX   :3;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN4TBSELSTR;
extern volatile CAN4TBSELSTR _CAN4TBSEL @(REG_BASE + 0x0000028A);
#define CAN4TBSEL _CAN4TBSEL.Byte
#define CAN4TBSEL_TX0 _CAN4TBSEL.Bits.TX0
#define CAN4TBSEL_TX1 _CAN4TBSEL.Bits.TX1
#define CAN4TBSEL_TX2 _CAN4TBSEL.Bits.TX2
#define CAN4TBSEL_TX _CAN4TBSEL.MergedBits.grpTX


/*** CAN4IDAC - MSCAN4 Identifier Acceptance Control Register; 0x0000028B ***/
typedef union {
  byte Byte;
  struct {
    byte IDHIT0      :1;                                       /* Identifier Acceptance Hit Indicator 0 */
    byte IDHIT1      :1;                                       /* Identifier Acceptance Hit Indicator 1 */
    byte IDHIT2      :1;                                       /* Identifier Acceptance Hit Indicator 2 */
    byte             :1; 
    byte IDAM0       :1;                                       /* Identifier Acceptance Mode 0 */
    byte IDAM1       :1;                                       /* Identifier Acceptance Mode 1 */
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpIDHIT :3;
    byte         :1;
    byte grpIDAM :2;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN4IDACSTR;
extern volatile CAN4IDACSTR _CAN4IDAC @(REG_BASE + 0x0000028B);
#define CAN4IDAC _CAN4IDAC.Byte
#define CAN4IDAC_IDHIT0 _CAN4IDAC.Bits.IDHIT0
#define CAN4IDAC_IDHIT1 _CAN4IDAC.Bits.IDHIT1
#define CAN4IDAC_IDHIT2 _CAN4IDAC.Bits.IDHIT2
#define CAN4IDAC_IDAM0 _CAN4IDAC.Bits.IDAM0
#define CAN4IDAC_IDAM1 _CAN4IDAC.Bits.IDAM1
#define CAN4IDAC_IDHIT _CAN4IDAC.MergedBits.grpIDHIT
#define CAN4IDAC_IDAM _CAN4IDAC.MergedBits.grpIDAM


/*** CAN4RXERR - MSCAN4 Receive Error Counter Register; 0x0000028E ***/
typedef union {
  byte Byte;
  struct {
    byte RXERR0      :1;                                       /* Bit 0 */
    byte RXERR1      :1;                                       /* Bit 1 */
    byte RXERR2      :1;                                       /* Bit 2 */
    byte RXERR3      :1;                                       /* Bit 3 */
    byte RXERR4      :1;                                       /* Bit 4 */
    byte RXERR5      :1;                                       /* Bit 5 */
    byte RXERR6      :1;                                       /* Bit 6 */
    byte RXERR7      :1;                                       /* Bit 7 */
  } Bits;
  struct {
    byte grpRXERR :8;
  } MergedBits;
} CAN4RXERRSTR;
extern volatile CAN4RXERRSTR _CAN4RXERR @(REG_BASE + 0x0000028E);
#define CAN4RXERR _CAN4RXERR.Byte
#define CAN4RXERR_RXERR0 _CAN4RXERR.Bits.RXERR0
#define CAN4RXERR_RXERR1 _CAN4RXERR.Bits.RXERR1
#define CAN4RXERR_RXERR2 _CAN4RXERR.Bits.RXERR2
#define CAN4RXERR_RXERR3 _CAN4RXERR.Bits.RXERR3
#define CAN4RXERR_RXERR4 _CAN4RXERR.Bits.RXERR4
#define CAN4RXERR_RXERR5 _CAN4RXERR.Bits.RXERR5
#define CAN4RXERR_RXERR6 _CAN4RXERR.Bits.RXERR6
#define CAN4RXERR_RXERR7 _CAN4RXERR.Bits.RXERR7
#define CAN4RXERR_RXERR _CAN4RXERR.MergedBits.grpRXERR


/*** CAN4TXERR - MSCAN4 Transmit Error Counter Register; 0x0000028F ***/
typedef union {
  byte Byte;
  struct {
    byte TXERR0      :1;                                       /* Bit 0 */
    byte TXERR1      :1;                                       /* Bit 1 */
    byte TXERR2      :1;                                       /* Bit 2 */
    byte TXERR3      :1;                                       /* Bit 3 */
    byte TXERR4      :1;                                       /* Bit 4 */
    byte TXERR5      :1;                                       /* Bit 5 */
    byte TXERR6      :1;                                       /* Bit 6 */
    byte TXERR7      :1;                                       /* Bit 7 */
  } Bits;
  struct {
    byte grpTXERR :8;
  } MergedBits;
} CAN4TXERRSTR;
extern volatile CAN4TXERRSTR _CAN4TXERR @(REG_BASE + 0x0000028F);
#define CAN4TXERR _CAN4TXERR.Byte
#define CAN4TXERR_TXERR0 _CAN4TXERR.Bits.TXERR0
#define CAN4TXERR_TXERR1 _CAN4TXERR.Bits.TXERR1
#define CAN4TXERR_TXERR2 _CAN4TXERR.Bits.TXERR2
#define CAN4TXERR_TXERR3 _CAN4TXERR.Bits.TXERR3
#define CAN4TXERR_TXERR4 _CAN4TXERR.Bits.TXERR4
#define CAN4TXERR_TXERR5 _CAN4TXERR.Bits.TXERR5
#define CAN4TXERR_TXERR6 _CAN4TXERR.Bits.TXERR6
#define CAN4TXERR_TXERR7 _CAN4TXERR.Bits.TXERR7
#define CAN4TXERR_TXERR _CAN4TXERR.MergedBits.grpTXERR


/*** CAN4IDAR0 - MSCAN4 Identifier Acceptance Register 0; 0x00000290 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN4IDAR0STR;
extern volatile CAN4IDAR0STR _CAN4IDAR0 @(REG_BASE + 0x00000290);
#define CAN4IDAR0 _CAN4IDAR0.Byte
#define CAN4IDAR0_AC0 _CAN4IDAR0.Bits.AC0
#define CAN4IDAR0_AC1 _CAN4IDAR0.Bits.AC1
#define CAN4IDAR0_AC2 _CAN4IDAR0.Bits.AC2
#define CAN4IDAR0_AC3 _CAN4IDAR0.Bits.AC3
#define CAN4IDAR0_AC4 _CAN4IDAR0.Bits.AC4
#define CAN4IDAR0_AC5 _CAN4IDAR0.Bits.AC5
#define CAN4IDAR0_AC6 _CAN4IDAR0.Bits.AC6
#define CAN4IDAR0_AC7 _CAN4IDAR0.Bits.AC7
#define CAN4IDAR0_AC _CAN4IDAR0.MergedBits.grpAC


/*** CAN4IDAR1 - MSCAN4 Identifier Acceptance Register 1; 0x00000291 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN4IDAR1STR;
extern volatile CAN4IDAR1STR _CAN4IDAR1 @(REG_BASE + 0x00000291);
#define CAN4IDAR1 _CAN4IDAR1.Byte
#define CAN4IDAR1_AC0 _CAN4IDAR1.Bits.AC0
#define CAN4IDAR1_AC1 _CAN4IDAR1.Bits.AC1
#define CAN4IDAR1_AC2 _CAN4IDAR1.Bits.AC2
#define CAN4IDAR1_AC3 _CAN4IDAR1.Bits.AC3
#define CAN4IDAR1_AC4 _CAN4IDAR1.Bits.AC4
#define CAN4IDAR1_AC5 _CAN4IDAR1.Bits.AC5
#define CAN4IDAR1_AC6 _CAN4IDAR1.Bits.AC6
#define CAN4IDAR1_AC7 _CAN4IDAR1.Bits.AC7
#define CAN4IDAR1_AC _CAN4IDAR1.MergedBits.grpAC


/*** CAN4IDAR2 - MSCAN4 Identifier Acceptance Register 2; 0x00000292 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN4IDAR2STR;
extern volatile CAN4IDAR2STR _CAN4IDAR2 @(REG_BASE + 0x00000292);
#define CAN4IDAR2 _CAN4IDAR2.Byte
#define CAN4IDAR2_AC0 _CAN4IDAR2.Bits.AC0
#define CAN4IDAR2_AC1 _CAN4IDAR2.Bits.AC1
#define CAN4IDAR2_AC2 _CAN4IDAR2.Bits.AC2
#define CAN4IDAR2_AC3 _CAN4IDAR2.Bits.AC3
#define CAN4IDAR2_AC4 _CAN4IDAR2.Bits.AC4
#define CAN4IDAR2_AC5 _CAN4IDAR2.Bits.AC5
#define CAN4IDAR2_AC6 _CAN4IDAR2.Bits.AC6
#define CAN4IDAR2_AC7 _CAN4IDAR2.Bits.AC7
#define CAN4IDAR2_AC _CAN4IDAR2.MergedBits.grpAC


/*** CAN4IDAR3 - MSCAN4 Identifier Acceptance Register 3; 0x00000293 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN4IDAR3STR;
extern volatile CAN4IDAR3STR _CAN4IDAR3 @(REG_BASE + 0x00000293);
#define CAN4IDAR3 _CAN4IDAR3.Byte
#define CAN4IDAR3_AC0 _CAN4IDAR3.Bits.AC0
#define CAN4IDAR3_AC1 _CAN4IDAR3.Bits.AC1
#define CAN4IDAR3_AC2 _CAN4IDAR3.Bits.AC2
#define CAN4IDAR3_AC3 _CAN4IDAR3.Bits.AC3
#define CAN4IDAR3_AC4 _CAN4IDAR3.Bits.AC4
#define CAN4IDAR3_AC5 _CAN4IDAR3.Bits.AC5
#define CAN4IDAR3_AC6 _CAN4IDAR3.Bits.AC6
#define CAN4IDAR3_AC7 _CAN4IDAR3.Bits.AC7
#define CAN4IDAR3_AC _CAN4IDAR3.MergedBits.grpAC


/*** CAN4IDMR0 - MSCAN4 Identifier Mask Register 0; 0x00000294 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN4IDMR0STR;
extern volatile CAN4IDMR0STR _CAN4IDMR0 @(REG_BASE + 0x00000294);
#define CAN4IDMR0 _CAN4IDMR0.Byte
#define CAN4IDMR0_AM0 _CAN4IDMR0.Bits.AM0
#define CAN4IDMR0_AM1 _CAN4IDMR0.Bits.AM1
#define CAN4IDMR0_AM2 _CAN4IDMR0.Bits.AM2
#define CAN4IDMR0_AM3 _CAN4IDMR0.Bits.AM3
#define CAN4IDMR0_AM4 _CAN4IDMR0.Bits.AM4
#define CAN4IDMR0_AM5 _CAN4IDMR0.Bits.AM5
#define CAN4IDMR0_AM6 _CAN4IDMR0.Bits.AM6
#define CAN4IDMR0_AM7 _CAN4IDMR0.Bits.AM7
#define CAN4IDMR0_AM _CAN4IDMR0.MergedBits.grpAM


/*** CAN4IDMR1 - MSCAN4 Identifier Mask Register 1; 0x00000295 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN4IDMR1STR;
extern volatile CAN4IDMR1STR _CAN4IDMR1 @(REG_BASE + 0x00000295);
#define CAN4IDMR1 _CAN4IDMR1.Byte
#define CAN4IDMR1_AM0 _CAN4IDMR1.Bits.AM0
#define CAN4IDMR1_AM1 _CAN4IDMR1.Bits.AM1
#define CAN4IDMR1_AM2 _CAN4IDMR1.Bits.AM2
#define CAN4IDMR1_AM3 _CAN4IDMR1.Bits.AM3
#define CAN4IDMR1_AM4 _CAN4IDMR1.Bits.AM4
#define CAN4IDMR1_AM5 _CAN4IDMR1.Bits.AM5
#define CAN4IDMR1_AM6 _CAN4IDMR1.Bits.AM6
#define CAN4IDMR1_AM7 _CAN4IDMR1.Bits.AM7
#define CAN4IDMR1_AM _CAN4IDMR1.MergedBits.grpAM


/*** CAN4IDMR2 - MSCAN4 Identifier Mask Register 2; 0x00000296 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN4IDMR2STR;
extern volatile CAN4IDMR2STR _CAN4IDMR2 @(REG_BASE + 0x00000296);
#define CAN4IDMR2 _CAN4IDMR2.Byte
#define CAN4IDMR2_AM0 _CAN4IDMR2.Bits.AM0
#define CAN4IDMR2_AM1 _CAN4IDMR2.Bits.AM1
#define CAN4IDMR2_AM2 _CAN4IDMR2.Bits.AM2
#define CAN4IDMR2_AM3 _CAN4IDMR2.Bits.AM3
#define CAN4IDMR2_AM4 _CAN4IDMR2.Bits.AM4
#define CAN4IDMR2_AM5 _CAN4IDMR2.Bits.AM5
#define CAN4IDMR2_AM6 _CAN4IDMR2.Bits.AM6
#define CAN4IDMR2_AM7 _CAN4IDMR2.Bits.AM7
#define CAN4IDMR2_AM _CAN4IDMR2.MergedBits.grpAM


/*** CAN4IDMR3 - MSCAN4 Identifier Mask Register 3; 0x00000297 ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN4IDMR3STR;
extern volatile CAN4IDMR3STR _CAN4IDMR3 @(REG_BASE + 0x00000297);
#define CAN4IDMR3 _CAN4IDMR3.Byte
#define CAN4IDMR3_AM0 _CAN4IDMR3.Bits.AM0
#define CAN4IDMR3_AM1 _CAN4IDMR3.Bits.AM1
#define CAN4IDMR3_AM2 _CAN4IDMR3.Bits.AM2
#define CAN4IDMR3_AM3 _CAN4IDMR3.Bits.AM3
#define CAN4IDMR3_AM4 _CAN4IDMR3.Bits.AM4
#define CAN4IDMR3_AM5 _CAN4IDMR3.Bits.AM5
#define CAN4IDMR3_AM6 _CAN4IDMR3.Bits.AM6
#define CAN4IDMR3_AM7 _CAN4IDMR3.Bits.AM7
#define CAN4IDMR3_AM _CAN4IDMR3.MergedBits.grpAM


/*** CAN4IDAR4 - MSCAN4 Identifier Acceptance Register 4; 0x00000298 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN4IDAR4STR;
extern volatile CAN4IDAR4STR _CAN4IDAR4 @(REG_BASE + 0x00000298);
#define CAN4IDAR4 _CAN4IDAR4.Byte
#define CAN4IDAR4_AC0 _CAN4IDAR4.Bits.AC0
#define CAN4IDAR4_AC1 _CAN4IDAR4.Bits.AC1
#define CAN4IDAR4_AC2 _CAN4IDAR4.Bits.AC2
#define CAN4IDAR4_AC3 _CAN4IDAR4.Bits.AC3
#define CAN4IDAR4_AC4 _CAN4IDAR4.Bits.AC4
#define CAN4IDAR4_AC5 _CAN4IDAR4.Bits.AC5
#define CAN4IDAR4_AC6 _CAN4IDAR4.Bits.AC6
#define CAN4IDAR4_AC7 _CAN4IDAR4.Bits.AC7
#define CAN4IDAR4_AC _CAN4IDAR4.MergedBits.grpAC


/*** CAN4IDAR5 - MSCAN4 Identifier Acceptance Register 5; 0x00000299 ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN4IDAR5STR;
extern volatile CAN4IDAR5STR _CAN4IDAR5 @(REG_BASE + 0x00000299);
#define CAN4IDAR5 _CAN4IDAR5.Byte
#define CAN4IDAR5_AC0 _CAN4IDAR5.Bits.AC0
#define CAN4IDAR5_AC1 _CAN4IDAR5.Bits.AC1
#define CAN4IDAR5_AC2 _CAN4IDAR5.Bits.AC2
#define CAN4IDAR5_AC3 _CAN4IDAR5.Bits.AC3
#define CAN4IDAR5_AC4 _CAN4IDAR5.Bits.AC4
#define CAN4IDAR5_AC5 _CAN4IDAR5.Bits.AC5
#define CAN4IDAR5_AC6 _CAN4IDAR5.Bits.AC6
#define CAN4IDAR5_AC7 _CAN4IDAR5.Bits.AC7
#define CAN4IDAR5_AC _CAN4IDAR5.MergedBits.grpAC


/*** CAN4IDAR6 - MSCAN4 Identifier Acceptance Register 6; 0x0000029A ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN4IDAR6STR;
extern volatile CAN4IDAR6STR _CAN4IDAR6 @(REG_BASE + 0x0000029A);
#define CAN4IDAR6 _CAN4IDAR6.Byte
#define CAN4IDAR6_AC0 _CAN4IDAR6.Bits.AC0
#define CAN4IDAR6_AC1 _CAN4IDAR6.Bits.AC1
#define CAN4IDAR6_AC2 _CAN4IDAR6.Bits.AC2
#define CAN4IDAR6_AC3 _CAN4IDAR6.Bits.AC3
#define CAN4IDAR6_AC4 _CAN4IDAR6.Bits.AC4
#define CAN4IDAR6_AC5 _CAN4IDAR6.Bits.AC5
#define CAN4IDAR6_AC6 _CAN4IDAR6.Bits.AC6
#define CAN4IDAR6_AC7 _CAN4IDAR6.Bits.AC7
#define CAN4IDAR6_AC _CAN4IDAR6.MergedBits.grpAC


/*** CAN4IDAR7 - MSCAN4 Identifier Acceptance Register 7; 0x0000029B ***/
typedef union {
  byte Byte;
  struct {
    byte AC0         :1;                                       /* Acceptance Code Bit 0 */
    byte AC1         :1;                                       /* Acceptance Code Bit 1 */
    byte AC2         :1;                                       /* Acceptance Code Bit 2 */
    byte AC3         :1;                                       /* Acceptance Code Bit 3 */
    byte AC4         :1;                                       /* Acceptance Code Bit 4 */
    byte AC5         :1;                                       /* Acceptance Code Bit 5 */
    byte AC6         :1;                                       /* Acceptance Code Bit 6 */
    byte AC7         :1;                                       /* Acceptance Code Bit 7 */
  } Bits;
  struct {
    byte grpAC   :8;
  } MergedBits;
} CAN4IDAR7STR;
extern volatile CAN4IDAR7STR _CAN4IDAR7 @(REG_BASE + 0x0000029B);
#define CAN4IDAR7 _CAN4IDAR7.Byte
#define CAN4IDAR7_AC0 _CAN4IDAR7.Bits.AC0
#define CAN4IDAR7_AC1 _CAN4IDAR7.Bits.AC1
#define CAN4IDAR7_AC2 _CAN4IDAR7.Bits.AC2
#define CAN4IDAR7_AC3 _CAN4IDAR7.Bits.AC3
#define CAN4IDAR7_AC4 _CAN4IDAR7.Bits.AC4
#define CAN4IDAR7_AC5 _CAN4IDAR7.Bits.AC5
#define CAN4IDAR7_AC6 _CAN4IDAR7.Bits.AC6
#define CAN4IDAR7_AC7 _CAN4IDAR7.Bits.AC7
#define CAN4IDAR7_AC _CAN4IDAR7.MergedBits.grpAC


/*** CAN4IDMR4 - MSCAN4 Identifier Mask Register 4; 0x0000029C ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN4IDMR4STR;
extern volatile CAN4IDMR4STR _CAN4IDMR4 @(REG_BASE + 0x0000029C);
#define CAN4IDMR4 _CAN4IDMR4.Byte
#define CAN4IDMR4_AM0 _CAN4IDMR4.Bits.AM0
#define CAN4IDMR4_AM1 _CAN4IDMR4.Bits.AM1
#define CAN4IDMR4_AM2 _CAN4IDMR4.Bits.AM2
#define CAN4IDMR4_AM3 _CAN4IDMR4.Bits.AM3
#define CAN4IDMR4_AM4 _CAN4IDMR4.Bits.AM4
#define CAN4IDMR4_AM5 _CAN4IDMR4.Bits.AM5
#define CAN4IDMR4_AM6 _CAN4IDMR4.Bits.AM6
#define CAN4IDMR4_AM7 _CAN4IDMR4.Bits.AM7
#define CAN4IDMR4_AM _CAN4IDMR4.MergedBits.grpAM


/*** CAN4IDMR5 - MSCAN4 Identifier Mask Register 5; 0x0000029D ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN4IDMR5STR;
extern volatile CAN4IDMR5STR _CAN4IDMR5 @(REG_BASE + 0x0000029D);
#define CAN4IDMR5 _CAN4IDMR5.Byte
#define CAN4IDMR5_AM0 _CAN4IDMR5.Bits.AM0
#define CAN4IDMR5_AM1 _CAN4IDMR5.Bits.AM1
#define CAN4IDMR5_AM2 _CAN4IDMR5.Bits.AM2
#define CAN4IDMR5_AM3 _CAN4IDMR5.Bits.AM3
#define CAN4IDMR5_AM4 _CAN4IDMR5.Bits.AM4
#define CAN4IDMR5_AM5 _CAN4IDMR5.Bits.AM5
#define CAN4IDMR5_AM6 _CAN4IDMR5.Bits.AM6
#define CAN4IDMR5_AM7 _CAN4IDMR5.Bits.AM7
#define CAN4IDMR5_AM _CAN4IDMR5.MergedBits.grpAM


/*** CAN4IDMR6 - MSCAN4 Identifier Mask Register 6; 0x0000029E ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN4IDMR6STR;
extern volatile CAN4IDMR6STR _CAN4IDMR6 @(REG_BASE + 0x0000029E);
#define CAN4IDMR6 _CAN4IDMR6.Byte
#define CAN4IDMR6_AM0 _CAN4IDMR6.Bits.AM0
#define CAN4IDMR6_AM1 _CAN4IDMR6.Bits.AM1
#define CAN4IDMR6_AM2 _CAN4IDMR6.Bits.AM2
#define CAN4IDMR6_AM3 _CAN4IDMR6.Bits.AM3
#define CAN4IDMR6_AM4 _CAN4IDMR6.Bits.AM4
#define CAN4IDMR6_AM5 _CAN4IDMR6.Bits.AM5
#define CAN4IDMR6_AM6 _CAN4IDMR6.Bits.AM6
#define CAN4IDMR6_AM7 _CAN4IDMR6.Bits.AM7
#define CAN4IDMR6_AM _CAN4IDMR6.MergedBits.grpAM


/*** CAN4IDMR7 - MSCAN4 Identifier Mask Register 7; 0x0000029F ***/
typedef union {
  byte Byte;
  struct {
    byte AM0         :1;                                       /* Acceptance Mask Bit 0 */
    byte AM1         :1;                                       /* Acceptance Mask Bit 1 */
    byte AM2         :1;                                       /* Acceptance Mask Bit 2 */
    byte AM3         :1;                                       /* Acceptance Mask Bit 3 */
    byte AM4         :1;                                       /* Acceptance Mask Bit 4 */
    byte AM5         :1;                                       /* Acceptance Mask Bit 5 */
    byte AM6         :1;                                       /* Acceptance Mask Bit 6 */
    byte AM7         :1;                                       /* Acceptance Mask Bit 7 */
  } Bits;
  struct {
    byte grpAM   :8;
  } MergedBits;
} CAN4IDMR7STR;
extern volatile CAN4IDMR7STR _CAN4IDMR7 @(REG_BASE + 0x0000029F);
#define CAN4IDMR7 _CAN4IDMR7.Byte
#define CAN4IDMR7_AM0 _CAN4IDMR7.Bits.AM0
#define CAN4IDMR7_AM1 _CAN4IDMR7.Bits.AM1
#define CAN4IDMR7_AM2 _CAN4IDMR7.Bits.AM2
#define CAN4IDMR7_AM3 _CAN4IDMR7.Bits.AM3
#define CAN4IDMR7_AM4 _CAN4IDMR7.Bits.AM4
#define CAN4IDMR7_AM5 _CAN4IDMR7.Bits.AM5
#define CAN4IDMR7_AM6 _CAN4IDMR7.Bits.AM6
#define CAN4IDMR7_AM7 _CAN4IDMR7.Bits.AM7
#define CAN4IDMR7_AM _CAN4IDMR7.MergedBits.grpAM


/*** CAN4RXIDR0 - MSCAN4 Receive Identifier Register 0; 0x000002A0 ***/
typedef union {
  byte Byte;
  struct {
    byte ID21        :1;                                       /* Extended format identifier Bit 21 */
    byte ID22        :1;                                       /* Extended format identifier Bit 22 */
    byte ID23        :1;                                       /* Extended format identifier Bit 23 */
    byte ID24        :1;                                       /* Extended format identifier Bit 24 */
    byte ID25        :1;                                       /* Extended format identifier Bit 25 */
    byte ID26        :1;                                       /* Extended format identifier Bit 26 */
    byte ID27        :1;                                       /* Extended format identifier Bit 27 */
    byte ID28        :1;                                       /* Extended format identifier Bit 28 */
  } Bits;
  struct {
    byte grpID_21 :8;
  } MergedBits;
} CAN4RXIDR0STR;
extern volatile CAN4RXIDR0STR _CAN4RXIDR0 @(REG_BASE + 0x000002A0);
#define CAN4RXIDR0 _CAN4RXIDR0.Byte
#define CAN4RXIDR0_ID21 _CAN4RXIDR0.Bits.ID21
#define CAN4RXIDR0_ID22 _CAN4RXIDR0.Bits.ID22
#define CAN4RXIDR0_ID23 _CAN4RXIDR0.Bits.ID23
#define CAN4RXIDR0_ID24 _CAN4RXIDR0.Bits.ID24
#define CAN4RXIDR0_ID25 _CAN4RXIDR0.Bits.ID25
#define CAN4RXIDR0_ID26 _CAN4RXIDR0.Bits.ID26
#define CAN4RXIDR0_ID27 _CAN4RXIDR0.Bits.ID27
#define CAN4RXIDR0_ID28 _CAN4RXIDR0.Bits.ID28
#define CAN4RXIDR0_ID_21 _CAN4RXIDR0.MergedBits.grpID_21
#define CAN4RXIDR0_ID CAN4RXIDR0_ID_21


/*** CAN4RXIDR1 - MSCAN4 Receive Identifier Register 1; 0x000002A1 ***/
typedef union {
  byte Byte;
  struct {
    byte ID15        :1;                                       /* Extended format identifier Bit 15 */
    byte ID16        :1;                                       /* Extended format identifier Bit 16 */
    byte ID17        :1;                                       /* Extended format identifier Bit 17 */
    byte IDE         :1;                                       /* ID Extended */
    byte SRR         :1;                                       /* Substitute Remote Request */
    byte ID18        :1;                                       /* Extended format identifier Bit 18 */
    byte ID19        :1;                                       /* Extended format identifier Bit 19 */
    byte ID20        :1;                                       /* Extended format identifier Bit 20 */
  } Bits;
  struct {
    byte grpID_15 :3;
    byte         :1;
    byte         :1;
    byte grpID_18 :3;
  } MergedBits;
} CAN4RXIDR1STR;
extern volatile CAN4RXIDR1STR _CAN4RXIDR1 @(REG_BASE + 0x000002A1);
#define CAN4RXIDR1 _CAN4RXIDR1.Byte
#define CAN4RXIDR1_ID15 _CAN4RXIDR1.Bits.ID15
#define CAN4RXIDR1_ID16 _CAN4RXIDR1.Bits.ID16
#define CAN4RXIDR1_ID17 _CAN4RXIDR1.Bits.ID17
#define CAN4RXIDR1_IDE _CAN4RXIDR1.Bits.IDE
#define CAN4RXIDR1_SRR _CAN4RXIDR1.Bits.SRR
#define CAN4RXIDR1_ID18 _CAN4RXIDR1.Bits.ID18
#define CAN4RXIDR1_ID19 _CAN4RXIDR1.Bits.ID19
#define CAN4RXIDR1_ID20 _CAN4RXIDR1.Bits.ID20
#define CAN4RXIDR1_ID_15 _CAN4RXIDR1.MergedBits.grpID_15
#define CAN4RXIDR1_ID_18 _CAN4RXIDR1.MergedBits.grpID_18
#define CAN4RXIDR1_ID CAN4RXIDR1_ID_15


/*** CAN4RXIDR2 - MSCAN4 Receive Identifier Register 2; 0x000002A2 ***/
typedef union {
  byte Byte;
  struct {
    byte ID7         :1;                                       /* Extended format identifier Bit 7 */
    byte ID8         :1;                                       /* Extended format identifier Bit 8 */
    byte ID9         :1;                                       /* Extended format identifier Bit 9 */
    byte ID10        :1;                                       /* Extended format identifier Bit 10 */
    byte ID11        :1;                                       /* Extended format identifier Bit 11 */
    byte ID12        :1;                                       /* Extended format identifier Bit 12 */
    byte ID13        :1;                                       /* Extended format identifier Bit 13 */
    byte ID14        :1;                                       /* Extended format identifier Bit 14 */
  } Bits;
  struct {
    byte grpID_7 :8;
  } MergedBits;
} CAN4RXIDR2STR;
extern volatile CAN4RXIDR2STR _CAN4RXIDR2 @(REG_BASE + 0x000002A2);
#define CAN4RXIDR2 _CAN4RXIDR2.Byte
#define CAN4RXIDR2_ID7 _CAN4RXIDR2.Bits.ID7
#define CAN4RXIDR2_ID8 _CAN4RXIDR2.Bits.ID8
#define CAN4RXIDR2_ID9 _CAN4RXIDR2.Bits.ID9
#define CAN4RXIDR2_ID10 _CAN4RXIDR2.Bits.ID10
#define CAN4RXIDR2_ID11 _CAN4RXIDR2.Bits.ID11
#define CAN4RXIDR2_ID12 _CAN4RXIDR2.Bits.ID12
#define CAN4RXIDR2_ID13 _CAN4RXIDR2.Bits.ID13
#define CAN4RXIDR2_ID14 _CAN4RXIDR2.Bits.ID14
#define CAN4RXIDR2_ID_7 _CAN4RXIDR2.MergedBits.grpID_7
#define CAN4RXIDR2_ID CAN4RXIDR2_ID_7


/*** CAN4RXIDR3 - MSCAN4 Receive Identifier Register 3; 0x000002A3 ***/
typedef union {
  byte Byte;
  struct {
    byte RTR         :1;                                       /* Remote Transmission Request */
    byte ID0         :1;                                       /* Extended format identifier Bit 0 */
    byte ID1         :1;                                       /* Extended format identifier Bit 1 */
    byte ID2         :1;                                       /* Extended format identifier Bit 2 */
    byte ID3         :1;                                       /* Extended format identifier Bit 3 */
    byte ID4         :1;                                       /* Extended format identifier Bit 4 */
    byte ID5         :1;                                       /* Extended format identifier Bit 5 */
    byte ID6         :1;                                       /* Extended format identifier Bit 6 */
  } Bits;
  struct {
    byte         :1;
    byte grpID   :7;
  } MergedBits;
} CAN4RXIDR3STR;
extern volatile CAN4RXIDR3STR _CAN4RXIDR3 @(REG_BASE + 0x000002A3);
#define CAN4RXIDR3 _CAN4RXIDR3.Byte
#define CAN4RXIDR3_RTR _CAN4RXIDR3.Bits.RTR
#define CAN4RXIDR3_ID0 _CAN4RXIDR3.Bits.ID0
#define CAN4RXIDR3_ID1 _CAN4RXIDR3.Bits.ID1
#define CAN4RXIDR3_ID2 _CAN4RXIDR3.Bits.ID2
#define CAN4RXIDR3_ID3 _CAN4RXIDR3.Bits.ID3
#define CAN4RXIDR3_ID4 _CAN4RXIDR3.Bits.ID4
#define CAN4RXIDR3_ID5 _CAN4RXIDR3.Bits.ID5
#define CAN4RXIDR3_ID6 _CAN4RXIDR3.Bits.ID6
#define CAN4RXIDR3_ID _CAN4RXIDR3.MergedBits.grpID


/*** CAN4RXDSR0 - MSCAN4 Receive Data Segment Register 0; 0x000002A4 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4RXDSR0STR;
extern volatile CAN4RXDSR0STR _CAN4RXDSR0 @(REG_BASE + 0x000002A4);
#define CAN4RXDSR0 _CAN4RXDSR0.Byte
#define CAN4RXDSR0_DB0 _CAN4RXDSR0.Bits.DB0
#define CAN4RXDSR0_DB1 _CAN4RXDSR0.Bits.DB1
#define CAN4RXDSR0_DB2 _CAN4RXDSR0.Bits.DB2
#define CAN4RXDSR0_DB3 _CAN4RXDSR0.Bits.DB3
#define CAN4RXDSR0_DB4 _CAN4RXDSR0.Bits.DB4
#define CAN4RXDSR0_DB5 _CAN4RXDSR0.Bits.DB5
#define CAN4RXDSR0_DB6 _CAN4RXDSR0.Bits.DB6
#define CAN4RXDSR0_DB7 _CAN4RXDSR0.Bits.DB7
#define CAN4RXDSR0_DB _CAN4RXDSR0.MergedBits.grpDB


/*** CAN4RXDSR1 - MSCAN4 Receive Data Segment Register 1; 0x000002A5 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4RXDSR1STR;
extern volatile CAN4RXDSR1STR _CAN4RXDSR1 @(REG_BASE + 0x000002A5);
#define CAN4RXDSR1 _CAN4RXDSR1.Byte
#define CAN4RXDSR1_DB0 _CAN4RXDSR1.Bits.DB0
#define CAN4RXDSR1_DB1 _CAN4RXDSR1.Bits.DB1
#define CAN4RXDSR1_DB2 _CAN4RXDSR1.Bits.DB2
#define CAN4RXDSR1_DB3 _CAN4RXDSR1.Bits.DB3
#define CAN4RXDSR1_DB4 _CAN4RXDSR1.Bits.DB4
#define CAN4RXDSR1_DB5 _CAN4RXDSR1.Bits.DB5
#define CAN4RXDSR1_DB6 _CAN4RXDSR1.Bits.DB6
#define CAN4RXDSR1_DB7 _CAN4RXDSR1.Bits.DB7
#define CAN4RXDSR1_DB _CAN4RXDSR1.MergedBits.grpDB


/*** CAN4RXDSR2 - MSCAN4 Receive Data Segment Register 2; 0x000002A6 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4RXDSR2STR;
extern volatile CAN4RXDSR2STR _CAN4RXDSR2 @(REG_BASE + 0x000002A6);
#define CAN4RXDSR2 _CAN4RXDSR2.Byte
#define CAN4RXDSR2_DB0 _CAN4RXDSR2.Bits.DB0
#define CAN4RXDSR2_DB1 _CAN4RXDSR2.Bits.DB1
#define CAN4RXDSR2_DB2 _CAN4RXDSR2.Bits.DB2
#define CAN4RXDSR2_DB3 _CAN4RXDSR2.Bits.DB3
#define CAN4RXDSR2_DB4 _CAN4RXDSR2.Bits.DB4
#define CAN4RXDSR2_DB5 _CAN4RXDSR2.Bits.DB5
#define CAN4RXDSR2_DB6 _CAN4RXDSR2.Bits.DB6
#define CAN4RXDSR2_DB7 _CAN4RXDSR2.Bits.DB7
#define CAN4RXDSR2_DB _CAN4RXDSR2.MergedBits.grpDB


/*** CAN4RXDSR3 - MSCAN4 Receive Data Segment Register 3; 0x000002A7 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4RXDSR3STR;
extern volatile CAN4RXDSR3STR _CAN4RXDSR3 @(REG_BASE + 0x000002A7);
#define CAN4RXDSR3 _CAN4RXDSR3.Byte
#define CAN4RXDSR3_DB0 _CAN4RXDSR3.Bits.DB0
#define CAN4RXDSR3_DB1 _CAN4RXDSR3.Bits.DB1
#define CAN4RXDSR3_DB2 _CAN4RXDSR3.Bits.DB2
#define CAN4RXDSR3_DB3 _CAN4RXDSR3.Bits.DB3
#define CAN4RXDSR3_DB4 _CAN4RXDSR3.Bits.DB4
#define CAN4RXDSR3_DB5 _CAN4RXDSR3.Bits.DB5
#define CAN4RXDSR3_DB6 _CAN4RXDSR3.Bits.DB6
#define CAN4RXDSR3_DB7 _CAN4RXDSR3.Bits.DB7
#define CAN4RXDSR3_DB _CAN4RXDSR3.MergedBits.grpDB


/*** CAN4RXDSR4 - MSCAN4 Receive Data Segment Register 4; 0x000002A8 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4RXDSR4STR;
extern volatile CAN4RXDSR4STR _CAN4RXDSR4 @(REG_BASE + 0x000002A8);
#define CAN4RXDSR4 _CAN4RXDSR4.Byte
#define CAN4RXDSR4_DB0 _CAN4RXDSR4.Bits.DB0
#define CAN4RXDSR4_DB1 _CAN4RXDSR4.Bits.DB1
#define CAN4RXDSR4_DB2 _CAN4RXDSR4.Bits.DB2
#define CAN4RXDSR4_DB3 _CAN4RXDSR4.Bits.DB3
#define CAN4RXDSR4_DB4 _CAN4RXDSR4.Bits.DB4
#define CAN4RXDSR4_DB5 _CAN4RXDSR4.Bits.DB5
#define CAN4RXDSR4_DB6 _CAN4RXDSR4.Bits.DB6
#define CAN4RXDSR4_DB7 _CAN4RXDSR4.Bits.DB7
#define CAN4RXDSR4_DB _CAN4RXDSR4.MergedBits.grpDB


/*** CAN4RXDSR5 - MSCAN4 Receive Data Segment Register 5; 0x000002A9 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4RXDSR5STR;
extern volatile CAN4RXDSR5STR _CAN4RXDSR5 @(REG_BASE + 0x000002A9);
#define CAN4RXDSR5 _CAN4RXDSR5.Byte
#define CAN4RXDSR5_DB0 _CAN4RXDSR5.Bits.DB0
#define CAN4RXDSR5_DB1 _CAN4RXDSR5.Bits.DB1
#define CAN4RXDSR5_DB2 _CAN4RXDSR5.Bits.DB2
#define CAN4RXDSR5_DB3 _CAN4RXDSR5.Bits.DB3
#define CAN4RXDSR5_DB4 _CAN4RXDSR5.Bits.DB4
#define CAN4RXDSR5_DB5 _CAN4RXDSR5.Bits.DB5
#define CAN4RXDSR5_DB6 _CAN4RXDSR5.Bits.DB6
#define CAN4RXDSR5_DB7 _CAN4RXDSR5.Bits.DB7
#define CAN4RXDSR5_DB _CAN4RXDSR5.MergedBits.grpDB


/*** CAN4RXDSR6 - MSCAN4 Receive Data Segment Register 6; 0x000002AA ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4RXDSR6STR;
extern volatile CAN4RXDSR6STR _CAN4RXDSR6 @(REG_BASE + 0x000002AA);
#define CAN4RXDSR6 _CAN4RXDSR6.Byte
#define CAN4RXDSR6_DB0 _CAN4RXDSR6.Bits.DB0
#define CAN4RXDSR6_DB1 _CAN4RXDSR6.Bits.DB1
#define CAN4RXDSR6_DB2 _CAN4RXDSR6.Bits.DB2
#define CAN4RXDSR6_DB3 _CAN4RXDSR6.Bits.DB3
#define CAN4RXDSR6_DB4 _CAN4RXDSR6.Bits.DB4
#define CAN4RXDSR6_DB5 _CAN4RXDSR6.Bits.DB5
#define CAN4RXDSR6_DB6 _CAN4RXDSR6.Bits.DB6
#define CAN4RXDSR6_DB7 _CAN4RXDSR6.Bits.DB7
#define CAN4RXDSR6_DB _CAN4RXDSR6.MergedBits.grpDB


/*** CAN4RXDSR7 - MSCAN4 Receive Data Segment Register 7; 0x000002AB ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4RXDSR7STR;
extern volatile CAN4RXDSR7STR _CAN4RXDSR7 @(REG_BASE + 0x000002AB);
#define CAN4RXDSR7 _CAN4RXDSR7.Byte
#define CAN4RXDSR7_DB0 _CAN4RXDSR7.Bits.DB0
#define CAN4RXDSR7_DB1 _CAN4RXDSR7.Bits.DB1
#define CAN4RXDSR7_DB2 _CAN4RXDSR7.Bits.DB2
#define CAN4RXDSR7_DB3 _CAN4RXDSR7.Bits.DB3
#define CAN4RXDSR7_DB4 _CAN4RXDSR7.Bits.DB4
#define CAN4RXDSR7_DB5 _CAN4RXDSR7.Bits.DB5
#define CAN4RXDSR7_DB6 _CAN4RXDSR7.Bits.DB6
#define CAN4RXDSR7_DB7 _CAN4RXDSR7.Bits.DB7
#define CAN4RXDSR7_DB _CAN4RXDSR7.MergedBits.grpDB


/*** CAN4RXDLR - MSCAN4 Receive Data Length Register; 0x000002AC ***/
typedef union {
  byte Byte;
  struct {
    byte DLC0        :1;                                       /* Data Length Code Bit 0 */
    byte DLC1        :1;                                       /* Data Length Code Bit 1 */
    byte DLC2        :1;                                       /* Data Length Code Bit 2 */
    byte DLC3        :1;                                       /* Data Length Code Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDLC  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN4RXDLRSTR;
extern volatile CAN4RXDLRSTR _CAN4RXDLR @(REG_BASE + 0x000002AC);
#define CAN4RXDLR _CAN4RXDLR.Byte
#define CAN4RXDLR_DLC0 _CAN4RXDLR.Bits.DLC0
#define CAN4RXDLR_DLC1 _CAN4RXDLR.Bits.DLC1
#define CAN4RXDLR_DLC2 _CAN4RXDLR.Bits.DLC2
#define CAN4RXDLR_DLC3 _CAN4RXDLR.Bits.DLC3
#define CAN4RXDLR_DLC _CAN4RXDLR.MergedBits.grpDLC


/*** CAN4TXIDR0 - MSCAN4 Transmit Identifier Register 0; 0x000002B0 ***/
typedef union {
  byte Byte;
  struct {
    byte ID21        :1;                                       /* Extended format identifier Bit 21 */
    byte ID22        :1;                                       /* Extended format identifier Bit 22 */
    byte ID23        :1;                                       /* Extended format identifier Bit 23 */
    byte ID24        :1;                                       /* Extended format identifier Bit 24 */
    byte ID25        :1;                                       /* Extended format identifier Bit 25 */
    byte ID26        :1;                                       /* Extended format identifier Bit 26 */
    byte ID27        :1;                                       /* Extended format identifier Bit 27 */
    byte ID28        :1;                                       /* Extended format identifier Bit 28 */
  } Bits;
  struct {
    byte grpID_21 :8;
  } MergedBits;
} CAN4TXIDR0STR;
extern volatile CAN4TXIDR0STR _CAN4TXIDR0 @(REG_BASE + 0x000002B0);
#define CAN4TXIDR0 _CAN4TXIDR0.Byte
#define CAN4TXIDR0_ID21 _CAN4TXIDR0.Bits.ID21
#define CAN4TXIDR0_ID22 _CAN4TXIDR0.Bits.ID22
#define CAN4TXIDR0_ID23 _CAN4TXIDR0.Bits.ID23
#define CAN4TXIDR0_ID24 _CAN4TXIDR0.Bits.ID24
#define CAN4TXIDR0_ID25 _CAN4TXIDR0.Bits.ID25
#define CAN4TXIDR0_ID26 _CAN4TXIDR0.Bits.ID26
#define CAN4TXIDR0_ID27 _CAN4TXIDR0.Bits.ID27
#define CAN4TXIDR0_ID28 _CAN4TXIDR0.Bits.ID28
#define CAN4TXIDR0_ID_21 _CAN4TXIDR0.MergedBits.grpID_21
#define CAN4TXIDR0_ID CAN4TXIDR0_ID_21


/*** CAN4TXIDR1 - MSCAN4 Transmit Identifier Register 1; 0x000002B1 ***/
typedef union {
  byte Byte;
  struct {
    byte ID15        :1;                                       /* Extended format identifier Bit 15 */
    byte ID16        :1;                                       /* Extended format identifier Bit 16 */
    byte ID17        :1;                                       /* Extended format identifier Bit 17 */
    byte IDE         :1;                                       /* ID Extended */
    byte SRR         :1;                                       /* Substitute Remote Request */
    byte ID18        :1;                                       /* Extended format identifier Bit 18 */
    byte ID19        :1;                                       /* Extended format identifier Bit 19 */
    byte ID20        :1;                                       /* Extended format identifier Bit 20 */
  } Bits;
  struct {
    byte grpID_15 :3;
    byte         :1;
    byte         :1;
    byte grpID_18 :3;
  } MergedBits;
} CAN4TXIDR1STR;
extern volatile CAN4TXIDR1STR _CAN4TXIDR1 @(REG_BASE + 0x000002B1);
#define CAN4TXIDR1 _CAN4TXIDR1.Byte
#define CAN4TXIDR1_ID15 _CAN4TXIDR1.Bits.ID15
#define CAN4TXIDR1_ID16 _CAN4TXIDR1.Bits.ID16
#define CAN4TXIDR1_ID17 _CAN4TXIDR1.Bits.ID17
#define CAN4TXIDR1_IDE _CAN4TXIDR1.Bits.IDE
#define CAN4TXIDR1_SRR _CAN4TXIDR1.Bits.SRR
#define CAN4TXIDR1_ID18 _CAN4TXIDR1.Bits.ID18
#define CAN4TXIDR1_ID19 _CAN4TXIDR1.Bits.ID19
#define CAN4TXIDR1_ID20 _CAN4TXIDR1.Bits.ID20
#define CAN4TXIDR1_ID_15 _CAN4TXIDR1.MergedBits.grpID_15
#define CAN4TXIDR1_ID_18 _CAN4TXIDR1.MergedBits.grpID_18
#define CAN4TXIDR1_ID CAN4TXIDR1_ID_15


/*** CAN4TXIDR2 - MSCAN4 Transmit Identifier Register 2; 0x000002B2 ***/
typedef union {
  byte Byte;
  struct {
    byte ID7         :1;                                       /* Extended format identifier Bit 7 */
    byte ID8         :1;                                       /* Extended format identifier Bit 8 */
    byte ID9         :1;                                       /* Extended format identifier Bit 9 */
    byte ID10        :1;                                       /* Extended format identifier Bit 10 */
    byte ID11        :1;                                       /* Extended format identifier Bit 11 */
    byte ID12        :1;                                       /* Extended format identifier Bit 12 */
    byte ID13        :1;                                       /* Extended format identifier Bit 13 */
    byte ID14        :1;                                       /* Extended format identifier Bit 14 */
  } Bits;
  struct {
    byte grpID_7 :8;
  } MergedBits;
} CAN4TXIDR2STR;
extern volatile CAN4TXIDR2STR _CAN4TXIDR2 @(REG_BASE + 0x000002B2);
#define CAN4TXIDR2 _CAN4TXIDR2.Byte
#define CAN4TXIDR2_ID7 _CAN4TXIDR2.Bits.ID7
#define CAN4TXIDR2_ID8 _CAN4TXIDR2.Bits.ID8
#define CAN4TXIDR2_ID9 _CAN4TXIDR2.Bits.ID9
#define CAN4TXIDR2_ID10 _CAN4TXIDR2.Bits.ID10
#define CAN4TXIDR2_ID11 _CAN4TXIDR2.Bits.ID11
#define CAN4TXIDR2_ID12 _CAN4TXIDR2.Bits.ID12
#define CAN4TXIDR2_ID13 _CAN4TXIDR2.Bits.ID13
#define CAN4TXIDR2_ID14 _CAN4TXIDR2.Bits.ID14
#define CAN4TXIDR2_ID_7 _CAN4TXIDR2.MergedBits.grpID_7
#define CAN4TXIDR2_ID CAN4TXIDR2_ID_7


/*** CAN4TXIDR3 - MSCAN4 Transmit Identifier Register 3; 0x000002B3 ***/
typedef union {
  byte Byte;
  struct {
    byte RTR         :1;                                       /* Remote Transmission Request */
    byte ID0         :1;                                       /* Extended format identifier Bit 0 */
    byte ID1         :1;                                       /* Extended format identifier Bit 1 */
    byte ID2         :1;                                       /* Extended format identifier Bit 2 */
    byte ID3         :1;                                       /* Extended format identifier Bit 3 */
    byte ID4         :1;                                       /* Extended format identifier Bit 4 */
    byte ID5         :1;                                       /* Extended format identifier Bit 5 */
    byte ID6         :1;                                       /* Extended format identifier Bit 6 */
  } Bits;
  struct {
    byte         :1;
    byte grpID   :7;
  } MergedBits;
} CAN4TXIDR3STR;
extern volatile CAN4TXIDR3STR _CAN4TXIDR3 @(REG_BASE + 0x000002B3);
#define CAN4TXIDR3 _CAN4TXIDR3.Byte
#define CAN4TXIDR3_RTR _CAN4TXIDR3.Bits.RTR
#define CAN4TXIDR3_ID0 _CAN4TXIDR3.Bits.ID0
#define CAN4TXIDR3_ID1 _CAN4TXIDR3.Bits.ID1
#define CAN4TXIDR3_ID2 _CAN4TXIDR3.Bits.ID2
#define CAN4TXIDR3_ID3 _CAN4TXIDR3.Bits.ID3
#define CAN4TXIDR3_ID4 _CAN4TXIDR3.Bits.ID4
#define CAN4TXIDR3_ID5 _CAN4TXIDR3.Bits.ID5
#define CAN4TXIDR3_ID6 _CAN4TXIDR3.Bits.ID6
#define CAN4TXIDR3_ID _CAN4TXIDR3.MergedBits.grpID


/*** CAN4TXDSR0 - MSCAN4 Transmit Data Segment Register 0; 0x000002B4 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4TXDSR0STR;
extern volatile CAN4TXDSR0STR _CAN4TXDSR0 @(REG_BASE + 0x000002B4);
#define CAN4TXDSR0 _CAN4TXDSR0.Byte
#define CAN4TXDSR0_DB0 _CAN4TXDSR0.Bits.DB0
#define CAN4TXDSR0_DB1 _CAN4TXDSR0.Bits.DB1
#define CAN4TXDSR0_DB2 _CAN4TXDSR0.Bits.DB2
#define CAN4TXDSR0_DB3 _CAN4TXDSR0.Bits.DB3
#define CAN4TXDSR0_DB4 _CAN4TXDSR0.Bits.DB4
#define CAN4TXDSR0_DB5 _CAN4TXDSR0.Bits.DB5
#define CAN4TXDSR0_DB6 _CAN4TXDSR0.Bits.DB6
#define CAN4TXDSR0_DB7 _CAN4TXDSR0.Bits.DB7
#define CAN4TXDSR0_DB _CAN4TXDSR0.MergedBits.grpDB


/*** CAN4TXDSR1 - MSCAN4 Transmit Data Segment Register 1; 0x000002B5 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4TXDSR1STR;
extern volatile CAN4TXDSR1STR _CAN4TXDSR1 @(REG_BASE + 0x000002B5);
#define CAN4TXDSR1 _CAN4TXDSR1.Byte
#define CAN4TXDSR1_DB0 _CAN4TXDSR1.Bits.DB0
#define CAN4TXDSR1_DB1 _CAN4TXDSR1.Bits.DB1
#define CAN4TXDSR1_DB2 _CAN4TXDSR1.Bits.DB2
#define CAN4TXDSR1_DB3 _CAN4TXDSR1.Bits.DB3
#define CAN4TXDSR1_DB4 _CAN4TXDSR1.Bits.DB4
#define CAN4TXDSR1_DB5 _CAN4TXDSR1.Bits.DB5
#define CAN4TXDSR1_DB6 _CAN4TXDSR1.Bits.DB6
#define CAN4TXDSR1_DB7 _CAN4TXDSR1.Bits.DB7
#define CAN4TXDSR1_DB _CAN4TXDSR1.MergedBits.grpDB


/*** CAN4TXDSR2 - MSCAN4 Transmit Data Segment Register 2; 0x000002B6 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4TXDSR2STR;
extern volatile CAN4TXDSR2STR _CAN4TXDSR2 @(REG_BASE + 0x000002B6);
#define CAN4TXDSR2 _CAN4TXDSR2.Byte
#define CAN4TXDSR2_DB0 _CAN4TXDSR2.Bits.DB0
#define CAN4TXDSR2_DB1 _CAN4TXDSR2.Bits.DB1
#define CAN4TXDSR2_DB2 _CAN4TXDSR2.Bits.DB2
#define CAN4TXDSR2_DB3 _CAN4TXDSR2.Bits.DB3
#define CAN4TXDSR2_DB4 _CAN4TXDSR2.Bits.DB4
#define CAN4TXDSR2_DB5 _CAN4TXDSR2.Bits.DB5
#define CAN4TXDSR2_DB6 _CAN4TXDSR2.Bits.DB6
#define CAN4TXDSR2_DB7 _CAN4TXDSR2.Bits.DB7
#define CAN4TXDSR2_DB _CAN4TXDSR2.MergedBits.grpDB


/*** CAN4TXDSR3 - MSCAN4 Transmit Data Segment Register 3; 0x000002B7 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4TXDSR3STR;
extern volatile CAN4TXDSR3STR _CAN4TXDSR3 @(REG_BASE + 0x000002B7);
#define CAN4TXDSR3 _CAN4TXDSR3.Byte
#define CAN4TXDSR3_DB0 _CAN4TXDSR3.Bits.DB0
#define CAN4TXDSR3_DB1 _CAN4TXDSR3.Bits.DB1
#define CAN4TXDSR3_DB2 _CAN4TXDSR3.Bits.DB2
#define CAN4TXDSR3_DB3 _CAN4TXDSR3.Bits.DB3
#define CAN4TXDSR3_DB4 _CAN4TXDSR3.Bits.DB4
#define CAN4TXDSR3_DB5 _CAN4TXDSR3.Bits.DB5
#define CAN4TXDSR3_DB6 _CAN4TXDSR3.Bits.DB6
#define CAN4TXDSR3_DB7 _CAN4TXDSR3.Bits.DB7
#define CAN4TXDSR3_DB _CAN4TXDSR3.MergedBits.grpDB


/*** CAN4TXDSR4 - MSCAN4 Transmit Data Segment Register 4; 0x000002B8 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4TXDSR4STR;
extern volatile CAN4TXDSR4STR _CAN4TXDSR4 @(REG_BASE + 0x000002B8);
#define CAN4TXDSR4 _CAN4TXDSR4.Byte
#define CAN4TXDSR4_DB0 _CAN4TXDSR4.Bits.DB0
#define CAN4TXDSR4_DB1 _CAN4TXDSR4.Bits.DB1
#define CAN4TXDSR4_DB2 _CAN4TXDSR4.Bits.DB2
#define CAN4TXDSR4_DB3 _CAN4TXDSR4.Bits.DB3
#define CAN4TXDSR4_DB4 _CAN4TXDSR4.Bits.DB4
#define CAN4TXDSR4_DB5 _CAN4TXDSR4.Bits.DB5
#define CAN4TXDSR4_DB6 _CAN4TXDSR4.Bits.DB6
#define CAN4TXDSR4_DB7 _CAN4TXDSR4.Bits.DB7
#define CAN4TXDSR4_DB _CAN4TXDSR4.MergedBits.grpDB


/*** CAN4TXDSR5 - MSCAN4 Transmit Data Segment Register 5; 0x000002B9 ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4TXDSR5STR;
extern volatile CAN4TXDSR5STR _CAN4TXDSR5 @(REG_BASE + 0x000002B9);
#define CAN4TXDSR5 _CAN4TXDSR5.Byte
#define CAN4TXDSR5_DB0 _CAN4TXDSR5.Bits.DB0
#define CAN4TXDSR5_DB1 _CAN4TXDSR5.Bits.DB1
#define CAN4TXDSR5_DB2 _CAN4TXDSR5.Bits.DB2
#define CAN4TXDSR5_DB3 _CAN4TXDSR5.Bits.DB3
#define CAN4TXDSR5_DB4 _CAN4TXDSR5.Bits.DB4
#define CAN4TXDSR5_DB5 _CAN4TXDSR5.Bits.DB5
#define CAN4TXDSR5_DB6 _CAN4TXDSR5.Bits.DB6
#define CAN4TXDSR5_DB7 _CAN4TXDSR5.Bits.DB7
#define CAN4TXDSR5_DB _CAN4TXDSR5.MergedBits.grpDB


/*** CAN4TXDSR6 - MSCAN4 Transmit Data Segment Register 6; 0x000002BA ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4TXDSR6STR;
extern volatile CAN4TXDSR6STR _CAN4TXDSR6 @(REG_BASE + 0x000002BA);
#define CAN4TXDSR6 _CAN4TXDSR6.Byte
#define CAN4TXDSR6_DB0 _CAN4TXDSR6.Bits.DB0
#define CAN4TXDSR6_DB1 _CAN4TXDSR6.Bits.DB1
#define CAN4TXDSR6_DB2 _CAN4TXDSR6.Bits.DB2
#define CAN4TXDSR6_DB3 _CAN4TXDSR6.Bits.DB3
#define CAN4TXDSR6_DB4 _CAN4TXDSR6.Bits.DB4
#define CAN4TXDSR6_DB5 _CAN4TXDSR6.Bits.DB5
#define CAN4TXDSR6_DB6 _CAN4TXDSR6.Bits.DB6
#define CAN4TXDSR6_DB7 _CAN4TXDSR6.Bits.DB7
#define CAN4TXDSR6_DB _CAN4TXDSR6.MergedBits.grpDB


/*** CAN4TXDSR7 - MSCAN4 Transmit Data Segment Register 7; 0x000002BB ***/
typedef union {
  byte Byte;
  struct {
    byte DB0         :1;                                       /* Data Bit 0 */
    byte DB1         :1;                                       /* Data Bit 1 */
    byte DB2         :1;                                       /* Data Bit 2 */
    byte DB3         :1;                                       /* Data Bit 3 */
    byte DB4         :1;                                       /* Data Bit 4 */
    byte DB5         :1;                                       /* Data Bit 5 */
    byte DB6         :1;                                       /* Data Bit 6 */
    byte DB7         :1;                                       /* Data Bit 7 */
  } Bits;
  struct {
    byte grpDB   :8;
  } MergedBits;
} CAN4TXDSR7STR;
extern volatile CAN4TXDSR7STR _CAN4TXDSR7 @(REG_BASE + 0x000002BB);
#define CAN4TXDSR7 _CAN4TXDSR7.Byte
#define CAN4TXDSR7_DB0 _CAN4TXDSR7.Bits.DB0
#define CAN4TXDSR7_DB1 _CAN4TXDSR7.Bits.DB1
#define CAN4TXDSR7_DB2 _CAN4TXDSR7.Bits.DB2
#define CAN4TXDSR7_DB3 _CAN4TXDSR7.Bits.DB3
#define CAN4TXDSR7_DB4 _CAN4TXDSR7.Bits.DB4
#define CAN4TXDSR7_DB5 _CAN4TXDSR7.Bits.DB5
#define CAN4TXDSR7_DB6 _CAN4TXDSR7.Bits.DB6
#define CAN4TXDSR7_DB7 _CAN4TXDSR7.Bits.DB7
#define CAN4TXDSR7_DB _CAN4TXDSR7.MergedBits.grpDB


/*** CAN4TXDLR - MSCAN4 Transmit Data Length Register; 0x000002BC ***/
typedef union {
  byte Byte;
  struct {
    byte DLC0        :1;                                       /* Data Length Code Bit 0 */
    byte DLC1        :1;                                       /* Data Length Code Bit 1 */
    byte DLC2        :1;                                       /* Data Length Code Bit 2 */
    byte DLC3        :1;                                       /* Data Length Code Bit 3 */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
  struct {
    byte grpDLC  :4;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} CAN4TXDLRSTR;
extern volatile CAN4TXDLRSTR _CAN4TXDLR @(REG_BASE + 0x000002BC);
#define CAN4TXDLR _CAN4TXDLR.Byte
#define CAN4TXDLR_DLC0 _CAN4TXDLR.Bits.DLC0
#define CAN4TXDLR_DLC1 _CAN4TXDLR.Bits.DLC1
#define CAN4TXDLR_DLC2 _CAN4TXDLR.Bits.DLC2
#define CAN4TXDLR_DLC3 _CAN4TXDLR.Bits.DLC3
#define CAN4TXDLR_DLC _CAN4TXDLR.MergedBits.grpDLC


/*** CAN4TXTBPR - MSCAN4 Transmit Transmit Buffer Priority; 0x000002BF ***/
typedef union {
  byte Byte;
  struct {
    byte PRIO0       :1;                                       /* Transmit Buffer Priority Bit 0 */
    byte PRIO1       :1;                                       /* Transmit Buffer Priority Bit 1 */
    byte PRIO2       :1;                                       /* Transmit Buffer Priority Bit 2 */
    byte PRIO3       :1;                                       /* Transmit Buffer Priority Bit 3 */
    byte PRIO4       :1;                                       /* Transmit Buffer Priority Bit 4 */
    byte PRIO5       :1;                                       /* Transmit Buffer Priority Bit 5 */
    byte PRIO6       :1;                                       /* Transmit Buffer Priority Bit 6 */
    byte PRIO7       :1;                                       /* Transmit Buffer Priority Bit 7 */
  } Bits;
  struct {
    byte grpPRIO :8;
  } MergedBits;
} CAN4TXTBPRSTR;
extern volatile CAN4TXTBPRSTR _CAN4TXTBPR @(REG_BASE + 0x000002BF);
#define CAN4TXTBPR _CAN4TXTBPR.Byte
#define CAN4TXTBPR_PRIO0 _CAN4TXTBPR.Bits.PRIO0
#define CAN4TXTBPR_PRIO1 _CAN4TXTBPR.Bits.PRIO1
#define CAN4TXTBPR_PRIO2 _CAN4TXTBPR.Bits.PRIO2
#define CAN4TXTBPR_PRIO3 _CAN4TXTBPR.Bits.PRIO3
#define CAN4TXTBPR_PRIO4 _CAN4TXTBPR.Bits.PRIO4
#define CAN4TXTBPR_PRIO5 _CAN4TXTBPR.Bits.PRIO5
#define CAN4TXTBPR_PRIO6 _CAN4TXTBPR.Bits.PRIO6
#define CAN4TXTBPR_PRIO7 _CAN4TXTBPR.Bits.PRIO7
#define CAN4TXTBPR_PRIO _CAN4TXTBPR.MergedBits.grpPRIO


/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte UNSEC       :1;                                       /* Unsecure */
    byte CLKSW       :1;                                       /* Clock switch */
    byte TRACE       :1;                                       /* TRACE1 BDM firmware command is being executed */
    byte SDV         :1;                                       /* Shift data valid */
    byte ENTAG       :1;                                       /* Tagging enable */
    byte BDMACT      :1;                                       /* BDM active status */
    byte ENBDM       :1;                                       /* Enable BDM */
  } Bits;
} BDMSTSSTR;
extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01);
#define BDMSTS _BDMSTS.Byte
#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC
#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW
#define BDMSTS_TRACE _BDMSTS.Bits.TRACE
#define BDMSTS_SDV _BDMSTS.Bits.SDV
#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG
#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT
#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM


/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/
typedef union {
  byte Byte;
  struct {
    byte CCR0        :1;                                       /* BDM CCR Holding Bit 0 */
    byte CCR1        :1;                                       /* BDM CCR Holding Bit 1 */
    byte CCR2        :1;                                       /* BDM CCR Holding Bit 2 */
    byte CCR3        :1;                                       /* BDM CCR Holding Bit 3 */
    byte CCR4        :1;                                       /* BDM CCR Holding Bit 4 */
    byte CCR5        :1;                                       /* BDM CCR Holding Bit 5 */
    byte CCR6        :1;                                       /* BDM CCR Holding Bit 6 */
    byte CCR7        :1;                                       /* BDM CCR Holding Bit 7 */
  } Bits;
  struct {
    byte grpCCR  :8;
  } MergedBits;
} BDMCCRSTR;
extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06);
#define BDMCCR _BDMCCR.Byte
#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0
#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1
#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2
#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3
#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4
#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5
#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6
#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7
#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR


/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte REG11       :1;                                       /* Internal register map position */
    byte REG12       :1;                                       /* Internal register map position */
    byte REG13       :1;                                       /* Internal register map position */
    byte REG14       :1;                                       /* Internal register map position */
    byte REG15       :1;                                       /* Internal register map position */
  } Bits;
  struct {
    byte         :1;
    byte         :1;
    byte         :1;
    byte grpREG_11 :5;
  } MergedBits;
} BDMINRSTR;
extern volatile BDMINRSTR _BDMINR @(0x0000FF07);
#define BDMINR _BDMINR.Byte
#define BDMINR_REG11 _BDMINR.Bits.REG11
#define BDMINR_REG12 _BDMINR.Bits.REG12
#define BDMINR_REG13 _BDMINR.Bits.REG13
#define BDMINR_REG14 _BDMINR.Bits.REG14
#define BDMINR_REG15 _BDMINR.Bits.REG15
#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11
#define BDMINR_REG BDMINR_REG_11


  /* Watchdog reset macro */
#ifdef _lint
  #define __RESET_WATCHDOG()  /* empty */
#else
  #define __RESET_WATCHDOG() {asm sta COPCTL;}  /* Just write a byte to feed the dog */
#endif

#endif

/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 03.33 for 
**     the Motorola HCS12 series of microcontrollers.
**
** ###################################################################
*/

